Shift Registers

REGISTERS
• A register is a digital circuit with two basic
functions: Data Storage and Data Shifting
– A shift register provides the data movement function
– A shift register “shifts” its output once every clock
cycle

• A shift register is a group of flip-flops set up in a

linear fashion with their inputs and outputs
connected together in such a way that the data
is shifted from one device to another when the
circuit is active
2
 Data Shifting
• The bits in a shift register can shift in any of the following
manners

3
 Data Shifting
• Block diagrams for shift registers with various
input/output options:

n-bit shift
register n-bit shift
register

n-bit shift
register n-bit shift
register

4
 Shift Register Characteristics
• Direction
– Left shift
– Right shift
– Rotate (right or left)
– Bidirectional
• Types n-bit shift
register
– Serial-in, Serial-out
– Serial-in, Parallel-out
– Parallel-in, Serial-out
– Parallel-in, Parallel-out
– Universal
5
 Serial-In Serial-Out

n-bit shift
register

6
Serial-In Serial-Out

7
Serial-In Serial-Out

8
 Serial-to-Parallel Conversion

n-bit shift
register

9
Parallel-to-Serial Conversion

n-bit shift register

10
Parallel-to-Serial Conversion
Parallel-to-Serial Conversion
PARALLEL Shift/load’ CLK (QA QB QC QD) SERIAL DATA
DATA IN OUT
ABCD (WHEN
SHIFT=1)
0000 0
0101 0 1 0101 1(MSB)
1 2 0010 0
1 3 0001 1
1 4 0000 0(LSB)
0000 0
1101 0 5 1101 1(MSB)
1 6 1110 0
1 7 1111 1
1 8 1111 1(LSB)
 Parallel-In Parallel-Out

DATA CLK DATA OUT

IN (QA QB QC QD)
ABCD
0000
0101 1 0101
0000
0110 2 0110
0000
1010 3 1010

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Bidirectional Shift Registers
 Universal Shift Register
A B C D

LIN
RIN
S1 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0
S0

D Q D Q D Q D Q
A B C D
C C C C
CLR CLR CLR CLR

CK

CLR_L

QA QB QC QD
15
Ring Counter
Johnson Counters
 COUNTERS
ASYNCHRONOUS SYNCHRONOUS
Flip-flops are connected in such a No connection between output of
way that output of first flip-flop first flip-flop and clock input of next
drives the clock for the next flip-flop. flip-flop.

All the flip-flops are not clocked All the flip-flops are clocked
simultaneously. simultaneously.

Logic circuit is simple even for more Design involves complex logic circuit
number of states. as number of states increases.

Main drawback is their low speed as As the clock is simultaneously given

the clock is propagated through to all flip-flops there is no problem
number of flip-flops before it of propagation delay.
reaches last flip-flop.
Asynchronous Up counter
Asynchronous Down counter
 Counters with MOD NUMBER < 2N

MOD-6 counter produced by clearing a MOD-8 counter when a count of six

occurs.
An asynchronously clocked decade counter with asynchronous recycling.
 Synchronous Counter Design
1. Determine desired number of bits (flip-flops)
required to build the counter
2. Write the excitation table for flip-flop.
3. Determine the transition table listing all PRESENT
states and their NEXT states.
4. Add a column for each flip-flop input.
5. Simplify the expressions for flip-flop inputs using
K-maps.
6. Implement the final expressions using flip-flops
and external logic gates.
 3-bit synchronous UP counter
Present state Next state Flip-flop inputs
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
EXCITATION/APPLICATION TABLE

Qn Qn+1 J K
0 0 0 X
FLIP-FLOP INPUTS:
0 1 1 X
J2 = K2 = Q1.Q0
1 0 X 1
1 1 X 0 J1 = K1 = Q0

J0 = K0 = 1
3-bit synchronous UP counter.
Timing diagram for the SYNCHRONOUS UP COUNTER

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