80386 Architecture

Salient Features
• First 32-bit microprocessor in the x86 family
• 80286 architecture expanded for 32 bit operation
• 32-bit Processor
• 32-bit ALU, 32-bit Registers, 32-bit Data Bus, 32-bit
Address Bus
• Uses 32-bit address for memory and 16-bit address
for I/O ports
• Maximum physical memory 4 Gb.
• Maximum number of I/O ports 64 K.
• Built-in Memory Management Unit to support
Segmentation, Paging and Virtual Memory.
 Features of 80386DX
• It supports 8/16/32 bit data operands
• It has 32-bit internal registers
• It supports 32-bit data bus and 32-bit non-
multiplexed address bus
• It supports
– Physical Address of 4GB
– Virtual Address of 64TB
– Maximum Segment size of 4GB
 Features of 80386DX
• It operates in 3 different modes
– Real
– Protected
– Virtual 8086
• MMU provides virtual memory, paging and 4
levels of protection
• Clock Frequency : 16 MHz,20MHz,25 MHz and
33MHz
• It has 132 pin package
 Features of 80386 (cont.)
• Pipelined architecture.
• It can operate on 17 different data types.
• Prefetch unit permits 80386dx to prefetch
upto 16 bytes of instruction code.
• It support numeric support with 80387co-
processor.
• FEATURES OF 80386:
• Two versions of 80386 are commonly available:
1) 80386DX 2)80386SX
• 80386DX 80386SX
1) 32 bit address bus 1) 24 bit address
bus 32bit data bus 16 bit data bus
2) Packaged in 132 pin ceramic 2) 100 pin flat
pin grid array(PGA) package
3) Address 4GB of memory 3) 16 MB of
Memory
80386DX Functional Block Diagram
Architecture of 80386

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Architecture of 80386

Three Sections:
Bus Interface units
Central Processing
Unit
Memory
10
Management Unit
 Architecture of 80386
• The internal architecture of 80386 is divided
into three sections:
1. Central Processing Unit
2. Memory Management Unit
3. Bus Interface unit

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 Bus Interface Unit
• It has a prioritizer to resolve
the priority of various bus
requests. This controls the
access of the bus
• The address driver drives
the bus enable and address
signals A2 – A31.
• The pipeline/bus size unit
handles the control signals
for pipelining and dynamic
bus sizing units 12
 Bus Interface Unit
• The data buffers interface the internal data
bus with system bus

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Central Processing Unit

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 Central Processing Unit
• The CPU is further divided into:
– Instruction Unit
– Execution Unit
• Instruction Unit:
– It decodes the opcode bytes received from the 16-
byte instruction queue and arranges them into a
3-decoded instruction queue.
– After decoding it is passed to control section for
deriving necessary control signals
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 Central Processing Unit
• Execution Unit:
– It has 8 general purpose and 8 special purpose
registers which either handles data or addresses
– The 64-bit barrel shifter increases the speed of all
shift, rotate, multiply and divide operations
– The multiply/divide logic implements the bit-shift-
rotate algorithms to complete the operations in
minimum time(Even 32bit multiplication is done in
1µs)

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 Central Processing Unit
• Element of the EU
– Arithmetic/logic unit (ALU)
• Performs the operation identified by ADD, SUB, AND, etc.
– Flags register
• Holds status and control information
– General-purpose registers
• Holds address or data information
– Control ROM
• Contains microcode sequences that define operations
performed by machine instructions
– Special multiply, shift, and barrel shift hardware
• Accelerate multiply, divide, and rotate operations 17
 Central Processing Unit
• Execution reads the decoded instruction from
the instruction queue and performs the
operations that are specified.
• During the execution of an instruction ,it
requests the segment and page units to
generate operand addresses and the bus
interface unit to perform read or write bus
cycles to access data in memory or I/O devices.
Memory Management Unit

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 Memory Management Unit
• MMU consists of a segmentation unit and paging
unit
• Segmentation Unit:
– It allows the use of two address components -
segment and offset – for relocability and sharing of
code and data
– It allows a maximum segment size of 4GB
– It provides a 4-level protection mechanism for
protecting and isolating system’s code and data from
those of application program
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 Memory Management Unit
– The limit and attribute PLA checks segment limits
and attributes at segment level to avoid invalid
accesses to code and data in memory segment.
• Paging Unit
– It organizes physical memory in terms of pages of
4KB size
– It works under the control of segmentation unit
– It converts linear addresses into physical addresses
– The control and attribute PLA checks privileges at
page level.

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 Register Overview
• The Intel386 DX has 32 register resources in
the following categories:
– General Purpose Registers
– Segment Registers
– Instruction Pointer and Flags
– Control Registers
– System Address Registers
– Debug Registers
– Test Registers
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General Purpose Registers
8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

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 General Purpose Registers
• hold data or address values.
• support data of 1, 8, 16, 32 and 64 bits.
• 32-bit registers : EAX, EBX, ECX, EDX, ESI, EDI,
EBP, and ESP.
• The least significant 16 bits of the registers can
be accessed as in 8086 with names of the
registers AX, BX, CX, DX, SI, DI, BP, and SP.

24
 General Purpose Registers
• When accessed as a 16-bit operand, the upper
16 bits of the register are neither used nor
changed.
• 8-bit operations can be performed with AL,
BL, CL and DL.
• The higher bytes are AH, BH, CH and DH
• The individual byte accessibility offers
flexibility for data operations.

25
Segment Registers

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 Segment Registers
• The segment registers
– CS indicates the current code segment
– SS indicates the current stack segment
– DS, ES, FS and GS indicate four current data
segments.
• On any data reference the DS-pointed data
segment is assumed by default.

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Instruction Pointer

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 Instruction Pointer
• It is a 32-bit register named EIP.
• EIP holds the offset of the next instruction to
be executed.
• The offset is always relative to the base of the
code segment (CS).
• The lower 16 bits of EIP contain the 16-bit
instruction pointer named IP, which is used by
16-bit addressing.

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Flag Register

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• Bit 17 (VM Bit, Virtual Mode):
– VM bit is set to work in Virtual 8086 mode
• Bit 16 (RF Bit, Resume Flag):
– RF flag is used with debug register breakpoints.
– When RF is set, debug fault need to be ignored on
the next instruction.
– RF is then automatically reset after every
instruction

31
 Flag Register
• Bit 15 : Reserved
• Bit 14 (NT Bit, Nested Task):
– This flag applies to Protected Mode.
– NT is set to indicate that the execution of this task
is nested within another task.
– If set, it indicates that the current nested task's
Task State Segment (TSS) has a valid back link to
the previous task's TSS.

32
• Bit 13,12 (IOPL Bit, Input/output Privilege):
– maximum CPL (current privilege level) value
permitted to execute I/O instructions without
generating an exception 13 fault or consulting the
I/O Permission Bitmap.

33
• Bit 11 (OF Bit, Overflow Flag):
– OF is set if the operation resulted in a signed
overflow.
• Bit 10 (DF Bit, Direction Flag):
– DF defines whether ESI/EDI registers decrement
or increment during th string instructions.
– increment occurs if DF is reset.
– decrement occurs if DF is set.

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 Flag Register
• Bit 9 (IF Bit, Interrupt Enable Flag):
– When IF =1 the processor allows recognition of
external interrupts on INTR pin
• Bit 8 (TF Bit, Trap Enable Flag):
– When TF =1 the processor enables the single step
mode for debugging.
• Bit 7 (SF Bit, Sign Flag):
– SF is set if the high-order bit of the result is set, it
is reset otherwise.
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 Flag Register
• Bit 6 (ZF bit, Zero Flag):
– ZF is set if all bits of the result are 0.
•  Bit 4 (AF Bit, Auxiliary Carry Flag):
– The Auxiliary Flag is used to simplify the addition
and subtraction of packed BCD numbers.
– AF is set if the operation resulted in a carry out of
bit 3 (addition) or a borrow into bit 3
(subtraction). Otherwise AF is reset.
– AF is only for bit 3.
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 Flag Register
• Bit 2 (PF Bit, Parity Flag):
– PF is set for even parity.
• Bit 0 (CF Bit, Carry Flag):
– CF is set for 8-, 16- or 32-bit operations if it results
in a carry out of (addition), or a borrow into
(subtraction) the high-order bit.

37
 Control Registers
• Intel386 DX has 3 control registers(CR0, CR2
and CR3) of 32 bits to hold machine state of a
global nature.
• These registers along with System Address
Registers hold machine state that affects all
tasks in the system
• To access Control Registers, load and store
instructions are defined

38
 CR0 : Machine Control Register
• CR0 contains 6 defined bits for control and
status purposes.
• The low-order 16 bits of CR0 is defined as
Machine Status Word
• To operate only on the low-order 16-bits of
CR0, LMSW and SMSW instructions are used.
• For 32-bit operations the system should use
MOV CR0, Reg instruction.

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 CR0 : Machine Control Register

• Bit 31 (PG Bit, Paging Enable) : The PG bit is

set to enable the on-chip paging unit.
• Bit 4 (Reserved) : This bit is reserved by Intel.

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 CR0 : Machine Control Register
• Bit 3 (TS Bit, Task Switched) : TS is
automatically set whenever a task switch
operation is performed.
• Bit 2 (EM Bit, Emulate Coprocessor) :
• Bit 1 (MP Bit, Monitor Coprocessor) :

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 CR0 : Machine Control Register
• Bit 0 (PE Bit, Protection Enable) :
– PE =1, enable the Protected Mode.
– If PE =0, processor operates in Real Mode.

42
 CR1 : Reserved
• CR1 is reserved for use in future Intel
processors

43
 CR2 : Page Fault Linear Address
• CR2 holds the 32-bit linear address that
caused the last page fault detected.

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CR3 : Page Directory Base Address

• CR3 contains the physical base address of the

page directory table.
• The Intel386 DX page directory table is always
page-aligned (4 Kbyte-aligned).
• Thus the lowest twelve bits of CR3 are ignored.
•  A task switch through a TSS invalidates all page
table entries in paging unit cache.
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 System Address Registers
• Four special registers are defined to reference
the tables.
• These tables or segments are:
– GDT (Global Descriptor Table)
– IDT (Interrupt Descriptor Table)
– LDT (Local Descriptor Table)
– TSS (Task State Segment)

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 System Address Registers
• The addresses of these tables and segments
are stored in special registers, the System
Address and System Segment Registers.
• These registers are named GDTR, IDTR, LDTR
and TR, respectively

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 GDTR and IDTR

• These registers hold:

– 32-bit linear base address and
– 16-bit limit
of GDT and IDT respectively.
• GDT and IDT segments are global to all tasks in
the system.
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 LDTR and TR
• These registers hold 16-
bit selector for
– LDT descriptor and
– TSS descriptor
• Since they are task
specific, they are defined
by selector values stored
in system segment
registers.

49
 LDTR and TR
• A system descriptor
register, which is not
visible to programmer, is
associated with each
system segment register

50
Segment Registers
 System Tables(Descriptor Tables)
• GDT (Global Descriptor Table),
• IDT (Interrupt Descriptor Table),
• LDT (Local Descriptor Table),
• TSS (Task State Segment).
System Segment Registers
 How Segment Descriptor is accessed?

Used to select one

of the 8192
segment
descriptors that
reside in the GDT
or LDT
 Segment selector
 In Real mode 16 bit segment registers hold the
starting address of the segment.
 In Protected mode these segment registers are used
as segment selector because it selects a segment
descriptor.
 Segment descriptor is a structure of 8 bytes that is
used to describe and locate segment present in
memory from descriptor table.
 Selector is used to index(point) a descriptor from the
table of descriptors.
Descriptor Table Registers
 Segment base
Global Descriptor Table (GDT), & GDTR address (32 bit)

GDT
Segment Descriptor n Offset
(32bit)

Segment register
Segment Descriptor 1 +
Selector
Segment Descriptor 0

GDTR NULL Descriptor

Base Address Limit - 1 Linear address
(32bit)
 Global Descriptor Table
• The Global Descriptor Table (GDT) contains
descriptors which are possibly available to all
of the tasks in a system.
• The GDT can contain any type of segment
descriptor except for descriptors which are
used for servicing interrupts (i.e. interrupt and
trap descriptors).
• Every Intel386 DX system contains a GDT
 Contd.
• Generally the GDT contains code and data
segments used by the operating systems and task state
segments, and descriptors for the LDTs in a system.
• GDT contains descriptors for segments which
are common to all tasks.
• The first entry in GDT is reserved it should contain all
zeros. Such a descriptor is called as Null Descriptor.
• Any access that is made using null selector will
generate an exception defines a null pointer value.
 Local Descriptor Table & LDTR
Physical Memory

Descriptor 1
LDT
Descriptor 0

LDTR selector LDT Descriptor

LIMIT
2

GDTR BASE 1
 Local Descriptor Table
• LDTs contain descriptors which are associated
with a given task.
• Generally, operating systems are designed
so that each task has a separate LDT.
• The LDT may contain only code, data, stack,
task gate, and call gate descriptors.
• There can be 0 or many LDTs.
 LDTR
• The visible portion of the LDT register contains
only a 16-bit selector.
• This selector refers to a Local Descriptor Table
descriptor in the GDT.
• LDTs provide a mechanism for isolating a given
task's code and data segments from the rest
of the operating system
 Interrupt Descriptor Table &IDTR
• IDT contains group of descriptors that define the
interrupts or exception handling routines.
• For 80386 to work in protected mode at least one IDT
needs to be defined.
• The IDT contains the descriptors which point to the
location of up to 256 interrupt service routine.
• IDT may contain only Task gate, Interrupt gate and
Trap gate Descriptors.
• Every interrupt used by the system must have an entry
in the IDT.
 Interrupt Descriptor Table &IDTR
Physical Memory
Interrupt Descriptor Table Register
256

255
47 40 39 16 15 0 254

BASE31-24 BASE23-0 LIMIT

IDT

3
2
1
 Debug Registers
• Debugging of 80386 allows data access
breakpoints as well as code execution
breakpoints.
• 80386 contains 6 debug registers to specify
– 4 breakpoints
– Breakpoint Control options
– Breakpoint Status
Debug Registers

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 Linear Breakpoint Address
Registers
• Breakpoint addresses are 32-bit linear
addresses
• While debugging, Intel 386 h/w continuously
compares the linear breakpoint addresses in
DR0-DR3 with the linear addresses generated
by executing software.

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 Debug Control Register

• LENi(i=0 - 3): Breakpoint Length Specification

Bits:
• 2 bit field for each breakpoint
• Specifies length of breakpoint fields
• The choices of data breakpoints are 1byte,
2bytes & 4bytes
• For instruction execution breakpoint, the
length is 1(beginning byte address)
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LENi Encoding
 Debug Control Register

• RWi(i=0 - 3): Memory Access Qualifier Bit

• 2 bit field for each breakpoint
• Specifies the type of usage which must occur to
activate the associated breakpoint

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 Debug Control Register

• GD: Global Debug Register Access Detect

• Debug registers can only be accessed in real
mode or at privilege level 0 in protected
mode
• GD bit, when set, provides extra protection
against any Debug Register access even in
Real Mode or at privilege level 0 in
Protected Mode.
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 Debug Control Register

• GE and LE bit: Exact data breakpoint match,

global and local
• If either GE or LE is set, any data breakpoint trap will be
reported exactly after completion of the instruction that
caused the operand transfer.
• LE bit is cleared during task switch and is used for task-
local breakpoints.
• GE bit is unaffected during a task switch and remain
enabled during all tasks executing in the system.
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 Debug Control Register

• Gi and Li(i=0 - 3): Breakpoint Enable, global and

local
• If either Gi and Li is set then the associated
breakpoint is enabled.

73
 Debug Status Register
• A Debug Status Register allows the exception 1
handler to easily determine why it was invoked.
• It can be invoked as a result of one of several
events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.
 Debug Status Register

• Bi : Debug fault/trap due to breakpoint 0 -3

• Four breakpoint indicator flags, B0-B3,
correspond one-to-one with the breakpoint
registers in DR0-DR3.
• A flag Bi is set when the condition described
by DRi, LENi, and RWi occurs.

75
 Debug Status Register

• BD : Debug fault due to attempted register

access when GD bit is set
• This bit is set if the exception 1 handler was
invoked due to an instruction attempting to
read or write to the debug registers when
GD bit was set.

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 Debug Status Register

• BS : Debug trap due to single step

• This bit is set if the exception 1 handler was
invoked due to the TF bit in the flag register
being set

77
 Debug Status Register

• BT : Debug trap due to task switch

• This bit is set if the exception 1 handler was
invoked due to a task switch occurring to a
task having an Intel386 DX TSS with the T
bit set.

78
 Test Registers

• They are used to control the testing of

Translation Look-aside Buffer of Intel386 DX.

79
 Data Types
• The Intel386 DX supports all of the data types
commonly used in high level languages:
• Bit: A single bit quantity.
• Bit Field: A group of upto 32 contiguous bits,
which spans a maximum of four bytes.

80
 Data Types
• Bit String: A set of contiguous bits, on the
Intel386 DX bit strings can be up to 4 gigabits
long.

• Byte: A signed
8-bit quantity
(range -128 to+127)
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 Data Types
• Unsigned Byte: An
unsigned 8-bit quantity.
(range 0 to 255)
• Integer (Word): A signed
16-bit quantity.
(-32768 to 32767)
• Long Integer (Double
Word):
– A signed 32-bit quantity.
(-2.147*109 to + 2.147*109 )
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 Data Types
• Unsigned Integer (Word): An unsigned 16-bit
quantity.(0 to65535)

• Unsigned Long Integer (Double Word): An

unsigned 32-bit quantity.(0 to 4294967295)

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 Data Types
• Signed Quad Word: A signed 64-bit quantity.

• Unsigned Quad Word: An unsigned 64-bit

quantity.

84
 Data Types
• Offset: A 16- or 32-bit offset only quantity
which indirectly references another memory
location.

85
 Data Types
• Pointer: A full pointer which consists of a 16-
bit segment selector and either a 16- or 32-bit
offset.

86
 Data Types
• Char: A byte representation of an ASCII
Alphanumeric or control character.

• String: A contiguous sequence of bytes, words

or dwords. A string may contain between 1
byte and 4 GB.

87
 Data Types
• BCD: A byte (unpacked) representation of
decimal digits 0±9.

• Packed BCD: A byte (packed) representation

of two decimal digits 0±9 storing one digit in
each nibble.

88
 Data Types
• When 80386 DX is coupled with 387 Numeric
Coprocessor then the following common
floating point types are supported.
• Floating Point: A signed 32-, 64-, or 80-bit real
number representation.

89
• References:
• Intel i386 manual