Lecture Notes

Insulated Gate Bipolar Transistors (IGBTs)

Outline
• Construction and I-V characteristics
• Physical operation
• Switching characteristics
• Limitations and safe operating area
• PSPICE simulation models

Copyright © by John Wiley & Sons 2003 IGBTs - 1

 Multi-cell Structure of IGBT
• IGBT = insulated gate bipolar transistor.
contact to source
emitter
diffusion
conductor
field
oxide

gate
oxide

gate
width
N
+ N+ N+ N
+
P P
N-
buffer layer
N+ (not essential)
+
P collector
metallization
gate
conductor

Copyright © by John Wiley & Sons 2003 IGBTs - 2

 Cross-section of IGBT Cell
gate
emitter
SiO
2 + +
J N N
3 P
Ls
J
2
-
N
+
N
+
P

J - Unique feature of IGBT collector

1 Buffer layer
Parasitic thyristor (not essential)

• Cell structure similar to power MOSFET (VDMOS) cell.

• P-region at collector end unique feature of IGBT compared to MOSFET.
• Punch-through (PT) IGBT - N+ buffer layer present.
• Non-punch-through (NPT) IGBT - N+ buffer layer absent.
Copyright © by John Wiley & Sons 2003 IGBTs - 3
 Cross-section of Trench-Gate IGBT Unit Cell
Emitter

boddy-source short
Oxide

N+ N+
Gate
Channel
• Non-punch-thru IGBT
P conductor P
length
Parasitic
I N- ID
SCR D

+
P

Collector

Emitter

boddy-source short
Oxide

N+ N+
Gate
Channel
P conductor P
length • Punch-thru IGBT
Parasitic
I N- I
SCR D D
N+
+
P

Collector

Copyright © by John Wiley & Sons 2003 IGBTs - 4

 IGBT I-V Characteristics and Circuit Symbols
increasing V
i GE
C i
v C
GE4
• No Buffer Layer
v GE3
VRM ≈ BV
CES
v
• With Buffer Layer v V GE
GE2 GE(th)
v
V ≈0 GE1
RM • Transfer curve
v
CE
V BV
RM • Output characteristics CES

drain collector

gate
gate • N-channel IGBT circuit symbols

source
emitter

Copyright © by John Wiley & Sons 2003 IGBTs - 5

 Blocking (Off) State Operation of IGBT
gate
emitter
SiO
2 + +
J N N
3 P
Ls
J
2
N-
+
N
P+

J - Unique feature of IGBT collector Buffer layer

1 (not essential)
Parasitic thyristor

• Blocking state operation - V GE < V GE(th) • With N+ buffer layer, junction J 1 has
• J unction J 2 is blocking junction - n+ drift small breakdownvoltage and thus IGBT
region holds depletion layer of blocking has little reverse blocking capability -
junction. anti-symmetric IGBT

• Without N+ buffer layer, IGBT has large

• Buffer layer speeds up device turn-off
reverse blocking capability - so-called
symmetric IGBT

Copyright © by John Wiley & Sons 2003 IGBTs - 6

 IGBT On-state Operation
gate
emitter

+ +
N N

P • MOSFET section designed

lateral (spreading)
N
- to carry most of the IGBT
resistance
+
collector current
N

+ + + + + + + + +
P

collector • On-state V CE(on) =

gate
V J 1 + Vdrift + ICRchannel
emitter

+ +
N N

P • Hole injection into drift

N
- region from J 1 minimizes
N
+
V drift .
P+

collector

Copyright © by John Wiley & Sons 2003 IGBTs - 7

 Approximate Equivalent Circuits for IGBTs

Conduction path resulting collector

drift region
resistance in thyristor turn-on (IGBT
V latchup) if current in this
V J1
drift path is too large

gate
I R gate
C channel

Principal
(desired) Body region
path of spreading
resistance
• Approximate equivalent circuit for collector
IGBT valid for normal operating current emitter
conditions.
• IGBT equivalent circuit showing
• V CE(on) = VJ 1 + V drift + IC Rchannel transistors comprising the parasitic
thyristor.
Copyright © by John Wiley & Sons 2003 IGBTs - 8
 Static Latchup of IGBTs
lateral (spreading)
resistance gate
J emitter
3

+ +
N N

J2 N-
+
N
J 1
+ + + P+ + + + +

collector
Conduction paths causing lateral voltage drops and turn-on
of parasitic thyristor if current in this path is too large

• Lateral voltage drops, if too large, will forward bias junction J3.
• Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor.
• Large power dissipation in latchup will destroy IGBT unless terminated quickly.
External circuit must terminate latchup - no gate control in latchup.

Copyright © by John Wiley & Sons 2003 IGBTs - 9

 Dynamic Latchup Mechanism in IGBTs
J emitter gate
3

+ +
N N

J
2 P

lateral
(spreading) expansion of
resistance N- depletion region
+
N
J 1
P+
collector

• MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into
N- layer, the base region of the pnp BJT.
• Expansion of depletion layer reduces base width of pnp BJT and its a increases.
• More injected holes survive traversal of drift region and become “collected” at junction J2.
• Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and
latchup soon occurs.
• Manufacturers usually specify maximum allowable drain current on basis of dynamic
latchup.

Copyright © by John Wiley & Sons 2003 IGBTs - 10

 Internal Capacitances Vs Spec Sheet Capacitances

C gc C
bridge
G C
+V -
C ge Cce b

E C gc
Bridge balanced (Vb=0) Cbridge = C gc = C res
G C

G C
Cies

E
C oes

Cies = C ge + C gc E

C oes = C gc + Cce

Copyright © by John Wiley & Sons 2003 IGBTs - 11

 IGBT Turn-on Waveforms

v (t) V
GE GG+
• Turn-on waveforms for
IGBT embedded in a t
stepdown converter.

• Very similar to turn-on t

waveforms of MOSFETs. d(on)
Io
• Contributions to t vf2 . i (t)
C
t
• Increase in Cge of t
ri
MOSFET section at low
collector-emitter
V
voltages. V CE(on)
DD
• Slower turn-on of pnp v (t)
CE
BJT section. t t
fv1
t fv2

Copyright © by John Wiley & Sons 2003 IGBTs - 12

 IGBT Turn-off Waveforms
• Turn-off waveforms for IGBT
V embedded in a stepdown
GE(th V
GG- converter.
)
v (t)
GE
t • Current “tailing” (t fi2 ) due to
stored charge trapped in drift
region (base of pnp BJ T) by rapid
turn-off of MOSFET section.
t
fi2 MOSFET
current • Shorten tailing interval by either
t d(off)
reducing carrier lifetime or by
BJT
i (t)
t current putting N+ buffer layer adjacent to
C
rv t
t injecting P+ layer at drain.
fi1

• Buffer layer acts as a sink for

excess holes otherwise trapped
V
DD in drift region becasue lifetime in
t buffer layer can be made small
v (t) without effecting on-state losses -
CE
buffer layer thin compared to drift
region.
Copyright © by John Wiley & Sons 2003 IGBTs - 13
 IGBT Safe Operating Area

• Maximum collector-emitter
i voltages set by breakdown
C
voltage of pnp transistor -
2500 v devices available.
-5
10 sec

-4 • Maximum collector current set

10 sec
FBSOA by latchup considerations - 100
A devices can conduct 1000 A
DC
v
for 10 µsec and still turn-off
CE via gate control.
dv
i re-applied CE
C
dt
1000 V/ s
μ • Maximum junction temp. = 150
C.
2000 V/ s
μ

RBSOA 3000 V/ μs • Manufacturer specifies a

maximum rate of increase of
v
CE re-applied collector-emitter
voltage in order to avoid latchup.

Copyright © by John Wiley & Sons 2003 IGBTs - 14

 Development of PSpice IGBT Model
Cm
gate
source Coxs

Coxd
+ +
N N
Cgdj
P

Ccer Cdsj
-
Drain-body or N
+ Rb
base-collector N
Cebj + Cebd
depletion layer +
P

drain

• Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer. • Reference - "An
Experimentally Verified
• Nonlinear capacitor Cebj + Cebd due to P+N+ junction IGBT Model
Implemented in the
• MOSFET and PNP BJT are intrinsic (no parasitics) devices SABER Circuit
Simulator", Allen R.
• Nonlinear resistor Rb due to conductivity modulation of N - drain drift region of Hefner, Jr. and Daniel
MOSFET portion. M. Diebolt, IEEE Trans.
on Power Electronics,
• Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N -P junction). Vol. 9, No. 5, pp. 532-
542, (Sept., 1994)
• Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.

Copyright © by John Wiley & Sons 2003 IGBTs - 15

 Parameter Estimation for PSpice IGBT Model
• Built-in IGBT model requires nine parameter values.
• Parameters described in Help files of Parts utility program.

• Parts utility program guides users through parameter estimation process.

• IGBT specification sheets provided by manufacturer provide sufficient
informaiton for general purpose simulations.
• Detailed accurate simulations, for example device dissipation studies, may
require the user to carefully characterize the selected IGBTs.
Drain

Cebj +
Cgdj Cebd • Built-in model does not model
Ccer ultrafast IGBTs with buffer
Coxd Rb
layers (punch-through IGBTs) or
Gate Cdsj
reverse free-wheeling diodes
Cm +
Coxs
Source
Copyright © by John Wiley & Sons 2003 IGBTs - 16
 PSpice IGBT - Simulation Vs Experiment

0V 5V 10 V 15 V 20 V 25 V
1
nF
Data from IXGH40N60 spec sheet

Simulated CGC versus VCE

0.75
nF for IXGH40N60

V =0V
GE

0.5
nF

0.25
nF

0
100 V 200 V 300 V 400 V 500 V
Collector - emitter Voltage

Copyright © by John Wiley & Sons 2003 IGBTs - 17