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Introduction
Cont..
 Different Modeling techniques
A module can be described in any one (or a combination) of the
following modeling techniques.
 Gate-level modeling using instantiation of primitive gates and user defined
modules.
 This describes the circuit by specifying the gates and how they are connected with each
other.
 Dataflow modeling using continuous assignment statements with the keyword
assign.
 This is mostly used for describing combinational circuits.
 Behavioral modeling using procedural assignment statements with keyword
always.
 This is used to describe digital systems at a higher level of abstraction.
 Gate-Level or Structural Modeling

 Here a circuit is specified by its logic gates and their interconnections.

 It provides a textual description of a schematic diagram.
 Verilog recognizes 12 basic gates as predefined primitives.
 4 primitive gates of 3-state type.
 Other 8 are: and, nand, or, nor, xor, xnor, not, buf
 1-bit Full Adder
//Gate-level hierarchical description
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
endmodule

module fulladder (S,C,x,y,z);

input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the half adders
halfadder HA1(S1,D1,x,y);
halfadder HA2(S,D2,S1,z);
or g1(C,D2,D1);
endmodule
 4-bit Full Adder
module _4bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries

//Instantiate the full adder

fulladder FA0 (S[0],C1,A[0],B[0],C0),
FA1 (S[1],C2,A[1],B[1],C1),
FA2 (S[2],C3,A[2],B[2],C2),
FA3 (S[3],C4,A[3],B[3],C3);
endmodule
 Dataflow Modeling

 Dataflow modeling uses a number of operators that act on operands to produce

desired results.
 Verilog HDL provides about 30 operator types.
 Dataflow modeling uses continuous assignments and the keyword assign.
 A continuous assignment is a statement that assigns a value to a net.
 The value assigned to the net is specified by an expression that uses operands
and operators.
 A wire should be assigned only once using continuous assignment.
 Only combinational logic can be modeled using Continuous Assignment
 Dataflow Modeling

//Dataflow description of a 2-to-4-line decoder

module decoder_df (A,B,E,D);
input A,B,E;
output [0:3] D;
assign D[0] = ~(~A & ~B & ~E),
D[1] = ~(~A & B & ~E),
D[2] = ~(A & ~B & ~E),
D[3] = ~(A & B & ~E);
endmodule

A 2-to-1 line multiplexer with data inputs A and B,

select input S, and output Y is described with the
continuous assignment
assign Y = (A & S) | (B & ~S)
 Behavioral Modeling

 Behavioral modeling represents digital circuits at a functional and algorithmic

level.
 It is used mostly to describe sequential circuits, but can also be used to describe
combinational circuits.
 Behavioral descriptions use the keyword always followed by a list of procedural
assignment statements.
 The target output of procedural assignment statements must be of the reg data
type.
 A reg data type retains its value until a new value is assigned.
 Procedural Assignment can drive only reg, integer, real and time data type.
Which means left-side data type cannot be nets.
 Procedural Assignment should appear inside procedures.
 Behavioral Modeling
 The procedural assignment statements inside the always block are executed every time there is
a change in any of the variable listed after the @ symbol. (Note that there is no “;” at the end of
always statement)

//Behavioral description of 2-to-1-line multiplexer

module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @(select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
 Special Language Tokens
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Useful for,
 gate instances and procedural statements
 unnecessary in RTL specification
$<identifier>: System tasks and functions
 $time
 $stop
 $finish

 $monitor

#<delay specification>
 System Tasks
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Display tasks
 $display : Displays the entire list at the time when statement is encountered
 $monitor : Whenever there is a change in any argument, displays the entire list at end
of time step

Simulation Control Task

 $finish : makes the simulator to exit
 $stop : suspends the simulation

Time
 $time: gives the simulation time
 Compiler Directives
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• Compiler directive are defined by using `<keyword>

construct.
• `define
• `include

• Verilog compiler substitutes the text of the macro/file

wherever it encounters a `<macro_name>.
Operator Types
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14
 Logical Operators
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&&  logical AND

||  logical OR
!  logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x
• Result is ONE bit value: 0, 1 or x
• If A = 0; B = 20; Find
• A && B
• A || B
• !A
• !B
 Bitwise Operators
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&  bitwise AND

|  bitwise OR
~  bitwise NOT
^  bitwise XOR
~^ or ^~  bitwise XNOR

• Operation on bit by bit basis

 Bitwise Operators
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c = a & b;
c = ~a;

a = 4’b1010;
b = 4’b1100;

c = a ^ b;

a = 4’b1010;
b = 2’b11;

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 Reduction Operators
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&  AND
|  OR
^  XOR
~&  NAND
~|  NOR
~^ or ^~  XNOR

• One multi-bit operand  One single-bit result

a = 4’b1001;
c = |a; // c = 1|0|0|1 = 1

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 Shift Operators
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>>  shift right

<<  shift left

• Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2;// d = 0010
c = a << 1; // c = 0100

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 Concatenation, Replication
Operators 20

• Concatenation
• {op1, op2, ..}  concatenates op1, op2, .. to single number
• Operands must be sized !!
catx = {a, b, c};
caty = {b, 2’b11, a};

• Replication
repl = {4{a}, b, 2{c}};
 Relational Operators
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>  greater than

<  less than
>=  greater or equal than
<=  less or equal than
• Result is one bit value: 0, 1 or x
• A= 3’b100 B = 3’b11
• A <= B ???
• A >= B ???

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 Equality Operators
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==  logical equality
Return 0, 1 or x
!=  logical inequality
===  case equality
!==  case inequality

• A = 3’b001; B = 2’b01; A == B?

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 Conditional Operator
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cond_expr ? true_expr :
false_expr

• eg: 2-to-1 mux ..(concurrent statement)

A
1
Y
B Y = (sel)? A : B;
0
sel

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Operator Precedence
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Use parentheses to
enforce your
priority

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 Operator Example
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module operator_eg(x,y,f1,f2);
input x,y;
output f1,f2;
wire [9:0] x,y;
wire [4:0]f1;
wire f2;
assign f1= x[4:0] & y[4:0];
assign f2= x[2] | f1[3];
assign f2= ~& x;
assign f1= f2 ? x[9:5] : x[4:0];
endmodule
Integer Arithmetic
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 Reference
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Text Book:
 Bhasker, Jayaram. A verilog HDL primer. Star Galaxy Publishing, 1999.
ModelSim Software
 https://www.mentor.com/company/higher_ed/modelsim-student-edition
THANK YOU

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