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    vushwarj
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    System reset can be either active low or active high. Verilog system tasks include $display to print data at an instant, $monitor to continuously monitor and print variable changes, and $strobe to print data after a statement executes. Timing diagrams show the clock, stable values, transitions, and high-impedance states. Signal conventions include using lowercase 'n' for active low signals and prefixes like 'H' for AHB and 'P' for APB bus signals.

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    sv_reset_pins

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    System reset can be either active low or active high. Verilog system tasks include $display to print data at an instant, $monitor to continuously monitor and print variable changes, and $strobe to print data after a statement executes. Timing diagrams show the clock, stable values, transitions, and high-impedance states. Signal conventions include using lowercase 'n' for active low signals and prefixes like 'H' for AHB and 'P' for APB bus signals.

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    7 views4 pages

    SV Reset Pins

    Uploaded by

    vushwarj
    System reset can be either active low or active high. Verilog system tasks include $display to print data at an instant, $monitor to continuously monitor and print variable changes, and $strobe to print data after a statement executes. Timing diagrams show the clock, stable values, transitions, and high-impedance states. Signal conventions include using lowercase 'n' for active low signals and prefixes like 'H' for AHB and 'P' for APB bus signals.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    System reset

    Reset PINS
    • Active Low Reset
    Active High “reset” input goes high (more
    +ve) to reset the circuit.
    • Active High Reset
    Active Low “reset” input goes low (more -ve) to
    reset the circuit.
    Verilog system tasks
    • $display:: It mainly prints the data or variable as it is
    at that instant of that time.
    • $monitor:: As from the name it is clear that It will
    monitor the data or variable for which it is written
    and whenever the variable changes it will print the
    changed value.
    • $strobe:: It prints the variable or data after the
    execution of the statement for which it is written. It
    means it prints the changed variable or after the
    operation, it got active for that statement.
    Key to timing diagram conventions

    • Timing diagrams
    – Clock
    – Stable values
    – Transitions
    – High-impedance

    • Signal conventions
    – Lower case ‘n’ denote
    active low (e.g. RESETn)
    – Prefix ‘H’ denotes AHB
    – Prefix ‘P’ denotes APB
    4

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