Logic Gates

06/21/20 1
 AND
 In order for current to flow, both switches
must be closed
¤ Logic notation AB = C
(Sometimes AB = C)

A B C
0 0 0
0 1 0
1 0 0
1 1 1
06/21/20 2
 OR
 Current flows if either switch is closed
¤ Logic notation A + B = C

A B C
0 0 0
0 1 1
1 0 1
1 1 1
06/21/20 3
 Properties of AND and OR
 Commutation
¤A+B=B+A
¤AB=BA

Same as

Same as

06/21/20 4
 Properties of AND and OR
 Associative Property
¤ A + (B + C) = (A + B) + C

¤ A  (B  C) = (A  B)  C

06/21/20 5
 Properties of AND and OR
 Distributive Property
¤ A + B  C = (A + B)  (A + C)
¤ A+BC
A B C Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
06/21/20 6
 Distributive Property
 (A + B)  (A + C)

A B C Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
06/21/20 1 1 1 1 7
 Binary Addition

A B S C(arry)
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1

Notice that the carry results are the same as AND

C=AB
06/21/20 8
 Inversion (NOT)

A Q

0 1
Logic: QA
1 0

06/21/20 9
 Exclusive OR (XOR)

Either A or B, but not both

A B S
This is sometimes called the
inequality detector, because the 0 0 0
result will be 0 when the inputs are the 1 0 1
same and 1 when they are different.
0 1 1
The truth table is the same as for 1 1 0
S on Binary Addition. S = A  B
06/21/20 10
 Getting the XOR
Two ways of getting S = 1 A B S
0 0 0
A  B or A  B
1 0 1
0 1 1
1 1 0

06/21/20 11
 Circuit for XOR

A  B  AB  AB
Accumulating our results: Binary addition is the
result of XOR plus AND
06/21/20 12
 NAND (NOT AND)

A B Q
Q  AB 0 0 1
0 1 1
1 0 1
1 1 0

06/21/20 13
 NOR (NOT OR)

A B Q
QAB 0 0 1
0 1 0
1 0 0
1 1 0
06/21/20 14
 Exclusive NOR

A B Q
Q  AB
0 0 1
0 1 0
Equality Detector
1 0 0
1 1 1
06/21/20 15
 Summary
Summary for all 2-input gates

Inputs Output of each gate

 A   B  AND NAND  OR  NOR XOR XNOR

0 0 0 1 0 1 0 1

0 1 0 1 1 0 1 0

1 0 0 1 1 0 1 0

1 1 1 0 1 0 0 1

06/21/20 16