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OWH000201 UMG8900 Hardware Data - Cascading
OWH000201 UMG8900 Hardware Data - Cascading
OWH000201 UMG8900
Hardware Data
Configuration
ISSUE 2.2 www.huawei.com
Save configuration
Save configuration
End
Start
Configure frame
Configure board
Cascading relationship
Configure clock
End
Command Function
ADD FRM Add a frame
RMV FRM Delete a frame
MOD FRM Modify a frame
LST FRM Query a frame
RST FRM Reset a frame
Default configuration :
The OMU and NET in the main control frame and the MPU
and NET in other frames are configured by default. You do
not need to configure these boards and cannot delete them.
Work modes :
1+1 backup :OMU, MPU, NET, CLK, TNU, TCLU, CMU,
RPU, ASU, BLU
Load sharing :PPU, E8T, E1G, P4L, P1H, A4L, EAC, TAC,
TCU, ECU, SPF, E32, T32, FLU
Load sharing or 1+1 backup :S2L
Command Function
ADD BRD Add a board
FE+GE+TDM F F FE+GE+TDM
Service
2# 3# 4# E E 5# 6# 7#
frame
(2#~7#)
Extended M M
N N
control frame E E
(8#) T T
Command Function
ADD FRMLNK Add a Frame Link
RMV FRMLNK Delete a Frame Link
LST FRMLNK QUERY Frame Link
The UMG8900 clock system provides can provide gateway exchange and lo
cal exchange with Stratum-3 or Stratum-2 Clock
The CLK board can extract CLK Source from:
Two-channel 8 kHz line clock
Automatic selection
BITS GPS
1.5GHz 1.5GHz
2048kbit/s
2048kHz 8kHz
C C N N E E
L L E E 3 3
main control frame
K K T T 2 2
service frames
central switching frame
B B N N E E N N
L L E E 3 3 E E
U U T T 2 2 T T
No
Configure reference
source?
Yes
Configure reference
source
No
No
Extract line clock?
Yes
Configure line clock
source
End
No
Yes Select reference source
Under SSM control? based on SSM level
No
Yes Select reference source
Without the same priority? based on priority
No
Select in the order of
GPS, LINE1, LINE2 and EXT
End
Command Function
MOD CLKSRC Modify configuration of reference source
Command Function
MOD CLK Modify configuration of clock board
Command Function
SET LINECLK Configure the port from which the CLK board
extracts line clock reference source
After clock configuration, you can query clock data configuration including
phase-lock status by the command DSP CLK. The value of phase-lock
status can be:
Free running: Indicates that the CLK board outputs free running clock
generated by its crystal.
Fast tracking: Indicates that the CLK board is tracking reference source
clock fast and is an instantaneous status usually when the system just
connects the reference source.
Locked: Indicates that the CLK board has locked primary reference
source and outputs clock signals aligned with reference source.
Holdover: Indicates that the CLK board outputs clock signals based on
the locked status when reference source is missing.