system composed of two or more independent cores (or CPUs). The cores are typically integrated onto a single integrated circuit die (known as a chip multiprocessor or CMP), or they may be integrated onto multiple dies in a single chip package. Multi-Core Computer The amount of performance gained by the use of a multi-core processor is strongly dependent on the software algorithms and implementation. All cores are identical in symmetric multi-core systems and they are not identical in asymmetric multi-core systems. Just as with single-processor systems, cores in multi-core systems may implement architectures such as superscalar, vector processing, or multithreading. Moore’s Law
• Number of transistors on-chip doubles every 18
months • Moore’s Law is facing a danger today – Power consumption is too high when clocked at multi- GHz frequency and it is proportional to the number of switching transistors • Wire delay doesn’t decrease with transistor size Moore’s Law Moore’s Law of transistor density is still going strong, but the clock speed has hit a wall. Now what do we do? Adding more transistors on a single chip, but don’t increase the clock speed. Instead, we increase computational throughput by using those transistors to pack multiple processors onto the same chip. Symmetric Multi-core Processor(SMP) A symmetric multi-core processor is one that has multiple cores on a single chip, and all of those cores are identical. ▪ Example: Intel Core 2: ▪ The Intel Core 2 is an example of a symmetric multi- core processor. The Core 2 can have either 2 cores on chip ("Core 2 Duo") or 4 cores on chip ("Core 2 Quad"). Each core in the Core 2 chip is symmetrical, and can function independently of one another. It requires a mixture of scheduling software and hardware to farm tasks out to each core. Symmetric Multi-core Processor
All cores which exist in a die are
exactly identical Performance of Symmetric Multicore Chips Serial Fraction 1-F uses 1 core at rate Perf(r) Serial time = (1 – f) / Perf(r) Parallel Fraction uses n/r cores at rate Perf(r) each Parallel time = f / (Perf(r) * ( n/r )) = f*r / Perf(r)*n Performance of Symmetric Multicore Chips Single BCE implements the baseline core. that architects can expend the resources of r BCEs to create a powerful core with sequential performance perf(r). Performance of Symmetric Multicore Chips Software fraction that is parallelizable (f) The total chip resources in BCEs (n) BCE resources (r) devoted to increase each core’s performance. The chip uses one core to execute sequentially at performance perf(r). It uses all n/r cores to execute in parallel at performance perf(r) × n/r. Example Symmetric Multi-core Processor Applications Personal Computers
Server / Super Computer
Asymmetric Multi-core Processor An asymmetric multi-core processor is one that has multiple cores on a single chip, but those cores might be different designs. For instance, there could be 2 general purpose cores and 2 vector cores on a single chip. ▪ Example: Cell Processor: ▪ IBM's Cell processor, used in the Sony PlayStation 3 video game console is an asymmetrical multi-core processor. The Cell has 9 processor cores on board, one general purpose processor, and 8 data-processing cores.. Asymmetric Multi-core Processor ▪ In an asymmetric multi-core processor, the chip has multiple cores onboard, but the cores might be different designs. ▪ Each core will have different capabilities. Serial Fraction 1-F same, so time = (1 – F) / Perf(R) Parallel Fraction F One core at rate Perf(R) N-R cores at rate 1 Parallel time = F / (Perf(R) + N - R)
Asymmetric offers greater speedups potential than Symmetric
As Moore’s Law increases N, Asymmetric gets better Asymmetric Multi-core Processor(ASMP) – Cell Processor • Applications Console Video Games Many core processor
Manycore processors are specialist multi-
core processors designed for a high degree of parallel processing, containing a large number of simpler, independent processor cores (e.g. 10s, 100s, or 1,000s). References http://en.wikipedia.org/wiki/Multi-core_(computing) Olukotun, Kunle and Hammond, Lance. The future of microprocessors.Queue, Volume 3, Issue 7, September 2005. www.princeton.edu/~jdonald/research/hyperthreading/garg_report.pdf Zheltov, Sergey N. and Bratanov, Stanislav V. Multi-threading for Experts: Synchronization. Technical Report. Intel. 2005. (WWWdocument, referenced 17.11.2005). Available: http://www.intel.com/cd/ids/developer/asmo-na/eng/183321.htm Parallel Programming:Moore’s Law and Multicore ,Mike Bailey,Oregon State University Amdahl’s Law in the Multicore Era, Mark D. Hill, University of Wisconsin- Madison, Michael R. Marty, Google