Professional Documents
Culture Documents
Computer Organization and Architecture: Reserved
Computer Organization and Architecture: Reserved
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 1
CPU Design
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 2 2
Introduction to CPU
The operation or task that must perform by CPU are:
•Fetch Instruction
•Interprete Instruction
•Fetch Data
•Process data
•Write data
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 3
•The major components of the CPU are an arithmetic and
logic unit (ALU) and a control unit (CU).
•The ALU does the actual computation or processing of
data.
•The CU controls the movement of data and instruction into
and out of the CPU and controls the operation of the ALU.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 4
CPU system Bus
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 5
CPU System Bus
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 6
Internal Structure of the CPU
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 7
There are three basic components of CPU:
1. Register bank
2. ALU and
3. Control Unit.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 8
Register Organization
•Segment pointer
•Index registers
•Stack pointer
Four registers are essential to instruction execution:
1. Program Counter (PC)
2. Instruction Register (IR)
3. Memory Address Register (MAR)
4. Memory Buffer Register (MBR)
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 10
Processor Status Word
1. Sign
2. Zero
3. Carry
4. Equal
5. Overflow
6. Interrupt enable/disable
7. Supervisor
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 11
Concept of Program Execution
1. Fetch the contents of the memory location pointed at by the PC. The
contents of this location are interpreted as an instruction to be executed.
Hence, they are stored in the instruction register (IR). Symbolically this can
be written as:
IR = [ [PC] ]
PC = [PC] + 1
3. Carry out the actions specified by the instruction stored in the IR.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 12
Single bus organization of the data path inside the CPU
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 13
The processor interpretes the instruction and performs the
required action. In general, the actions fall into four categories:
•Processor-memory
•Processor-I/O
•Data processing
•Control
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 14
Instruction cycle
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 15
An instruction cycle consists of two phase,
1. Fetch cycle
2. Execution cycle
Operation of a CPU:
1. Fetch the contents of a given memory location and load them into a CPU
register.
2. Store a word of data from a CPU register into a given memory location.
3. Transfer a word of data from one CPU register to another or to the ALU.
4. Perform an arithmetic or logic operation, and store the result in a CPU register
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 16
8086 ARCHITECTURE
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 17
Addressing Modes
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 19
Immediate Addressing
OPERAND = A
Instruction
Opcode Operand
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 20
Direct Addressing
•
Address field contains address of operand
•
Effective address (EA) = address field (A)
•
e.g. ADD A
•
Add contents of cell A to accumulator
•
Look in memory at address A for operand
•
Single memory reference to access data
•
No additional calculations to work out effective address
•
Limited address space
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 21
Direct Addressing Diagram
Instruction
Address A
Memory
Operand
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 22
Indirect Addressing
•
Memory cell pointed to by address field contains the address
of (pointer to) the operand
•
EA = (A)
Look in A, find address (A) and look there for operand
•
•
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator
•
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 23
Indirect Addressing Diagram
Instruction
Address A
Memory
Pointer to operand
Operand
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 24
Register Addressing
•
Operand is held in register named in address filed
•
EA = R
•
Limited number of registers
•
Very small address field needed
•
Shorter instructions
•
Faster instruction fetch
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 25
Register Addressing
•
No memory access
•
Very fast execution
•
Very limited address space
•
Multiple registers helps performance
Requires good assembly programming or compiler writing
•
•
Direct addressing
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 26
Register Addressing Diagram
Instruction
Register Address R
Registers
Operand
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 27
Register Indirect Addressing
•
Indirect addressing
•
EA = (R)
•
Operand is in memory cell pointed to by contents of register
R
•
Large address space (2n)
•
One fewer memory access than indirect addressing
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 28
Register Indirect Addressing
Instruction
Registers
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 29
Displacement Addressing
•
EA = A + (R)
•
Address field hold two values
•
A = base value
•
R = register that holds displacement
•
or vice versa
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 30
Displacement Addressing Diagram
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 31
Displacement Addressing
•
Relative Addressing
•
Base-Register Addressing
•
Indexing
•
auto-indexing
•
auto-incrementing
•
EA = A + (R)
•
R = (R) + 1
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 32
Displacement Addressing
•
auto-decrementing
•
EA = A + (R)
•
R = (R) – 1
•
If indexing is performed after the indirection, it is termed
postindexing
EA = (A) + (R)
•
With preindexing, the indexing is performed before the
indirection:
EA = ( A + (R) )
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 33
Stack Addressing
•
Operand is (implicitly) on top of stack
•
e.g.
ADD Pop top two items from stack and add
•
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 34
Instruction Set
•
The operation of a CPU is determine by the instruction it
executes, referred to as machine instructions or computer
instructions. The collection of different instructions is referred
as the instruction set of the CPU.
•
Each instruction must contain the information required by the
CPU for execution.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 35
Opcodes are represented by abbreviations, called
mnemonics, that indicate the operations
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 36
The instruction set of a CPU can be categorized as follows:
1. Data Processing
2. Data Storage
3. Data Movement
4. Control
Types of Operands
1. Addresses
2. Numbers
3. Characters
4. Logical Data
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
37
RESERVED
Types of Operations
•
Data Transfer
•
Arithmetic
•
Logical
•
Conversion
•
Input Output [ I/O ]
•
System Control
•
Transfer Control
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 38
A. Data Transfer
Move (Transfer) --------Transfer word or block from source to destination
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 41
D. Input/output
Input (Read)----- Transfer data from specified I/O port or device to
destination (e.g., main memory or processor register)
•
System control instructions are those which are
used for system setting and it can be used only in
privileged state.
•
Typically, these instructions are reserved for the
use of operating systems.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 43
F. Transfer of Control
•
The most common transfer-of-control operations
found in instruction set are:
•
Branch
•
Skip
•
Procedure call.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 44
BRP X ----Branch to location X if result is positive
BRN X ---- Branch to location X if result is negative
BRZ X----- Branch to location X is result is zero
BRO X----- Branch to location X if overflow occurs
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 45
Instruction Format
Opcode Zero Address Instruction
Two address
MOV R1 , A
instructions
R 1 <--M [ A ]
ADD R1 , B R 1 <--R 1 + M [ B ]
MOV R2 , C R 2 <--M [ C ]
ADD R2 , D R 2 <--R 2 + M [ D ]
MUL R1 , R2 R 1 <--R 1 * R 2
MOV X , R1 M [ X ] <--R 1
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 47
One address instructions
LOAD A A C <- M [ A J
ADD B A C <- A C + M [ B ]
STORE T M [ T ] <- A C
LOAD C A C <- M [ C ]
ADD D A C <- A C + M [ D ]
MUL T A C <- A C • M [ T ]
STORE X M [ X ] <- A C
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 48
Zero address instructions
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 49
Stack Organization
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 50
Subroutine Calls
Requirements
Set PC to arbitrary address
•
Transfer: transfers data from one register to another
R0 <- R1
•
Arithmetic: performs arithmetic on data in registers
R0 <- R1 + R2
•
Logic/bit manipulation: performs bit (Boolean) operations on data
R0 <- R1 & R2 ; or R0 <- R1 | R2
•
Shift: shift data in registers by one or more bit positions
R0 <- R1 << 3; or R0 <- R2 >> 2
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 53
Micro-Ops Transfer
Parallel
Parallel transfer is typically used
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 54
Micro-Ops Transfer
Serial
Serial transfer is used to specify
that a collection of bits are to be
moved, but that the transfer is to
occur one bit at a time
•
Ex: S: A <- B, B <-B
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 55
Micro-Ops Transfer
Bus
A bus consists of a set of parallel data lines
To transfer data using a bus: connect the output of the source register to the bus; connect
the input of the target register to the bus; when the clock pulse arrives, the transfer occurs
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 56
Micro-Ops Transfer
Memory
Memory transfers are similar to register transfers, but…
registers:
AR <- address
DR <- M[AR]
RTL expressions for a write operation, assuming use of a data register:
AR <- address
DR <- value
M[AR] <- DR
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 57
MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
AND Routine
ADD 0000 0001
. 0010 LDA Routine
AND 0001 . STA Routine
. 0011
LDA 0010 0100
BUN Routine
STA 0011 Control
BUN 0100 Storage
Mapping
10 xxxx 010
Bits Address
10 0000 010 ADD Routine
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS 58
RESERVED
MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14 11 10 0
I Opcode Address
Micro-instruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 59
Sample machine instructions
Symbol Opcode Description
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 60
MICROINSTRUCTION FIELD DESCRIPTIONS -
F1,F2,F3
F1 Micro Symbol F2 Micro Symbol F3 Micro Symbol
operation operation operation
000 None NOP 000 None NOP 000 None NOP
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 61
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD Condition Symbol Comments
00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
CAR CAR + 1 if condition = 0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 62
DESIGN OF CONTROL UNIT
DECODING ALU CONTROL INFORMATION -
microoperation fields
F1 F2 F3
AND
ADD Arithmetic AC
DRTAC logic and
shift unit DR
PCTAR
DRTAR
From From
PC DR(0-10) Load
AC
Select 0 1
Multiplexers
Load AR Clock
•
ROM: Read only memories are non volatile in nature. The
storage is permanent, but it is read only memory. We can
not store new information in ROM.
•
Types: PROM, EPROM, EEPROM, UVPROM
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 65
Main Memory Organization
•
16X4 Means 16 Locations & 4 bits in each Location
•
Read – Retrieve data from memory to CPU registers
•
Write – Store data to memory from CPU registers
•
To transfer data we require data bus
•
To specify or to identify a particular memory location we require
address bus
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 66
Semiconductor Memory Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random
EPROM Mask-Programmed
Access Access
2
E PROM Programmable (PROM)
DRAM LIFO
Shift Register
Content
Addressable
Memory (CAM)
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 67
RAM
•
Random write and read operation for any cell
•
Volatile data
•
Most of computer memory
•
DRAM
•
Low Cost
•
High Density
•
Medium Speed
•
SRAM
•
High Speed
•
Ease of use
•
Medium Cost
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 68
ROM
•
Non-volatile Data
•
Method of Data Writing
•
Mask ROM
Data written during chip fabrication
•
•
PROM
Fuse ROM: Non-rewritable
•
EPROM:
•
Erase data by UV rays
EEPROM: Erase and write through electrical means
•
•
Speed 2-3 times slower than RAM
•
Upper limit on write operations
•
Flash Memory – High density, Low Cost
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 69
FLASH
•
Extension of EEPROM
Same floating gate principle
•
•
Fast erase
Large blocks of memory erased at once, rather than one word at a time
•
•
Writes to single words may be slower
Entire block must be read, word updated, then entire block written back
•
•
Used with embedded microcomputer systems storing large data items in nonvolatile
memory
e.g., digital cameras, MP3, cell phones
•
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 70
CPU and Memory
•
CPU can interact with main memory in two ways:
•It can write a byte/word to a given memory location.
•The previous bits that were in that location are destroyed
•The new bits are saved for future use.
•It can read a byte/word from a given memory location.
•The CPU copies the bits stored at that location and stores them in a CPU register
•The contents of the memory location are NOT changed.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 71
Main Memory Characteristics
Very closely connected to the CPU.
Contents are quickly and easily changed.
Holds the programs and data that the processor is actively working
with.
Interacts with the processor millions of times per second.
Nothing permanent is kept in main memory.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 72
Secondary Storage Characteristics
Connected to main memory through a bus and a device controller.
Contents are easily changed, but access is very slow compared to
main memory.
Only occasionally interacts with CPU.
Used for long-term storage of programs and data.
Much larger than main memory (GBs vs. MBs).
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 73
•
CPU --- Memory
Hi Lo
•
16-bit CPU Byte Organized
•
Data Size Lower order byte
first or little endian
15-8 7-0 Hi CPU
Lo
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 74
The data transfer between main memory and the CPU takes place through two
CPU registers.
If the MAR is k-bit long, then the total addressable memory location will be 2k.
If the MDR is n-bit long, then the n bit of data is transferred in one memory cycle.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 75
Binary Storage Cell
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 76
Depending on the technology used to construct a RAM, there are two types of
RAM –
SRAM
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 77
DRAM
SRAM & DRAM both are volatile
•
Memory split into two User Program
1. For operating system
2. For currently executing program
Uni-Program
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 82
Memory Management
Memory
Multi-Program:
Operating System
Multi-Program
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 83
Partitionin
g
1) Fixed size partitions
2) Variable size partitions
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 84
Paging
The memory is partitioned into equal fixed size chunks that are relatively
small. This chunk of memory is known as frames or page frames.
Each process is also divided into small fixed chunks of same size. The
chunks of a program is known as pages.
At a given point of time some of the frames in memory are in use and
some are free. The list of free frame is maintained by the operating system.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 85
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 86
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 87
Cache Memory
It is the fact that CPU is a faster device and memory is a relatively slower device.
Memory access is the main bottleneck for the performance efficiency. If a faster memory
device can be inserted between main memory and CPU, the efficiency can be increased.
The faster memory that is inserted between CPU and Main Memory is termed as Cache
memory.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 88
Cache Memory
•
High speed (towards CPU speed)
•
Small size (power & cost)
Miss
Main
CPU Memory
Cache (Slow)
(Fast) Mem
Hit Cache
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 90
Cache Mapping
1. Direct mapping
2. Associative mapping
3. Block-set-associative mapping
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 91
Direct Mapping
•
A particular block of main
memory can be brought to a
particular block of cache
memory.
•
It is not flexible
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 92
Associative Mapping
•
In this mapping function, any
block of Main memory can
potentially reside in any cache
block position.
•
This is much more flexible
mapping method.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 93
Block Set Associative Mapping
•
In this method, blocks
of cache are grouped
into sets, and the
mapping allows a block
of main memory to
reside in any block of a
specific set. From the
flexibility point of view,
it is in between to the
other two methods
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 94
Cache Replacement Policies
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 95
Virtual Memory
The virtual address space is used to develop a process. The special hardware unit , called
Memory Management Unit (MMU) translates virtual address to physical address. When
the desired data is in the main memory, the CPU can work with these data. If the data are
not in the main memory, the MMU causes the operating system to bring into the memory
from the disk.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 96
VIRTUAL MEMORY
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 98
Address space and memory space split into groups of lK words.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 99
Memory Table in a paged system
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
100
RESERVED
An associative memory page table.
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS
RESERVED 101