PIPELINE PROCESSOR

Characteristics Of Pipeline Processors

• Pipelining refers to the temporal overlapping of processing pipelines are nothing more than

assembly lines in computing that can be used for instruction processing.

• A basic pipeline process a sequence of tasks or instruction, according to the following principle of

operation.

• Each task is subdivided into a number of successive tasks.

• The processing of each single instruction can be broken down into four sub tasks:-

• 1. Instruction Fetch

• 2. Instruction Decode

• 3. Execute

• 4. Write back

• It is assumed that there is a pipelined stage associated with each subtask.

•  
 Linear Pipeline Processors
• A linear Pipeline processor is a cascade of processing stages which are linearly

• connected to perform a fixed function over a stream of data flowing from one

• end to other.

• In modern computers, linear pipelines are applied for instruction execution, arithmetic computation, memory

access operations.

•  

• A linear pipeline processor is constructed with be processing stages. External

• inputs are fed into the pipeline at the first stage S1. The processed results are

• passed from stage Si to stage Si+1 for all i = 1,2…….K-1. The final result emerges

• from the pipeline at the last stage Sk. Depending on the control of data flow

• along the pipeline, linear pipelines are model in two categories.

•  
 Pipeline instruction processing
• Fetch stage (F) fetches instructions from a cache memory.
• · Decode stage (D) decode the instruction in order to find function to be
• performed and identifies the resources needed.
• · Issue stage (I) reserves resources. Resources include GPRs, bases and
• functional units.
• · The instructions are executed in one or several execute stages (E)
• · Write back stage (WB) is used to write results into the registers.
• · Memory lead and store (L/S) operations are treated as part of solution.
• · Floating point add and multiply operations take four execution clock cycles
Synchronous Model
 Asynchronous Model
• Data flow between adjacent stages in asynchronous
• pipeline is controlled by handshaking protocol. When stage
S1 is ready to
• transmit, it sends a ready signal to Si + 1. After stage Si+1
receives the incoming
• data, it returns an acknowledge signal to Si.
•  
 Speedup
• Speedup We define the speedup of a k -stage linear pipeline
processor
• over an equivalent non-pipeline processor as
• It should be noted that the maximum speedup isS k k → ,for n >>
k. In other
• words, the maximum speedup that a linear pipeline can provide us
is k ,
• where k is the number of stages in the pipe. The maximum speedup
is never
• fully achievable because of data dependencies between
instructions,
• interrupts, and other factors.
 Efficiency
• The efficiency of a linear pipeline is measured by the percentage

• of busy time-space spans over the total time-space span, which equals the sum of all busy and idle time-

space spans. Let n, k,τ be the number of tasks (instructions), the number of pipeline stages, and the clock

period of a linear pipeline, respectively. The pipeline efficiency is defined by

• Note that η  1as n  ∞. This implies that the larger the number of

• tasks flowing through the pipeline, the better is its efficiency. Moreover, we

• realize that η = Sk /k . This provides another view of efficiency of a linear

• pipeline as the ratio of its actual speedup to the ideal speedup k . In the steady

• state of a pipeline, we have n >> k, the efficiency η should approach 1.

• However, this ideal case may not hold all the time because of program

• branches and interrupts, data dependency, and other reasons

 Throughput
• The number of results (tasks) that can be completed by a

• pipeline per unit time is called its throughput. This rate reflects the computing

• power of a pipeline. In terms of efficiency η and clock period τ of a linear

• pipeline, we define the throughput as follows:

• where n equals the total number of tasks being processed during an

• observation period kτ + (n − 1)τ . In the ideal case, w = 1/ τ=f

• when η → 1.This means that the maximum throughput of a linear pipeline is equal to its frequency,

which corresponds to one output result per clock period. According to the levels of processing, pipeline

processors can be classified into the classes: arithmetic, instruction, processor, unifunction vs.

multifunction, static vs. dynamic, scalar vs. vector pipelines.

NON LINEAR PIPELINE PROCESSOR
Arithmetic pipeline & pipeline design
 Floating point representation IEEE 754 Standard

IEEE standards for floating-point representation

3.16
IEEE Specifications

Storage of IEEE standard floating point numbers:

1. Store the sign in S (0 or 1).
2. Change the number to binary.
3. Normalize.
4. Find the values of E and M.
5. Concatenate S, E, and M.
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Example
Show the Excess_127 (single precision) representation of the
decimal number5.75.
Solution
a. The sign is positive, so S = 0.
b. Decimal to binary transformation: 5.75 = (101.11)2.
c. Normalization: (101.11)2 = (1.1011)2 × 22.
d. E = 2 + 127 = 129 = (10000001)2, M = 1011. We need to add
nineteen zeros at the right of M to make it 23 bits.
e. The presentation is shown below:

The number is stored in the computer as

01000000110110000000000000000000
3.18