Memory Organization

and Interfacing
EEE-3131
 Semiconductor Memory
 Capacity
• Kbits (Kilobits)
• Mbits (Megabits)

 Organization
• Number of locations => Number of
address lines
• Size of a location => Number of data
lines
Semiconductor Memory (cont’d)
 Speed
• Access time

 Volatility

 Programmability
 Memory Organization
Number of address lines
Number of locations

2 y
x

Number of data lines

 Nonvolatile Memory
 Read-Only Memory (ROM)
 Programming or Burning
• PROM; one-time programmable
• EPROM; erasable using UV radiation
• EEPROM; electrically erasable
• Flash ROM; erasable in a flash (fast
time)
• Mask ROM; mask technology
 Volatile Memory
 Random Access Memory (RAM)
 Types
• Static RAM (SRAM)
 does not require refreshing
 up to four transistors per cell
• Dynamic RAM (DRAM)
 requires refreshing
 one transistor (capacitor) per cell
 Address Decoding
A19 A0
0000 1000 0000 0000 0000
………
0000 1111 1111 1111 1111 D7 D0
A0

A15 32Kx8
A16 A14
A17
A18 CS
A19 OE WR

MEMR MEMW

Range of addresses 08000h to 0FFFFh

 Conventional Memory
 640K of RAM
FFFFFh
ROM 256K
C0000h
BFFFFh
VDR 128K
A0000h Conventional
9FFFFh memory
•MS-DOS OS
•Utilities
•Applications
RAM 640K
BIOS temp data 004FFh •Etc…
003FFh
Interrupt vector table
00000h
 BIOS Data Area
Start Address End Address # Bytes Description

0000:0000 0000:03FF 1024 Interrupt table

0000:0400 0000:0401 2 Port address COM1

… … … …

0000:0408 0000:0409 2 Port address LPT1

…. …. … …

0000:0410 0000:0411 2 List of hardware

0000:00412 0000:0412 1 Initialization flag

0000:0413 0000:0414 2 Memory size (KB)

… … … …

… … … …
DRAM Memory Banks
Bank 3 64K x 4 64K x 4 64K x 1

Bank 2 64K x 4 64K x 4 64K x 1

Bank 1 256K x 4 256K x 4 256K x 1

Bank 0 256K x 4 256K x 4 256K x 1

Example configuration of 640KB RAM

 P o w e r- O N

F F F F :0 0 0 0
( R e s e t P o in t)

PO ST
Bootstrap Loader
Bootstrap ROM
S y s te m In it . Boot ROM
IN T 1 9

L o a d B o o ts tra p R e c o rd
(T ra c k 0 , S e c to r 0 )

L o a d O p e r a t in g S y s t e m
( IO .S Y S , M S D O S .S Y S , C O M M A N D .C O M )
• Memory Address Map
 Memory Configuration : 512 bytes RAM + 512 bytes
ROM
• 1 x 512 byte ROM + 4 x 128 bytes RAM
A d d re s s b u s CPU

 Memory Address Map : Tab. 12-1 16 - 11 10 9 8 7 - 1 RD W R D a ta b u s

• Address line 9 8 D ecoder

3 2 1 0

 RAM 1 0 0 : 0000 - 007F

CS1
CS2
128× 8 D a ta
RD
 RAM 1 0 1 : 0080 - 00FF
RAM 1
W R
AD7

 RAM 1 1 0 : 0100 - 017F CS1

 RAM 1 1 1 : 0180 - 01FF

CS2
128× 8 D a ta
RD
RAM 2

• Address line 10
W R
AD7

 ROM 1 : 0200 - 03FF CS1

CS2

Memory Connection to CPU : Fig. 12-4

128× 8 D a ta
RD
 W R
RAM 3

AD7

• 2 x 4 Decoder : RAM select (CS1) CS1

• Address line 10 CS2

RD
128× 8 D a ta
RAM 4

 RAM select : CS2

W R
AD7

 ROM select : CS2 의 Invert CS1

CS2

 RD : ROM CS1 1-7 128× 8

ROM
D a ta
8
AD9

OE(Output Enable)
9
 A d d re s s b u s C P U

1 6 - 1 1 1 0 9 8 7 - 1 R D W R D a ta b u s

D e c o d e r
3 2 1 0
C S 1
C S 2
1 2 8 × 8 D a ta
R D
R A M 1
W R
A D 7

C S 1
C S 2
1 2 8 × 8 D a ta
R D
R A M 2
W R
A D 7

C S 1
C S 2
1 2 8 × 8 D a ta
R D
R A M 3
W R
A D 7

C S 1
C S 2
1 2 8 × 8 D a ta
R D
R A M 4
W R
A D 7

C S 1
C S 2
1 - 7 1 2 8 × 8 D a ta
R O M
8
A D 9
9