# Modeling for Synthesis With VHDL

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Synthesis is used for decreasing the area increase the speed and It is used for decreasing the power consumption.

Synthesis= Translation + Optimization + Mapping

RTL Synthesis
VHDL / Verilog

RTL Optimization

Logic level optimization

Gate level Optimization

(i)Constant folding Eg: A+3+2 it is folded as A+5 (ii)Loop Unrolling: All loop statements are unrolled to a series of individual statements. Different implementation of Arithmetic operations have different area and timing constarints .RTL level optimization: Code related processing is first performed When a model is synthesized.

 Common Sub-Expression Sharing: Suppose if we want to implement two functions Y1 and Y2 it takes more adders to implement in normal way Y1= A+B+X Y2=A+Y+B . Depending of our constraints we decide which is best for him  Suppose ³+´ operation can be performed using different adders user will pick which suits for him.

Y1= A+B+X A B Y2= A+Y+B A Y + + X + + Y1 B Y2 .

 Common Sub-Expression Sharing A B x + + Y1 Y + Y2 Y2= A+Y+B Y1= A+B+X .

 Resource Sharing A B C D If (s) Y=A+B Else Y=C+D + + MUX Y S .

A MUX C B D MUX S S + Y .

B. A S B 10 Y . g4: or port map (Y. end process p1. end.S).BS). else Y <= B.Sbar). --Structural model Synthesis architecture behav of mux is signal Sbar:std_logic begin g1: not port map (Sbar.ASbar.B. g2: and port map (ASbar.S) begin if (S = '0') then Y <= A. g3: and port map (BS. end if.A.S). end.Synthesis  Converts behavioral model to structural model --Behavioral model architecture behav of mux is begin p1: process(A.

end. Expected synthesized design Synthesis Actual synthesized design (oops!!!) 11 .S1.B. end process p1. --else I do not care --what is assigned to Y end if. elsif (S2 = '0') then Y <= B.Why is Understanding of Synthesis Process Important? Behavioral model architecture behav of ckt1 is begin p1: process(A.S2) begin if (S1 = '0') and (S2 = '1') then Y <= A.

Prev. elsif (S2 = '0') then Y <= B. --else do not care --else end if. Stored Value 0 1 B A Latch disabled B A 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 12 .Why is Understanding of Synthesis Process Important? --Code snippet --Code if (S1 = '0') and (S2 = '1') then Y <= A.

Issues with extra hardware  Extra redundant components increase area utilization  More switching activity leading to power loss  Issues with latches ± Setup and hold timing violations may prevent correct functioning ± Glitches can cause further problems in operation 13 .

S2) begin if (S1 = '0') and (S2 = '1') then Y <= A. else --a value is assigned to Y in the else clause Y <= X .Why is Understanding of Synthesis Process Important? Corrected behavioral code Actual synthesized design architecture behav of ckt1 is begin p1: process(A. using ³else´ end process p1.B. Ensure all cases taken care of. Thumb rule: end if. clause for combinational scenarios end.S1. elsif (S2 = '0') then Y <= B. 14 .

Types of Synthesized Circuits  Combinational logic circuits ± random logic ± multiplexers ± decoders  Arithmetic functions  Sequential logic (registers) ± synchronous & asynchronous inputs  Shift registers  Finite state machines  Memory synthesis 15 .

-. b) begin c <= a and b. must be in the sensitivity list 16 . b: in BIT.this should be process (a.Use concurrent assignment or a process. architecture Synthesis_Bad of And_Bad is begin process (a) -. end And_Bad. c: out BIT).Combinational Logic -.can miss changes in b Thumb rule: end process.All signals referenced in a process must be in the sensitivity list. -. All signals referenced in the process end Synthesis_Bad. entity And_Bad is port (a.

i) begin case sel is when "00" => s <= i(0).Multiplexer: Using case Statement entity Mux4 is port (i: in BIT_VECTOR(3 downto 0). when "10" => s <= i(2). end process. end Synthesis_1. architecture Synthesis_1 of Mux4 is begin process(sel. Thumb rule: Case statement must be exhaustive 17 . when "11" => s <= i(3). when "01" => s <= i(1). end case. sel: in BIT_VECTOR(1 downto 0). end Mux4. s: out BIT).

Multiplexer using concurrent signal assignment architecture Synthesis_2 of Mux4 is begin with sel select s <= i(0) when "00". i(1) when "01". end Synthesis_2. Thumb rule: Cover all conditions 18 . i(2) when "10". i(3) when "11".

architecture Synthesis_1 of Mux8 is begin process(InBus .OutBit <= InBus(TO_INTEGER ( UNSIGNED ( Sel ) ) ). -. end Synthesis_1.if Sel is std_logic_vector. OutBit : out STD_LOGIC). Sel : in INTEGER range 0 to 7. end process. end Mux8. then must convert to integer -. Sel ) begin OutBit <= InBus(Sel ). 19 .Multiplexer using an array entity Mux8 is port ( InBus : in STD_LOGIC_VECTOR(7 downto 0).

>=  Use ranged integers instead of unbound to minimize generated logic. -1 . <= .*. and abs  Special operations: +1 . > . /= . signal i : integer range 0 to 15. Ex. unary  Relational Operators: = . < .Synthesizing arithmetic circuits  Synthesis tools will generally recognize overloaded operators and generate corresponding circuits: +.-. 20 .

c: integer range 0 to 255. c := a + b.Adders/ subtracters automatically generated for integer data variable a. Thumb rule: Ex:c := a + 5. --produces 8-bit adder (unsigned) Constant operands result in reduced logic by removing logic due to hard-wired values. Use constants in place of variables whenever possible 21 . --produces 32-bit adder (signed) Thumb rule: Use bounded data-types whenever possible variable a. c := a + b.b.b.c: integer.

Multiple adder structures z <= a + b + c + d. --3 adders stacked 3 deep Synthesis output z <= (a + b) + (c + d). --3 adders stacked 2 deep Synthesis output 22 .

c.sel) begin if (sel= 0 ) then z <= a + b .Resource sharing for mutually-exclusive operations process (a. --either this evaluates else z <= a + c . Synthesis output 23 .b. end process . --or this evaluates end if .

begin if (sel= 0 ) then tmp:= b . --mux output added to a end process . end if . Synthesis output 24 .Equivalent model process (a.sel) begin variable tmp: unsigned(0 downto 0) . --mux will select b or c else tmp:= c . z <= a + tmp.c.b.

end process.  Flip-flops process (clk) begin if (clk event and clk= 1 ) then Q <= D . end if. end if. end process. 25 . D) --Sensitivity list begin if (EN = 1 ) then Q <= D .Latches and Flip-flops  Latches process (EN.

--a. b := a. dout<= b. so they become wires . (Only one flip flop from din -> dout) 26 . end process. begin Synthesis output if (clk eventand clk= 1 ) then a := din. end if.3-bit shift register example Unexpected resulting structure process (clk) variable a.b: bit. b changed before used so values are not stored.

Finite state machines (FSM)  Model states as enumerated type  Model present_state and next_state signals/variables  Construct two processes to model FSM ± One process updates state with next_state ± One process updates next_state  Allow synthesis tool to encode states (binary. random.)  Consider how initial state will be forced 27 . one hot. etc. gray code.

state) ± Moore model: outputs = f ( state )  case more efficient than if-then-elsif present_state (later builds a priority encoder)  Signal assignment consideration to test ± Assign outputs & next_state for every case/condition. ± If an output or next_state is not assigned something under a certain condition in the case statement. the synthesis tools will have to preserve the value with extra latches/flip-flops.  Left-most value of enumeration type is default simulation starting value (use reset to initialize real circuit) 28 .State machine synthesis issues  Two-types of FSM models ± Mealy model: outputs = f ( inputs.

Design capture tools :  One of the first tasks a designer needs to do is capture a description of the design using a HDL (Hardware Description Language).  The objective at this stage is to create high-quality code as quickly as possible before moving on to the simulation stage  As design capture can be a very time consuming and error prone process. e.g. . there are a number of tools that can help a designer improve productivity and enhance the quality of the HDL code produced at this stage. Verilog or VHDL.

These tools can be classified as:  Text editors  Linters  Graphical editors  Rule-based checkers .

 Although this facility is useful.  Some of the more advanced text editors enable text to be automatically indented and color-coded whenever certain keywords or constructs are detected.(i) Text Editors:  Basic text editors offer simple facilities such as the ability to copy and paste text. search and replace text strings and format text using tabs (tabulation characters) or spaces. . it does not help in isolating and identifying any coding problems or syntax errors. because it shows the structure of the captured code.

 There are also programmable editors that have language specific modes of operation that automate and enforce a standard set of coding standards.  As the information held in the template is fixed it is not very easy for the user to make changes to the defined coding standards. .  This is normally achieved by using a predefined template that specifies the coding standards that will be used by the editor.

.  Verilog and VHDL have a syntax very similar to C and Pascal respectively.  For example.e.) and that it matched what had been declared in the main body of the program. integer. checking that a value passed to a procedure or function was the correct type (i. etc. Boolean. it was natural for linters to appear for these two HDL languages.(ii) Linters:  The original concept of `linting'' comes from languages like C and C++ where linters are used to check for inconsistencies within the code that had been written. string.

 VHDL is a strongly typed language and this means it is relatively easy task for a linting tool to check for any inconsistencies in the source code.  Verilog on the other hand is a loosely typed language that allows registers to be overloaded or array boundaries to be exceeded.  So here the linting tool has to detect "logical" coding errors that would otherwise be acceptable to Verilog.  A simple example of this type of coding error is shown below where a vectored net is assigned to a signal of a different width. a[0] <= #1 b[1:0]  Depending upon the sophistication of the linting tool, other forms of checks that may be applied include: range and index checking, checking whether a variable is used before it has been assigned and width checking.

(iii) Graphical Editors:
 Consider the task of capturing a complex FSM (Finite State Machine) containing a large number of states and conditional transitions.

 In this situation a designer is normally faced with the task of writing a series of involved `case¶ constructs where each `case term¶ defines a state and the conditions that must be satisfied in order to move onto the next state.

 Although a designer may be willing to undertake this task at the initial design stage, it can get very tedious and time-consuming altering the HDL code whenever changes are made to the operational sequence of the FSM.

 In this particular situation graphical editors can prove very useful, because as well as saving time at the design capture stage they also present the designer with a pictorial image of the FSM that makes it easier to understand the interactions within the FSM.  It is normally easier to see the interactions between the various states using a graphical presentation than trying to decipher a block of HDL source code that may span a number of printed pages.

usually boolean expressions ± Structural description of the collection of gates and connections. more like a schematic ± Physical .Levels of Abstraction  Digital system can be represented at different levels of abstraction ± Behavioral relationship between input and output signals.

components operating concurrently .Basic Structure of a VHDL File  Entity ± Entity declaration: interface to outside world. defines input and output signals ± Architecture: describes the entity. contains processes.

character.Entity Declaration entity NAME_OF_ENTITY is port (signal_names: mode type. std_logic . inout type: boolean.     NAME_OF_ENTITY: user defined signal_names: list of signals (both input and output) mode: in. integer. : signal_names: mode type). buffer. out. signal_names: mode type. end [NAME_OF_ENTITY] .

y: in std_logic. entity half_adder is port( x. . use ieee.Half Adder library ieee.all. carry <= x and y. end myadd. sum. carry: out std_logic). end half_adder. architecture myadd of half_adder is begin sum <= x xor y.std_logic_1164.

Processes Used in behavioral modeling that allows you to use sequential statements to describe the behavior of a system over time [process_label:] process [ (sensitivity_list) ] begin list of sequential statements such as: signal assignments variable assignments case statement exit statement if statement loop statement next statement null statement procedure call wait statement end process [process_label].  .

entity FULL_ADDER is port (A. begin -. . B) begin int1<= A xor B. end process. int2. int3 <= int1 and Cin. use ieee. end process.gate P2: process (int1. Cout : out std_logic). end BEHAV_FA. int2. Sum. Cin) begin Sum <= int1 xor Cin.Full Adder using Processes library ieee.std_logic_1164. int3: std_logic.Process P1 that defines the first half adder P1: process (A. int2<= A and B. architecture BEHAV_FA of FULL_ADDER is signal int1. end FULL_ADDER. B. Cin : in std_logic. -.Process P2 that defines the second half adder and the OR -. Cout <= int2 or int3.all.

Logic Operators  VHDL provides the following predefined basic logic operators: Keyword and or xor xnor* nand nor not Definition conjunction inclusive or exclusive or complement exclusive or complement conjunction complement inclusive or complement * only predefined in VHDL-93 Predefined operators are all binary except for µnot¶ Page 43 .

OR evaluation Page 44 . innermost to outermost order ± Must be used for proper AND .Operator Precedence  Unary not has a higher precedence than any binary operator  ALL binary operators have the SAME precedence  Operators with the same precedence are evaluated left-to-right  Operators in parentheses are evaluated first.

INT2: BIT. declared in declarations part of body  Equivalent to defining intermediate circuit signals for symbolic analysis E.Body Signal Declarations  Similar to interface port declaration ± must define identifier. Page 45 .G. direction not needed  Keyword is signal . type ± signals are internal to body. signal INT1.

Page 46 . INT2 <= not A and B. INT2: BIT.Concurrent Operation Example entity XOR2_OP is port (A. architecture AND_OR_CONC of XOR2_OP is signal INT1. B : in BIT. end AND_OR_CONC . begin Z <= INT1 or INT2. INT1 <= A and not B. Z : out BIT). end XOR2_OP.

Dataflow VHDL Page 47 .

etc. function selection.Bit Vectors  Signals can be more than one bit (a vector) ± Represent QP address and data.  Declaration is similar to single bit signals ± Type is bit_vector or std_logic_vector  We also must specify vector index range and direction ± Big indian: (low to high) ± little endian: (high downto low) Page 48 .

max .min + 1) Page 49 .Vector Declarations port ( A.e. Z: out std_logic_vector(1 to 16) ). A and B: Z: 1 2 7 3 6 4 5 5 4 6 3 7 2 8 1 0 9 10 11 12 13 14 15 16 Note! The first bit and last bit index numbers define the number of bits in the vector (i. B: in std_logic_vector(7 downto 0).

decimal. or hexadecimal. ± O 1234 D 1999 X ABCD Page 50 .Vector Literals  Single bit binary literals are 0 and 1  Vector binary literals are 0101  For bit_vectors we can also specify values using octal.

Vector Logical Operations  Single bit logical operations also apply to vectors ± Operands MUST be the same size (generally applies to all vector operations) ± Assignment target must also have the same number of bits as the result ± Operations are applied bitwise to operands to produce the vector result Page 51 .

Is equivalent to: for i ! 0 to 7 Zi ! A i and Bi . B.Vector Operations Given: Signal A. Then the following logical operation and assignment Z <= A and B. Z: std_logic_vector(7 downto 0). Page 52 .

i. context dependent ± Precedence of relational operators is lower than logical operators.Relational Operators  In the previous example we introduced a new operator. the relational equals ± The relational operators are = (equals) /= (not equals) > (greater than) < (less than) >= (greater or equal) <= (less or equal) ± Note that <= (less or equal) is same operator as <= (signal assignment). Page 53 .e.

Structural Modeling in VHDL Page 54 .

Overview      Component and signal declarations Component instantiations Hierarchical structures Packages Name spaces and scope Page 55 .

Schematic Vs. similar to circuit schematic ± Defines the circuit components ± Describes how components are connected  System behavior or functionality is indirectly defined. ± Symbolic analysis allows us to determine functionality of system from understanding component behaviors Page 56 . defined way. VHDL  Structural VHDL models the structure of a circuit. model only lets components work in a certain.

Example Schematic A A1 B A_IN A B_IN B C_IN A A3 B Z INT3 A2 Z A INT2 B O1 C Z Z_OUT Z INT1 Page 57 .

Example Structural VHDL Interface -. Z_OUT : out BIT).Define the Interface entity MAJORITY is port (A_IN. C_IN: in BIT. end MAJORITY. Page 58 . B_IN.

Page 59 . B : in BIT. signal INT1. Z : out BIT).Declaration of components and local signals component AND2_OP port (A. Z : out BIT). component OR3_OP port (A. B. end component. INT3 : BIT. INT2. end component. C : in BIT.Example VHDL Body architecture STRUCTURE of MAJORITY is -.

Page 60 . A3: AND2_OP port map (B_IN. B_IN. INT3). C_IN. O1: OR3_OP port map (INT1. INT1). INT2). Z_OUT). C_IN.Define the component connections A1: AND2_OP port map (A_IN.Example VHDL Statement Part begin -. end STRUCTURE. INT3. INT2. A2: AND2_OP port map (A_IN.

CASE case <expression> is when choice1 => seq. Statements 1 when choice2 => seq. the choices may be a single value. Statements others end case. Statements 2 * * when others => seq. Like the select assignment.a group (c1 | c2 | c3) or a range (c1 to c3) Page 61 .

C. end process. when 9 | 7 => Z <= B. when others => Z <= 0. end EXAMPLE Page 62 . Z : out integer range 0 to 15.entity CASE_STATEMENT is port )A. when 1 to 5 => Z <= C. B. end case . architecture EXAMPLE of CASE_STATEMENT is begin process )A. end CASE_STATEMENT. X( begin case X is when 0 => Z <= A. X : in integer range 0 to 15. C. B.

IF THEN ELSE If <condition> then seq. If a condition is true the associate statements are executed and the rest of the group are skipped. Statements end if. NOTE: the ³else if´ case is ELSIF (one word. Statements elsif <condition> then seq. Statements else seq. e missing) Page 63 .

Begin process begin wait until CLK=`1`. end BEH_1. end BEH_2. CLK : in bit. end FF.entity FF is port (D. Q <= D. end process. end if. Q : out bit). begin process begin wait on CLK. if (CLK = '1') then Q <= D. Page 64 . end process.

c. architecture archi of mux is begin process (a. s) begin if (s = "00") then o = a.all. c. entity mux is port (a. o : out std_logic). else o = d. library ieee. b. use ieee. end mux.std_logic_1164. elsif (s = "01") then o = b. s : in std_logic_vector (1 downto 0). end if. end process. end archi. elsif (s = "10") then o = c. d : in std_logic.Following is the VHDL code for a 4-to-1 1-bit MUX using an IF Statement. b. d. Page 65 .

. end case. library ieee. b. architecture archi of mux is begin process (a. s) begin case s is when "00" = o = a. end archi. o : out std_logic). s : in std_logic_vector (1 downto 0). b.std_logic_1164. c. d : in std_logic. when "10" = o = c. end process. c. use ieee.Following is the VHDL code for a 4-to-1 1-bit MUX using a Case Statement.all. when "01" = o = b. entity mux is port (a. when others = o = d. d. end mux.

res: out std_logic_vector (7 downto 0)).Following is the VHDL code for a 1-of-8 decoder. end archi. (ONE HOT) library ieee.std_logic_1164. architecture archi of dec is begin res = "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000". . use ieee. entity dec is port (sel: in std_logic_vector (2 downto 0). end dec.all.

Following is the VHDL code for a 1-of-8 decoder. ( ONE COLD) library ieee. use ieee. res: out std_logic_vector (7 downto 0)). entity dec is port (sel: in std_logic_vector (2 downto 0). .std_logic_1164. end dec.all. architecture archi of dec is begin res = "11111110" when sel = "000" else "11111101" when sel = "001" else "11111011" when sel = "010" else "11110111" when sel = "011" else "11101111" when sel = "100" else "11011111" when sel = "101" else "10111111" when sel = "110" else "01111111". end archi.

library ieee. end flop. end if.std_logic_1164.all. architecture archi of flop is begin process (C) begin if (C'event and C='1') then Q = D. use ieee. Q : out std_logic). . end archi.Following is the equivalent VHDL code sample for the DFF with a positive-edge clock. D : in std_logic. entity flop is port(C. end process.

Following is the equivalent VHDL code for a DFF with a negative-edge clock and asynchronous clear. library ieee. . elsif (C'event and C='0')then Q = D. D.all. use ieee.std_logic_1164. end archi. end if. CLR : in std_logic. end process. architecture archi of flop is begin process (C. Q : out std_logic). CLR) begin if (CLR = '1')then Q = '0'. entity flop is port(C. end flop.

end process.all. S : in std_logic. else Q = D. end flop. library ieee. end archi.Following is the equivalent VHDL code for the DFF with a positive-edge clock and synchronous set. .std_logic_1164. end if. D. use ieee. Q : out std_logic). entity flop is port(C. architecture archi of flop is begin process (C) begin if (C'event and C='1') then if (S='1') then Q = '1'. end if.

all.Following is VHDL code for a 4-bit unsigned Up counter with asynchronous clear. end counter. library ieee. end archi. . use ieee. CLR) begin if (CLR='1') then tmp = "0000".std_logic_unsigned. Q = tmp.std_logic_1164. architecture archi of counter is signal tmp: std_logic_vector(3 downto 0). use ieee. elsif (C'event and C='1') then tmp = tmp + 1. end if. Q : out std_logic_vector(3 downto 0)). end process.all. entity counter is port(C. CLR : in std_logic. begin process (C.

end counter. .all. else tmp = tmp . end if. end archi.Following is the VHDL code for a 4-bit unsigned Down counter with synchronous set.1. use ieee.all. Q : out std_logic_vector(3 downto 0)).std_logic_unsigned. architecture archi of counter is signal tmp: std_logic_vector(3 downto 0). entity counter is port(C.std_logic_1164. end if. S : in std_logic. library ieee. Q = tmp. begin process (C) begin if (C'event and C='1') then if (S='1') then tmp = "1111". use ieee. end process.

library ieee.std_logic_unsigned. CLR) begin if (CLR='1') then tmp = "0000". end if. CLR. entity counter is port(C. architecture archi of counter is signal tmp: std_logic_vector(3 downto 0).std_logic_1164. elsif (C'event and C='1') then if (up_down='1') then tmp = tmp + 1. . end process. else tmp = tmp . use ieee. begin process (C. end counter. up_down : in std_logic. use ieee.all. end archi. Q = tmp.1. Q : out std_logic_vector(3 downto 0)).all.Following is the VHDL code for a 4-bit unsigned Up/Down counter with asynchronous clear. end if.