Modeling for Synthesis

With VHDL

1
Synthesis is used for decreasing the area
increase the speed
and
It is used for decreasing the power consumption.

Synthesis= Translation + Optimization + Mapping

RTL Synthesis

VHDL / Verilog

RTL Optimization

Logic level optimization

Gate level Optimization

RTL level optimization:
Code related processing is first performed
When a model is synthesized.

(i)Constant folding

Eg: A+3+2 it is folded as A+5

(ii)Loop Unrolling:
All loop statements are unrolled to a series
of individual statements.

Different implementation of Arithmetic operations have different area and timing constarints
• Depending of our constraints we decide which is best for him

• Suppose “+” operation can be performed using different adders user will pick which
suits for him.

• Common Sub-Expression Sharing:

Suppose if we want to implement two functions

Y1 and Y2 it takes more adders to implement in normal way

Y1= A+B+X

Y2=A+Y+B
 Y1= A+B+X Y2= A+Y+B

A B
A Y

X
+ +
B

+ +
Y1
Y2
• Common Sub-Expression Sharing

A B

Y
x +

+ +

Y1
Y2

Y1= A+B+X Y2= A+Y+B

 A B C D
• Resource Sharing

If (s) + +
Y=A+B
Else
Y=C+D

MUX
Y

S
A B
MUX MUX
D
C

S S

Y
 Synthesis
• Converts behavioral model to structural model
--Behavioral model --Structural model
architecture behav of mux is architecture behav of mux is
begin signal Sbar:std_logic
p1: process(A,B,S) Synthesis begin
begin g1: not port map (Sbar,S);
if (S = '0') then g2: and port map (ASbar,A,Sbar);
Y <= A; g3: and port map (BS,B,S);
else g4: or port map (Y,ASbar,BS);
Y <= B; end;
end if; A
end process p1;
end; S Y

10
 Why is Understanding of
Synthesis Process Important?
Behavioral model Expected synthesized design
architecture behav of ckt1 is
begin
p1: process(A,B,S1,S2)
begin
Synthesis
if (S1 = '0') and (S2 = '1') then
Y <= A;
elsif (S2 = '0') then
Y <= B; Actual synthesized design (oops!!!)
--else I do not care
--what is assigned to Y
end if;
end process p1;
end;

11
 Why is Understanding of
Synthesis Process Important?
--Code snippet
if (S1 = '0') and (S2 = '1') then
Y <= A;
elsif (S2 = '0') then
Y <= B;
--else do not care
end if;

Prev.
1
0 Stored
Value
A
B A
B
Latch
disabled
0
-1 1
-0
1
0
1
0 10
1
0

1
0 0
1

12
 Issues with extra hardware

• Extra redundant components increase area

utilization
• More switching activity leading to power loss
• Issues with latches
– Setup and hold timing violations may prevent correct
functioning
– Glitches can cause further problems in operation

13
 Why is Understanding of
Synthesis Process Important?
Corrected behavioral code
Actual synthesized design
architecture behav of ckt1 is
begin
p1: process(A,B,S1,S2)
begin
if (S1 = '0') and (S2 = '1') then
Y <= A;
elsif (S2 = '0') then
Y <= B;
else
--a value is assigned to Y in the “else” clause
Y <= ‘X’; Thumb rule:
end if; Ensure all cases taken care of, using
end process p1; “else” clause for combinational scenarios
end;
14
 Types of Synthesized Circuits

• Combinational logic circuits

– random logic
– multiplexers
– decoders
• Arithmetic functions
• Sequential logic (registers)
– synchronous & asynchronous inputs
• Shift registers
• Finite state machines
• Memory synthesis
15
 Combinational Logic

-- Use concurrent assignment or a process.

-- All signals referenced in a process must be in the sensitivity list.
entity And_Bad is
port (a, b: in BIT; c: out BIT);
end And_Bad;

architecture Synthesis_Bad of And_Bad is

begin
process (a) -- this should be process (a, b)
begin
c <= a and b; -- can miss changes in b Thumb rule:
end process; All signals referenced in the process
end Synthesis_Bad; must be in the sensitivity list

16
 Multiplexer: Using “case” Statement
entity Mux4 is
port (i: in BIT_VECTOR(3 downto 0);
sel: in BIT_VECTOR(1 downto 0);
s: out BIT);
end Mux4;

architecture Synthesis_1 of Mux4 is

begin
process(sel, i)
begin
case sel is
when "00" => s <= i(0);
when "01" => s <= i(1);
when "10" => s <= i(2);
when "11" => s <= i(3);
end case; Thumb rule:
end process; Case statement must be exhaustive
end Synthesis_1;

17
 Multiplexer using concurrent signal
assignment
architecture Synthesis_2 of Mux4 is
begin
with sel select
s <= i(0) when "00",
i(1) when "01",
i(2) when "10",
i(3) when "11"; Thumb rule:
Cover all conditions
end Synthesis_2;

18
 Multiplexer using an array
entity Mux8 is
port ( InBus : in STD_LOGIC_VECTOR(7 downto 0);
Sel : in INTEGER range 0 to 7;
OutBit : out STD_LOGIC);
end Mux8;

architecture Synthesis_1 of Mux8 is begin

process(InBus , Sel ) begin
OutBit <= InBus(Sel );
end process;
end Synthesis_1;

-- if Sel is std_logic_vector, then must convert to integer

-- OutBit <= InBus(TO_INTEGER ( UNSIGNED ( Sel ) ) );

19
 Synthesizing arithmetic circuits

• Synthesis tools will generally recognize overloaded

operators and generate corresponding circuits:
+,-,*, and abs
• Special operations:
“+1” , “-1” , unary “-”
• Relational Operators:
“=“, “/=“, “<“, “>”, “<=“, “>=“
• Use ranged integers instead of unbound to minimize
generated logic.
Ex. signal i : integer range 0 to 15;
20
 Adders/ subtracters automatically
generated for integer data
Thumb rule:
Use bounded data-types
whenever possible
variable a,b,c: integer;
c := a + b; --produces 32-bit adder (signed)

variable a,b,c: integer range 0 to 255;

c := a + b; --produces 8-bit adder (unsigned)

Constant operands result in reduced logic by

removing logic due to hard-wired values. Thumb rule:
Ex:c := a + 5; Use constants in place of
variables whenever possible
21
 Multiple adder structures

z <= a + b + c + d; --3 adders stacked 3 deep

Synthesis output

z <= (a + b) + (c + d); --3 adders stacked 2 deep

Synthesis output

22
 Resource sharing for
mutually-exclusive operations

process (a,b,c,sel) begin

if (sel=‘0’) then
z <= a + b ; --either this evaluates
else
Synthesis output
z <= a + c ; --or this evaluates
end if ;
end process ;

23
 Equivalent model
process (a,b,c,sel) begin
variable tmp: unsigned(0 downto 0) ;
begin
if (sel=‘0’) then
tmp:= b ; --mux will select b or c
else
tmp:= c ;
end if ;
z <= a + tmp; --mux output added to ‘a’ Synthesis output
end process ;

24
 Latches and Flip-flops
• Latches
process (EN, D) --Sensitivity list
begin
if (EN = ‘1’) then
Q <= D ;
end if;
end process;

• Flip-flops
process (clk)
begin
if (clk’event and clk= ‘1’) then
Q <= D ;
end if;
end process;
25
 3-bit shift register example
Unexpected resulting structure
process (clk)
variable a,b: bit;
begin Synthesis output
if (clk’eventand clk= ‘1’) then
a := din;
b := a;
dout<= b;
end if;
end process;
--a, b changed before used so values are not stored, so they
become “wires”. (Only one flip flop from din -> dout)

26
 Finite state machines (FSM)
• Model states as enumerated type
• Model “present_state” and “next_state”
signals/variables
• Construct two processes to model FSM
– One process updates state with next_state
– One process updates next_state
• Allow synthesis tool to encode states
(binary, one hot, random, gray code, etc.)
• Consider how initial state will be forced
27
 State machine synthesis issues
• Two-types of FSM models
– Mealy model: outputs = f ( inputs, state)
– Moore model: outputs = f ( state )
• “case” more efficient than “if-then-elsif…” to test
present_state
(later builds a priority encoder)
• Signal assignment consideration
– Assign outputs & next_state for every case/condition.
– If an output or next_state is not assigned something under a certain
condition in the case statement, the synthesis tools will have to
preserve the value with extra latches/flip-flops.
• Left-most value of enumeration type is default simulation
starting value (use reset to initialize real circuit)

28
Design capture tools :

• One of the first tasks a designer needs to do is capture a description of the design

using a HDL (Hardware Description Language). e.g. Verilog or VHDL.

• The objective at this stage is to create high-quality code as quickly as possible

before moving on to the simulation stage

• As design capture can be a very time consuming and error prone process, there
are a number of tools that can help a designer improve productivity and enhance
the quality of the HDL code produced at this stage.
These tools can be classified as:

• Text editors

• Linters

• Graphical editors

• Rule-based checkers
(i) Text Editors:

• Basic text editors offer simple facilities such as the ability to copy and paste text,
search and replace text strings and format text using tabs (tabulation characters)
or spaces.

• Some of the more advanced text editors enable text to be automatically indented
and color-coded whenever certain keywords or constructs are detected.

• Although this facility is useful, because it shows the structure of the captured
code, it does not help in isolating and identifying any coding problems or
syntax errors.
• There are also programmable editors that have language specific modes of
operation that automate and enforce a standard set of coding standards.

• This is normally achieved by using a predefined template that specifies the

coding
standards that will be used by the editor.

• As the information held in the template is fixed it is not very easy for the user to
make changes to the defined coding standards.
(ii) Linters:
• The original concept of `linting'' comes from languages like C and C++ where

linters are used to check for inconsistencies within the code that had been
written.
• For example, checking that a value passed to a procedure or function was the
correct type (i.e. integer, Boolean, string, etc.) and that it matched what had
been declared in the main body of the program.

• Verilog and VHDL have a syntax very similar to C and Pascal respectively, it
was natural for linters to appear for these two HDL languages.
• VHDL is a strongly typed language and this means it is relatively easy task for a
linting tool to check for any inconsistencies in the source code.

• Verilog on the other hand is a loosely typed language that allows registers to be
overloaded or array boundaries to be exceeded.

• So here the linting tool has to detect "logical" coding errors that would otherwise
be
acceptable to Verilog.
• A simple example of this type of coding error is shown below where a vectored net
is
assigned to a signal of a differenta[0]
width.
<= #1 b[1:0]

• Depending upon the sophistication of the linting tool, other forms of checks that may
be applied include: range and index checking, checking whether a variable is used
before it has been assigned and width checking.
(iii) Graphical Editors:

• Consider the task of capturing a complex FSM (Finite State Machine) containing
a large number of states and conditional transitions.

• In this situation a designer is normally faced with the task of writing a series of
involved `case’ constructs where each `case term’ defines a state and the
conditions that must be satisfied in order to move onto the next state.

• Although a designer may be willing to undertake this task at the initial design
stage, it can get very tedious and time-consuming altering the HDL code whenever

changes are made to the operational sequence of the FSM.

• In this particular situation graphical editors can prove very useful, because as well
as
saving time at the design capture stage they also present the designer with a pictorial

•image of the FSM

It is normally thattomakes
easier see theit interactions
easier to understand
between the
the interactions within
various states usingthe
a
FSM.
graphical presentation than trying to decipher a block of HDL source code that may
span a number of printed pages.
 Levels of Abstraction

• Digital system can be represented at different

levels of abstraction
– Behavioral—relationship between input and
output signals, usually boolean expressions
– Structural—description of the collection of gates
and connections, more like a schematic
– Physical
 Basic Structure of a VHDL File
• Entity
– Entity declaration:
interface to outside world;
defines input and output
signals
– Architecture: describes the
entity, contains processes,
components operating
concurrently
 Entity Declaration

entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;

• NAME_OF_ENTITY: user defined

• signal_names: list of signals (both input and
output)
• mode: in, out, buffer, inout
• type: boolean, integer, character, std_logic
Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(
x,y: in std_logic;
sum, carry: out std_logic);
end half_adder;

architecture myadd of half_adder is

begin
sum <= x xor y;
carry <= x and y;
end myadd;
 Processes
• Used in behavioral modeling that allows you to use sequential statements to describe
the behavior of a system over time
[process_label:] process [ (sensitivity_list) ]
begin
list of sequential statements such as:
signal assignments
variable assignments
case statement
exit statement
if statement
loop statement
next statement
null statement
procedure call
wait statement
end process [process_label];
 Full Adder – using Processes
library ieee; -- Process P2 that defines the second half adder
use ieee.std_logic_1164.all; and the OR -- gate
entity FULL_ADDER is P2: process (int1, int2, Cin)
port (A, B, Cin : in std_logic; begin
Sum, Cout : out std_logic); Sum <= int1 xor Cin;
int3 <= int1 and Cin;
end FULL_ADDER; Cout <= int2 or int3;
  end process;
architecture BEHAV_FA of FULL_ADDER is end BEHAV_FA;
signal int1, int2, int3: std_logic;
begin
-- Process P1 that defines the first half adder
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
 Logic Operators
• VHDL provides the following predefined
basic logic operators:
Keyword Definition
and conjunction
or inclusive or
xor exclusive or
xnor* complement exclusive or
nand complement conjunction
nor complement inclusive or
not complement
* only predefined in VHDL-93

Predefined operators are all binary except for ‘not’

Page 43
 Operator Precedence

• Unary ‘not’ has a higher precedence than any

binary operator
• ALL binary operators have the SAME precedence
• Operators with the same precedence are
evaluated left-to-right
• Operators in parentheses are evaluated first;
innermost to outermost order
– Must be used for proper AND - OR evaluation

Page 44
 Body Signal Declarations
• Similar to interface ‘port’ declaration
– must define identifier, type
– signals are internal to body; direction not needed
• Keyword is ‘signal’; declared in declarations part
of body
• Equivalent to defining intermediate circuit signals
for symbolic analysis

E.G.

signal INT1, INT2: BIT;

Page 45
Concurrent Operation Example
entity XOR2_OP is
port
(A, B : in BIT;
Z : out BIT);
end XOR2_OP;

architecture AND_OR_CONC of XOR2_OP is

signal INT1, INT2: BIT;
begin
Z <= INT1 or INT2;
INT2 <= not A and B;
INT1 <= A and not B;
end AND_OR_CONC ;

Page 46
Dataflow VHDL

Page 47
 Bit Vectors

• Signals can be more than one bit (a vector)

– Represent P address and data, function selection,
etc.
• Declaration is similar to single bit signals
– Type is bit_vector or std_logic_vector
• We also must specify vector index range and
direction
– Big indian: (low to high)
– little endian: (high downto low)
Page 48
 Vector Declarations
port (
A, B: in std_logic_vector(7 downto 0);
Z: out std_logic_vector(1 to 16)
);

A and B: 7 6 5 4 3 2 1 0

Z:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Note! The first bit and last bit index numbers define
the number of bits in the vector (i.e. max - min + 1)

Page 49
 Vector Literals

• Single bit binary literals are ‘0’ and ‘1’

• Vector binary literals are “0101”
• For bit_vectors we can also specify values
using octal, decimal, or hexadecimal.
– O”1234” D”1999” X”ABCD”

Page 50
 Vector Logical Operations

• Single bit logical operations also apply to

vectors
– Operands MUST be the same size (generally
applies to all vector operations)
– Assignment target must also have the same
number of bits as the result
– Operations are applied bitwise to operands to
produce the vector result

Page 51
 Vector Operations
Given:

Signal A, B, Z: std_logic_vector(7 downto 0);

Then the following logical operation and assignment

Z <= A and B;

Is equivalent to:

for i  0 to 7
Zi  A i and Bi ;

Page 52
 Relational Operators

• In the previous example we introduced a new

operator, the relational “equals”
– The relational operators are
= (equals) /= (not equals)
> (greater than) < (less than)
>= (greater or equal) <= (less or equal)
– Note that <= (less or equal) is same operator as <=
(signal assignment); i.e. context dependent
– Precedence of relational operators is lower than
logical operators.
Page 53
Structural Modeling in VHDL

Page 54
 Overview

• Component and signal declarations

• Component instantiations
• Hierarchical structures
• Packages
• Name spaces and scope

Page 55
 Schematic Vs. VHDL

• Structural VHDL models the structure of a circuit;

similar to circuit schematic
– Defines the circuit components
– Describes how components are connected
• System behavior or functionality is indirectly
defined; model only lets components work in a
certain, defined way.
– Symbolic analysis allows us to determine functionality
of system from understanding component behaviors

Page 56
 Example Schematic
A
A1 Z
B INT1

A_IN

A
A INT2
B_IN A2 Z B O1 Z Z_OUT
B
C
C_IN

A INT3
A3 Z
B

Page 57
Example Structural VHDL Interface
-- Define the Interface

entity MAJORITY is
port
(A_IN, B_IN, C_IN: in BIT;
Z_OUT : out BIT);
end MAJORITY;

Page 58
 Example VHDL Body
architecture STRUCTURE of MAJORITY is

-- Declaration of components and local signals

component AND2_OP
port (A, B : in BIT; Z : out BIT);
end component;
component OR3_OP
port (A, B, C : in BIT; Z : out BIT);
end component;

signal INT1, INT2, INT3 : BIT;

Page 59
Example VHDL Statement Part
begin

-- Define the component connections

A1: AND2_OP port map (A_IN, B_IN, INT1);

A2: AND2_OP port map (A_IN, C_IN, INT2);
A3: AND2_OP port map (B_IN, C_IN, INT3);
O1: OR3_OP port map (INT1, INT2, INT3, Z_OUT);

end STRUCTURE;

Page 60
 CASE
case <expression> is

when choice1 => seq. Statements 1

when choice2 => seq. Statements 2
*
*
when others => seq. Statements others

end case;

Like the select assignment, the choices may be a single value,a group (c1 | c2
| c3) or a range (c1 to c3)

Page 61
entity CASE_STATEMENT is
   port (A, B, C, X : in   integer range 0 to 15;
            Z              : out integer range 0 to 15;
end CASE_STATEMENT;
  
architecture EXAMPLE of CASE_STATEMENT is
begin
   process (A, B, C, X)
   begin
       case  X  is
          when 0 =>
            Z <= A;
          when  7  |  9 =>
            Z <= B;
          when  1 to 5   =>
            Z <= C;
          when others  =>
            Z <= 0;
       end case;        
   end process;
end EXAMPLE
Page 62
 IF THEN ELSE
If a condition is true the associate
If <condition> then
statements are executed and the rest of
the group are skipped.
seq. Statements
NOTE: the “else if” case is
elsif <condition> then
ELSIF (one word, e missing)
seq. Statements

else

seq. Statements

end if;

Page 63
entity FF is
port (D, CLK : in bit;
Q : out bit);
end FF;

begin Begin
process process
begin begin
wait on CLK; wait until CLK=`1`;
if (CLK = '1') then Q <= D;
Q <= D; end process;
end if; end BEH_2;
end process;
end BEH_1;
Page 64
Following is the VHDL code for a 4-to-1 1-bit MUX using an IF Statement.

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
if (s = "00") then o = a;
elsif (s = "01") then o = b;
elsif (s = "10") then o = c;
else o = d;
end if;
end process;
end archi;
Page 65
Following is the VHDL code for a 4-to-1 1-bit MUX using a Case Statement.

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;

architecture archi of mux is

begin
process (a, b, c, d, s)
begin
case s is
when "00" = o = a;
when "01" = o = b;
when "10" = o = c;
when others = o = d;
end case;
end process;
end archi;
Following is the VHDL code for a 1-of-8 decoder. (ONE HOT)

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
architecture archi of dec is
begin
res = "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
Following is the VHDL code for a 1-of-8 decoder. ( ONE COLD)

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
architecture archi of dec is
begin
res = "11111110" when sel = "000" else
"11111101" when sel = "001" else
"11111011" when sel = "010" else
"11110111" when sel = "011" else
"11101111" when sel = "100" else
"11011111" when sel = "101" else
"10111111" when sel = "110" else
"01111111";
end archi;
Following is the equivalent VHDL code sample for the DFF with a positive-edge
clock.

library ieee;
use ieee.std_logic_1164.all;

entity flop is
port(C, D : in std_logic;
Q : out std_logic);
end flop;

architecture archi of flop is

begin
process (C)
begin
if (C'event and C='1') then
Q = D;
end if;
end process;
end archi;
Following is the equivalent VHDL code for a DFF with a negative-edge clock and
asynchronous clear.

library ieee;
use ieee.std_logic_1164.all;

entity flop is
port(C, D, CLR : in std_logic;
Q : out std_logic);
end flop;

architecture archi of flop is

begin
process (C, CLR)
begin
if (CLR = '1')then
Q = '0';
elsif (C'event and C='0')then
Q = D;
end if;
end process;
end archi;
Following is the equivalent VHDL code for the DFF with a positive-edge clock and
synchronous set.

library ieee;
use ieee.std_logic_1164.all;

entity flop is
port(C, D, S : in std_logic;
Q : out std_logic);
end flop;

architecture archi of flop is

begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
Q = '1';
else
Q = D;
end if;
end if;
end process;
end archi;
Following is VHDL code for a 4-bit unsigned Up counter with asynchronous clear.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp = "0000";
elsif (C'event and C='1') then
tmp = tmp + 1;
end if;
end process;
Q = tmp;
end archi;
Following is the VHDL code for a 4-bit unsigned Down counter with synchronous set.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp = "1111";
else
tmp = tmp - 1;
end if;
end if;
end process;
Q = tmp;
end archi;
Following is the VHDL code for a 4-bit unsigned Up/Down counter with asynchronous
clear.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR, up_down : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then tmp = "0000";
elsif (C'event and C='1') then
if (up_down='1') then tmp = tmp + 1;
else
tmp = tmp - 1;
end if;
end if;
end process;
Q = tmp;