Memory Management

Hardware Implementation
Direct Mapping: 0001 0 1 =5
Main Memory
0 0 1 2 3 Block offset
Block #
Cache Memory 1 4 5 6 7
TAG Line No BO
2 .
0
3 . 0011 00
1
4 .
2
5 .
3
6 .
From the block number,
7 . 0111 1 1 the LSB (here last 2 bit)
8 . Indicates cache
9 . line number

Many to One mapping 10 .

11 .
12 .
13 .
14 .
15 60 61 62 63
1111 00
Cache Line Main Memory
0 0 1 2 3
00 00 00 1 4 5 6 7
01
2 .
10
TAG Cache Line # 11
000000=0
3 .
4 .
00 000001=1 5 .
6 .
000010=2
X 000011=3
7
8
.
.
Memory block # 0 9 .
11
10 .
1 1 0 0 0 0 = 48
11 .
1 1 0 0 0 1 = 49 12 .
13 .
1 1 0 0 1 0 = 50
14 .
1 1 0 0 1 1 = 51 15 60 61 62 63
Memory block # 12
Problem:

MM Size Cache Block TAG bits TAG Directory

Size Size Size
128 KB 16 KB 256B - -
32 GB 32 KB 1 KB - -
- 512 KB 1 KB 7 -
16 GB - 4 KB 10 -
64 MB - - 10 -
- 512 KB - 7 -
Assuming that memory Byte addressable
MM Size Cache Block TAG bits TAG Directory
Size Size Size
128 KB 16 KB 256B 3 3X26 bits
32 GB 32 KB 1 KB - -
- 512 KB 1 KB 7 -
16 GB - 4 KB 10 -
64 MB - - 10 -
- 512 KB - 7 -
Assuming that memory Byte addressable
A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The
processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition
to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an
address is

(A) 11 (B) 14 (C) 16 (D) 27

Answer: (C)

Que-2: Consider the data given in previous question. The size of the cache tag directory is
(B) 160 Kbits (B) 136 bits (C) 40 Kbits (D) 32 bits

Answer: (A)

Que-3: An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The
processor generates 32-bit addresses. The cache controller maintains the tag information for each cache
block comprising of the following.
1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the
cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the
cache?

(C) 4864 bits (B) 6144 bits (C) 6656 bits (D) 5376 bits
 A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as
direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-
associative cache, the length of the TAG field is ______ bits.

(A) 12
(B) 14
(C) 16
(D) 18

Answer: (B) 

Explanation: Type of mapping is direct map; for this direct map, 10 bits are required in its Tag. It is updated to 16
way set Associative map then new tag field size = 10 + log216 = 14 bits, because for k way set associative map
design, log2k bits are additionally required to the number of bits in tag field for Direct map design.

The size of the physical address space of a processor is 2P bytes. The word length is 2W bytes. The
capacity of cache memory is 2N bytes. The size of each cache block is 2M words. For a K-way set-
associative cache memory, the length (in number of bits) of the tag field is

(A) P−N−log2K.  (B) P−N+log2K.   (C) P−N−M−W−log2K. (D) P−N−M−W+log2K

Ans (B)
Q. Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is
empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same
cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesse
to memory blocks
(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)
is repeated 10 times. The number of conflict misses experienced by the cache is ____________ . 
Q. A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct
mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache,
the length of the TAG field is ______ bits.

Q. If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets, How big is the
cache in Megabytes ?

Ans: 16MB

Q. In a two-level cache system, the access times of L1 and L2 caches are 1 and 8 clock cycles, respectively.
The miss penalty from the L2 cache to main memory is 18 clock cycles. The miss rate of L1 cache is twise
that of L2. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rate
of L1 and L2 respectively are:
Q. Did you get any difference in the Programme ? Assuming, the cache has a block size of 4 words each, word size being 4 bytes

Program 1 Program 2

int sum_array(int a[4][4]) { int sum_array(int a[4][4])

int i, j, sum = 0; { int i, j, sum = 0;
for (i = 0; i < 4; i++) for (j = 0; j < 4; j++)
for (j = 0; j < 4; j++) for (i = 0; i < 4; i++)
sum += a[i][j]; sum += a[i][j];
return sum; return sum;
} }
Q. Consider the cache memory size of 16kb, and cache block size is 16
bytes. The processor generates the physical address of 32 bits. Assume
the cache is fully associative. What are the TAG and index bits
__________
(A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits.
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