VISVESVARAYA NATIONAL INSTITUTE OF

TECHNOLOGY , NAGPUR

DETECTION OF CHANGE IN SELF RESONANCE FREQUENCY OF

INDUCTOR FOR MALARIA DETECTION
Guided by
Dr.VASU PULIJALA MOHAN R. SARDAR
MT19MVD017
3rd sem,VLSI DESIGN
 OUTLINE
● INTRODUCTION

● LITERATURE SURVEY

● CONCLUSION & FUTURE WORK

● REFERENCES
 INTRODUCTION
MOTIVATION
● Malaria continues to be a fatal infectious disease and critical in less developed regions of
the world, claiming several lives. Hence, there is need of early detection for its effective
control.
● The prevalent diagnostic methods for malaria are rapid diagnostics tests (RDTs)

1.Fluorescence optical microscopy and antibody based techniques are expensive and
requires skilled technicians

2. Biomarkers based technique needs maintenance, This may affect the stability of the kits
and yield false positive or negative results.

● With all these present concerns, there is an urgent need for a sensitive and reusable
diagnostic method.
PROBLEM STATEMENT :
● Design a circuit in cadence to detect change in self resonant frequency of
an inductor for malaria detection.
● Implement this simulated circuit on PCB.
CHANGE IN INDUCTANCE AND RESONANT FREQUENCY ACCORDING TO MEDIUM OBTAINED
EXPERIMENTALLY

Table.I

● A. P. Hole and V. Pulijala, "An Inductive Based Sensitive and Reusable Sensor for the Detection of Malaria," in IEEE Sensors Journal, doi:
10.1109/JSEN.2020.3016657.
SELF RESONANCE FREQUENCY

Fig.1 Lumped Model of Inductor

Fig.2 Inductance vs Frequency

SELF RESONANCE FREQUENCY
At the SRF of an inductor, all of the following conditions are met:

● Phase angle becomes zero

● The effective inductance is zero, since the negative capacitive reactance (Xc = 1 / jωC) just
cancels the positive inductive reactance (XL = jωL).

A measurement of any of these conditions can be used to determine the SRF of an inductor.
LITERATURE SURVEY
Sr.No Method Technology Phase Supply Voltage Frequency
Node (μm) Noise(dBc/Hz) (V) Range(GHZ)
1. Using D-FF ,delay element and AND
0.25 -78 2.5 0.9 to 0.95
Gate

2. Using D-FF and AND Gate 0.65 -106 1.8 30

3. Domino logic method 0.18 -113.47 1.8 9.6 to 11.06

4. Using D-FF and AND Gate 0.13 -96.2 1 1 to 1.5

5. Nand based D flip flop circuit 0.09 -147 1.2 5

1. Seon Cheol Kim and Youngsik Kim, "A fractional-n PLL frequency synthesizer design," Proceedings. IEEE SoutheastCon, 2005.
2. N. Mahalingam, Y. Wang, B. K. Thangarasu, K. Ma and K. S. Yeo, "A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications," in IEEE
Transactions on Microwave Theory and Techniques, vol. 65, Nov. 2017.
3. J. F. Huang, W. C. Lai, J. Y. Wen and C. C. Mao, "Chip design of 10 GHz low phase noise and small chip area PLL," 2013 8th International Conference on
Communications and Networking in China (CHINACOM), Guilin, 2013.
4. S. K. Saw, P. Meher and S. K. Chakraborty, "Design of high frequency D flip flop circuit for phase detector application," TENCON 2017 - 2017 IEEE Region 10
Conference, Penang, 2017.
5. A. Mishra, G. K. Sharma and D. Boolchandani, "Performance analysis of power optimal PLL design using five-stage CS-VCO in 180nm," 2014 International
Conference on Signal Propagation and Computer Technology (ICSPCT 2014), Ajmer, 2014.
CONCLUSION & FUTURE WORK
● Literature survey has been done .
● At self resonance frequency phase becomes zero.this self resonance frequency detected
using phase detector circuit .
● Design a phase detector circuit in cadence to detect change in self resonant frequency of an
inductor for malaria detection.
● Implement this simulated circuit on PCB.
REFERENCES
● A. P. Hole and V. Pulijala, "An Inductive Based Sensitive and Reusable Sensor for the
Detection of Malaria," in IEEE Sensors Journal, doi: 10.1109/JSEN.2020.3016657.
● N. Mahalingam, Y. Wang, B. K. Thangarasu, K. Ma and K. S. Yeo, "A 30-GHz Power-
Efficient PLL Frequency Synthesizer for 60-GHz Applications," in IEEE Transactions on
Microwave Theory and Techniques, vol. 65, no. 11, pp. 4165-4175, Nov. 2017, doi:
10.1109/TMTT.2017.2699671.
● J. F. Huang, W. C. Lai, J. Y. Wen and C. C. Mao, "Chip design of 10 GHz low phase noise
and small chip area PLL," 2013 8th International Conference on Communications and
Networking in China (CHINACOM), Guilin, 2013, pp. 276-280, doi:
10.1109/ChinaCom.2013.6694605.
● Seon cheol Kim and Youngsik Kim, "A fractional-n PLL frequency synthesizer design,"
Proceedings. IEEE SoutheastCon, 2005., Ft. Lauderdale, FL, USA, 2005, pp. 84-87, doi:
10.1109/SECON.2005.1423222.
● N. Mahalingam, Y. Wang, B. K. Thangarasu, K. Ma and K. S. Yeo, "A 30-GHz Power-
Efficient PLL Frequency Synthesizer for 60-GHz Applications," in IEEE Transactions on
Microwave Theory and Techniques, vol. 65, no. 11, pp. 4165-4175, Nov. 2017, doi:
10.1109/TMTT.2017.2699671.
● J. F. Huang, W. C. Lai, J. Y. Wen and C. C. Mao, "Chip design of 10 GHz low phase noise
and small chip area PLL," 2013 8th International Conference on Communications and
Networking in China (CHINACOM), Guilin, 2013, pp. 276-280, doi:
10.1109/ChinaCom.2013.6694605.
● A. Mishra, G. K. Sharma and D. Boolchandani, "Performance analysis of power optimal
PLL design using five-stage CS-VCO in 180nm," 2014 International Conference on Signal
Propagation and Computer Technology (ICSPCT 2014), Ajmer, 2014, pp. 764-768, doi:
10.1109/ICSPCT.2014.6885029.
● S. K. Saw, P. Meher and S. K. Chakraborty, "Design of high frequency D flip flop circuit for
phase detector application," TENCON 2017 - 2017 IEEE Region 10 Conference, Penang,
2017, pp. 229-233, doi: 10.1109/TENCON.2017.8227867.
THANK YOU !!