Low-cost FPGA based

onboard computer
DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]
1&2
CAPE PENINSULA UNIVERSITY OF TECHNOLOGY, CAPE TOWN, SA
ICCIS 2020
 CONTENTS
• Introduction
• Related work
• Proposed work
• Results and simulations
• Future development
• References
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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 INTRODUCTION

• Small satellite industry growth.

• Satellite structural layers: OBC as main component.
• Performance and functionality of the OBC through FPGAs.
• Commercial-off-the-shelf components (COTS).
• CubeSat standards for internal electronic hardware:
• PC/104 form factor
• Communication: UART and I2C
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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 INTRODUCTION
Basic structural layout of a small satellite

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 RELATED WORK

• The FPGA acts as the primary source for all house keeping and CDH.
• Architecture: OBC platform.
• Previous implementations.
• Satellite applications: Earth observation.

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 PROPOSED WORK

• Hardware design for the FPGA based OBC platform.

• Development board approach.
• Proposed OBC interface.
• Xilinx Spartan-3E FPGA with onboard flash memory.

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 PROPOSED WORK

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 RESULTS AND SIMULATIONS
• Xilinx Spartan 3E OBC testing and simulation.
• First In First Out data transfer and cross clock domains.

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 RESULTS AND SIMULATIONS
• Full FIFO buffer simulation

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 RESULTS AND SIMULATIONS
• UART simulation

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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 • VHDL memory test flow sequence

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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

 FUTURE DEVELOPMENT
• Xilinx FPGA family
• Further Hardwre-in-the-Loop (HIL) simulations

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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

1.
REFERENCES
T. Thai, “Applications for FPGAs on Nanosatellites,” no. April, 2014.
2. A. Hanafi and I. Latachi, “FPGA-based Secondary On-Board Computer System for Low-Earth-Orbit Nano-satellite,”
pp. 1–6, 2017.
3. A. N. Uryu, A Combined Data and Power Management Infrastructure. 2013.
4. K. Varnavas, W. H. Sims, and J. Casas, “The Use of Field Programmable Gate Arrays ( FPGA ) in Small Satellite
Communication Systems,” SPACOMM 2015 Seventh Int. Conf. Adv. Satell. Sp. Commun., pp. 86–89, 2015, [Online].
Available: https://www.thinkmind.org/download.php?articleid=spacomm_2015_4_30_20063.
5. Antunes Sandy, DIY Comms and Control for Amateur Space. Maker Media, Inc, 2015.
6. A. Prasad, Y. Jain, N. Joshi, N. Gupta, V. Singhania, and Y. Sreedharan, “Interfacing Architecture between Telemetry
and On-Board Computer for a Nanosatellite,” pp. 1–6, 2020, doi: 10.1109/aero47225.2020.9172773.
7. C. Hillier and V. Balyan, “Error Detection and Correction On-Board Nanosatellites Using Hamming Codes”, February
2019, Journal of Electrical and Computer Engineering 2019(6):1-15, DOI: 10.1155/2019/3905094.
8. A. H. Lokman et al., “A Review of Antennas for Picosatellite Applications,” Int. J. Antennas Propag., vol. 2017, 2017,
doi: 10.1155/2017/4940656.
9. C. Hillier and V. Balyan, “Effect of Space Radiation on LEO Nanosatellites” Journal of Engineering and
Applied Sciences, 2019, Vol. 14, No. 17, pp. 6843-6857.
10.T. Kuwahara, “FPGA-based reconfigurable on-board computing systems for space applications,” Eng. Sci., 2010,
[Online]. Available: http://elib.uni-stuttgart.de/opus/volltexte/2010/5030/.
11.D. Extra, “Atmel AT45DB161E Pin Configurations and Pinouts,” pp. 1–70, 2012.
12.UG332, “Spartan-3 Generation Configuration,” Xilinx User Guid., vol. 332, 2015.
13.LWABANJI
2013.
TONY LUMBWE, “Development of an onboard computer (OBC) for a CubeSat,” no. May, pp. 1–178,
14.M. Gschwind and V. Salapura, “Optimizing VHDL code for FPGA targets 1 Introduction,” pp. 1–13.
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DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]

THANK YOU FOR YOUR TIME

Paper 32: Low-cost FPGA based

onboard computer

DIRK VAN WYK1[0000-0003-1672-8381] AND VIPIN BALYAN2[0000-0002-5032-8966]