L T P J C

ECE 5017- DIGITAL DESIGN WITH FPGA LAB

2 0 2 4 4
Slot :L5+L6 /L29+L30/L31+L32/L45+L46

Instructor: Dr.K.Sivasankaran,
Associate Professor,
Department of Micro and Nanoelectronics,
School of Electronics Engineering,
Assistant Director, Sponsored Research & Industrial Consultancy
VIT

ksivasankaran@vit.ac.in

9994256440
Outline

• Objective

• Pre-requisite

• Tentative Course Plan

• Evaluation Criteria

• Hardware and Software Details

• Pre-Lab Activities

• Download Links
Objective
To design the combinational and sequential circuits with
Block Diagram /Schematic /IP/Verilog HDL. (Modelsim –
Verilog & Intel Quartus Prime)

To verify the functionality of the design using simulation.

(Modelsim)

To analyse the design after synthesis (Intel Quartus Prime).

To perform timing analysis using Time quest timing analyser.

(Intel Quartus Prime).
Objective

To compute / analyse power using power play power analyser

(Intel Quartus Prime).

To implement the design in Cyclone IV / Cyclone 10 FPGAs.

(Intel Quartus Prime).

To verify the implemented logic using signal tap II logic

analyser. (Intel Quartus Prime).

To develop Configurable System using Qsys and Nios II IDE

Pre-Requisite

• Digital Logic Design

• Basic Computer knowledge (Linux Platform)
• Prior knowledge of Modelsim and Intel Quartus Prime not
Mandatory.
Tentative Course Plan
Week Activity
1 Course Objectives & Plan, Evaluation Procedure / (Tool
Installation)
2 Schematic / Block based combinational & sequential
circuit design – Demo (Practice with examples)
3 Design of Combinational Circuit (Verilog HDL) - Modelsim
- Demo (Practice with examples)
4 Assessment - 1
5 Intel Quartus Prime Sign off – Demo (Practice with
examples)
6 Complex Combinational Circuit Design & Implementation
(Practice with examples)
7 Assesment-2
Tentative Course Plan
Week Activity
8 Sequential Circuit Design & Implementation / Timing
Analysis /Power Analysis – Demo (Practice with
examples)
9 Assessment -3
10 FSM based Design & Implementation / Signal Tap II Logic
Analyser - Demo (Practice with examples)
11 Assessment -4
12 System Design – Demo (Practice with examples)
13 Assessment -5
14 FAT Lab
 Assessment Plan
Assessment Max.Mark Weightage
Assessment -1 20 10
Assessment -2 20 10
Assessment -3 20 15
Assessment -4 20 15
Assessment -5 20 10
FAT 50 40

Note: Check the deadline in VTop for uploading each assessment

document
Hardware Facilities

DE2-115 FPGA Board

Cyclone IV EP4CE115 FPGA – 115K logic
elements (LEs) - 3,888 Embedded
memory (Kbits) -266 Embedded 18 x 18
multipliers - 4 General-purpose PLLs
528 User I/Os

Intel Cyclone 10LP FPGA Evaluation Kit

Intel® Cyclone® 10 LP FPGA P/N: 10CL025YU256I7G -

- 25K LEs
Hardware Facilities

DE10 Nano Board

Intel Cyclone® V SE 5CSEBA6U23I7NDK device
(110K LEs) – Hard-core ARM Processor -
OpenCL

DE10 Standard Board

Cyclone V SX SoC—5CSXFC6D6F31C6N - 110K LEs

- 5,761 Kbits embedded memory-925 MHz, Dual-
Core ARM Cortex-A9 MPCore Processor
Hardware Facilities

DE10 Lite Board

MAX 10 10M50DAF484C7G Device -
Integrated dual ADCs, each ADC supports 1
dedicated analog input and 8 dual function
pins- 50K programmable logic elements -
1,638 Kbit M9K Memory

DE1 SoC Board

Cyclone V SoC 5CSEMA5F31C6 Device - Dual-core
ARM Cortex-A9 (HPS) - 85K Programmable Logic
Elements - 4,450 Kbits embedded memory
6 Fractional PLLs - 2 Hard Memory Controllers
Hardware Facilities
8 Mega Pixel Digital Camera Package with GPIO interface

Multi-Touch LCD Module Second Edition (MTL2)

Mankrit 3.5mm Clip for Microphone |

Creative Multimedia 2.0 Speaker SBS A60

 Software Facilities
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Lab Photos
Pre-Lab Tasks

Design and Implementation of Combinational Circuits

Half and Full Adder, Multiplexer and De-multiplexer, Encoder and

decoder, Parity generator and checker, Magnitude Comparator

Design and Implementation of Sequential Circuits

Flip-Flops, Shift Registers, Counters

Design and Implementation of Arithmetic circuit design

Adders and Multipliers

Pre-Lab Tasks

Design and Implementation of FSM based controller

Sequence detector, Vending machine and Traffic light controller

Interfacing of Peripherals with FPGA using System Design

Download Links

https://vtop.vit.ac.in  Course Page

(Course Material –PPTs,e-book,Assesment Questions, Templates)

How to Download Intel Quartus Prime 18.0?

https://tinyurl.com/ddfpgalec1

How to Install Intel Quartus Prime 18.0?

https://tinyurl.com/ddfpgalec2
Google Drive:
https://tinyurl.com/ECE5017
Task for this Week

• Fundamentals of Digital Logic Design – Refresh

• Download the Intel Quartus Prime and Modelsim.

• Install the Intel Quartus Prime and Modelsim.

 L T P J C
ECE 5017- DIGITAL DESIGN WITH FPGA LAB
2 0 2 4 4
Slot :L5+L6 /L29+L30/L31+L32/L45+L46

Instructor: Dr.K.Sivasankaran,
Associate Professor,
Department of Micro and Nanoelectronics,
School of Electronics Engineering,
Assistant Director, Sponsored Research & Industrial Consultancy
VIT

ksivasankaran@vit.ac.in

9994256440
Slot in VTop
Evaluation Procedure ( J Component)

Component Marks Weightage

Review -1 20 20
Review - 2 30 30
Review - 3 50 50

Introduction Digital Design with FPGA 21

Task for the Week

• Form Team within L31+L32 batch

• Maximum three in a Team
• Register in the following link
https://tinyurl.com/jcomp3