Professional Documents
Culture Documents
Q 8.1 (MCRA)
I 0.0
( MCR< )
M0.0
I1.2 Q 9.3
SR
S Q
I1.3
R
Input
Start of the cycle monitoring time
Module
PII PIQ
User
Byte 0 Program Byte 0
Byte 1 Byte 1
Byte 2 1 Byte 2
: : :
: : : 1
: A I 2.0 :
= Q 4.3
:
:
:
:
CPU Memory Area CPU Memory Area
Recipe A
Pump
OB 1 OB 1 Recipe B OB 1
Mixer
Outlet
Outlet
All instructions are The instructions for the indi- Reuseable functions are loaded
found in one block vidual functions are found in into individual blocks.
(normally in the individual blocks. OB 1 calls the OB 1 (or other blocks) call
organization block OB 1) individual blocks one after the these blocks and pass on the
other. pertinent data.
Operating System
Cycle
Time OB
FB FC SFB
Organization
Process Blocks
FB FB SFC
Error
OB = Organization Block
Legend:
FB = Function Block
FC = Function
SFB = System Function Block
SFC = System Function FB with instance
data block
NO activated
contact LAD: LAD:
Yes 1 “Yes“ “No”
1 0
“NO contact” “NC contact”
not No
activated 0 “No” “Yes”
0 1
FBD: FBD:
& &
NC activated
No 0 “No” “Yes”
contact
0 1
not
STL: STL:
activated Yes 1 “Yes” “No”
A I x.y 1 AN I x.y 0
Hardware
S1 S2 S1 S2 S1 S2
II1.0
1.0 II1.1
1.1 II1.0
1.0 II1.1
1.1 II1.0
1.0 II1.1
1.1
Programmable controller Programmable controller Programmable controller
Q 4.0 Q 4.0 Q 4.0
Software
I 1.0 I 1.1 Q 4.0 I1.0 I1.1 Q 4.0 I1.0 I1.1 Q 4.0
LAD
FDB
I1.1 Q 4.0 I1.1 Q 4.0 I1.1 Q 4.0
Slot No. 1 2 4 5 6 7 8 9 10
Modules PS CPU SM SM SM SM SM SM SM
Address 0.0
Address 0.7
Address 1.0
Address 1.7
PS
IM 32.0 36.0 40.0 44.0 48.0 52.0 56.0 60.0
Rack to to to to to to to to
1 (Receive)
35.7 39.7 43.7 47.7 51.7 55.7 59.7 63.7
Slot 1 2 3 4 5 6 7 8 9 10 11
S1 (I 0.0)
I0.0 I0.1 Q 8.0 I 0.0 & Q 8.0 A I0.0
= A I0.1
AND S2 (I 0.1) I 0.1
= Q 8.0
Q 8.1 Q 8.1 = Q 8.1
=
L1 L2
(Q 8.0) (Q 8.1)
S3
(I 0.2) I0.2 Q 8.2
Q 8.2 O I0.2
S4 I 0.2 >=1
OR = O I0.3
(I 0.3) I 0.3 = Q 8.2
I0.3
L3 (Q 8.2)
Q 8.0 X I0.4
I 0.4 XOR X I0.5
=
I 0.5 = Q8.0
Result of Check
Result of Check
Result of Check
Result of Logic
Result of Logic
Result of Logic
Signal State
Signal State
Signal State
First Check
First Check
First Check
Operation
Operation
Operation
A I 1.0 0 1 1
AN I 1.1 0 1 0
A M 4.0 0 1 1
= Q 8.0
= Q 8.1
A I 2.0 0 1 0
I 1.0 I 1.1
Q 8.0 A I 1.0
I 1.0 & A I 1.1
Assignment ( ) Q 8.0
= Q 8.0
I 1.1 =
I 1.2 I 1.3
Q 8.1 I 1.2 A I 1.2
& Q 8.1
Set (S ) A I 1.3
I 1.3 S S Q 8.1
I 1.4 Q 8.1
(R) I 1.4 O I 1.4
>=1 Q 8.1 O I 1.5
Reset I 1.5 R R Q 8.1
I 1.5
M0.0 M0.0
I1.2 Q 9.3 A I 1.2
SR SR S M 0.0
Dominant S Q I1.2 S
Reset A I 1.3
Q9.3 R M 0.0
I1.3
R = A M 0.0
R I1.3 Q
= Q 9.3
M0.0 M0.0
I1.3 Q 9.3 A I 1.3
Dominant RS RS R M 0.0
R Q I1.3 R
Set A I 1.2
Q9.3 S M 0.0
I1.2
= A M 0.0
S I1.2 S Q
= Q 9.3
LAD STL
A I0.0
I0.0 I0.1
Q8.0 I0.0 & A I0.1
NOT Q8.0
NOT ( ) I0.1 = NOT
= Q8.0
I1.6 A I1.6
SAVE ( SAVE ) I1.6 & SAVE SAVE
BR Q8.1 Q8.1 A BR
BR ( ) BR = = Q 8.1
15 8 1
Status word
BR RLO
I0.0
A I0.0 // Enable MCR
( MCR< ) A0.0 & MCR<
MCR( // Open MCR
NEW1 NEW1
A I1.0
I1.0 I1.1 M1.0 M8.0 I1.0 &
M1.0 M8.0 A I1.1
P FP M1.0
I1.1 P = = M8.0
OB1-Cycle
I1.0
I1.1
RLO
Example
M1.0
M1.1
M8.0
M8.1
Example M1.0
M1.1
OB1-Cycle
M8.0
M8.1
Bottle
sensor
I 16.6 (I 8.6)
M
Q 20.5 (Q 8.5) Conveyor forwards
Q 20.6 (Q 8.6) Conveyor backwards