Digital Logic Design - Revision

NUMBER SYSTEMS – Representation
 Positive radix, positional number systems

 A number with radix r is represented by a
string of digits:
An - 1An - 2 … A1A0 . A- 1 A- 2 … A- m + 1 A- m
in which 0 £ Ai < r and . is the radix point.
 The string of digits represents the power series:
i=n-1 j=-1
(å )+ ( å )
i j
(Number)r =
Ai r Aj r
i=0 j=-m
(Integer Portion) + (Fraction Portion)
Chapter 1 1
Number Systems – Examples
General Decimal Binary

Radix (Base) r 10 2
Digits 0 => r - 1 0 => 9 0 => 1
0 r0 1 1
1 r1 10 2
2 r2 100 4
3 r3 1000 8
Powers of 4 r4 10,000 16
r5 100,000 32
Radix 5 r -1 0.1 0.5
-1 r -2 0.01 0.25
-2 r -3 0.001 0.125
-3 r -4 0.0001 0.0625
-4 r -5 0.00001 0.03125
-5
Chapter 1 2
Special Powers of 2
 210 (1024) is Kilo, denoted "K"
 220 (1,048,576) is Mega, denoted "M"
 230 (1,073, 741,824)is Giga, denoted "G"
 240 (1,099,511,627,776 ) is Tera, denoted “T"
Chapter 1 3
ARITHMETIC OPERATIONS - Binary
Arithmetic
 Single Bit Addition with Carry

 Multiple Bit Addition
 Single Bit Subtraction with Borrow
 Multiple Bit Subtraction
 Multiplication
 BCD Addition
Chapter 1 4
Single Bit Binary Addition with Carry
Given two binary digits (X,Y), a carry in (Z) we get the

following sum (S) and carry (C):
Carry in (Z) of 0: Z 0 0 0 0
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
Carry in (Z) of 1: Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
Chapter 1 5
Multiple Bit Binary Addition
 Extending this to two multiple bit

examples:
Carries 0 0
Augend 01100 10110
Addend +10001 +10111
Sum
 Note: The 0 is the default Carry-In to
the least significant bit.
Chapter 1 6
Single Bit Binary Subtraction with Borrow
 Given two binary digits (X,Y), a borrow in (Z) we
get the following difference (S) and borrow (B):
 Borrow in (Z) of 0: Z
0 0

0

0

X 0 0 1 1

-Y -0 -1 -0 -1

BS 00 11 01 00
 Borrow in (Z) of 1:
Z 1 1 1 1

X 0 0 1 1

-Y -0 -1 -0 -1

BS 11 10 00 11
Chapter 1 7
Multiple Bit Binary Subtraction
 Extending this to two multiple bit examples:

Borrows 0 0
Minuend 10110 10110
Subtrahend - 10010 - 10011
Difference
 Notes: The 0 is a Borrow-In to the least significant
bit. If the Subtrahend > the Minuend, interchange
and append a – to the result.
Chapter 1 8
Binary Multiplication
The binary multiplication table is simple:

00=0 | 10=0 | 01=0 | 11=1
Extending multiplication to multiple digits:
Multiplicand 1011
Multiplier x 101
Partial Products 1011
0000 -
1011 - -
Product 110111
Chapter 1 9
BASE CONVERSION - Positive Powers of 2
 Useful for Base Conversion

Exponent Value Exponent Value
0 1 11 2,048
1 2 12 4,096
2 4 13 8,192
3 8 14 16,384
4 16 15 32,768
5 32 16 65,536
6 64 17 131,072
7 128 18 262,144
8 256 19 524,288
9 512 20 1,048,576
10 1024 21 2,097,152
Chapter 1 10
Converting Binary to Decimal
 To convert to decimal, use decimal arithmetic

to form S (digit × respective power of 2).
 Example:Convert 110102 to N10:
Chapter 1 11
Converting Decimal to Binary
 Method 1
• Subtract the largest power of 2 (see slide 14) that gives
a positive remainder and record the power.
• Repeat, subtracting from the prior remainder and
recording the power, until the remainder is zero.
• Place 1’s in the positions in the binary result
corresponding to the powers recorded; in all other
positions place 0’s.
 Example: Convert 62510 to N2
Chapter 1 12
Commonly Occurring Bases
Name Radix Digits
Binary 2 0,1
Octal 8 0,1,2,3,4,5,6,7
Decimal 10 0,1,2,3,4,5,6,7,8,9
Hexadecimal 16 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
 The six letters (in addition to the 10

integers) in hexadecimal represent:
Chapter 1 13
Numbers in Different Bases
 Good idea to memorize!

Decimal Binary Octal Hexa decimal
(Base 10) (Base 2) (Base 8) (Base 16)
00 00000 00 00
01 00001 01 01
02 00010 02 02
03 00011 03 03
04 00100 04 04
05 00101 05 05
06 00110 06 06
07 00111 07 07
08 01000 10 08
09 01001 11 09
10 01010 12 0A
11 0101 1 13 0B
12 01100 14 0C
13 01101 15 0D
14 01110 16 0E
15 01111 17 0F
16 10000 20 10
Chapter 1 14
Conversion Between Bases
 Method 2
 To convert from one base to another:
1) Convert the Integer Part
2) Convert the Fraction Part
3) Join the two results with a radix point
Chapter 1 15
Conversion Details
 To Convert the Integral Part:

Repeatedly divide the number by the new radix and
save the remainders. The digits for the new radix are
the remainders in reverse order of their computation.
If the new radix is > 10, then convert all remainders >
10 to digits A, B, …
 To Convert the Fractional Part:
Repeatedly multiply the fraction by the new radix and
save the integer digits that result. The digits for the
new radix are the integer digits in order of their
computation. If the new radix is > 10, then convert all
integers > 10 to digits A, B, …
Chapter 1 16
Example: Convert 46.687510 To Base 2
 Convert 46 to Base 2
 Convert 0.6875 to Base 2:
 Join the results together with the

radix point:
Chapter 1 17
Additional Issue - Fractional Part
 Note that in this conversion, the fractional part

can become 0 as a result of the repeated
multiplications.
 In general, it may take many bits to get this to
happen or it may never happen.
 Example Problem: Convert 0.6510 to N2
• 0.65 = 0.1010011001001 …
• The fractional part begins repeating every 4 steps
yielding repeating 1001 forever!
 Solution: Specify number of bits to right of
radix point and round or truncate to this
number.
Chapter 1 18
Checking the Conversion
To convert back, sum the digits times their

respective powers of r.
From the prior conversion of 46.687510
1011102 = 1·32 + 0·16 +1·8 +1·4 + 1·2 +0·1
= 32 + 8 + 4 + 2
= 46
0.10112 = 1/2 + 1/8 + 1/16
= 0.5000 + 0.1250 + 0.0625
= 0.6875
Chapter 1 19
Why Do Repeated Division and
Multiplication Work?
 Divide the integer portion of the power series
on slide 11 by radix r. The remainder of this
division is A0, represented by the term A0/r.
 Discard the remainder and repeat, obtaining
remainders A1, …
 Multiply the fractional portion of the power
series on slide 11 by radix r. The integer part of
the product is A-1.
 Discard the integer part and repeat, obtaining
integer parts A-2, …
 This demonstrates the algorithm for any radix
r >1.
Chapter 1 20
Octal (Hexadecimal) to Binary and
Back
 Octal (Hexadecimal) to Binary:
• Restate the octal (hexadecimal) as three
(four) binary digits starting at the radix
point and going both ways.
 Binary to Octal (Hexadecimal):
• Group the binary digits into three (four) bit
groups starting at the radix point and going
both ways, padding with zeros as needed in
the fractional part.
• Convert each group of three bits to an octal
(hexadecimal) digit.
Chapter 1 21
Octal to Hexadecimal via Binary
 Convert octal to binary.

 Use groups of four bits and convert as above to
hexadecimal digits.
 Example: Octal to Binary to Hexadecimal
6 3 5 . 1 7 7 8
 Why do these conversions work? Chapter 1 22

A Final Conversion Note
 You can use arithmetic in other bases if

you are careful:
 Example: Convert 1011102 to Base 10
using binary arithmetic:
Step 1 101110 / 1010 = 100 r 0110
Step 2 100 / 1010 = 0 r 0100
Converted Digits are 01002 | 01102
or 4 6 10
Chapter 1 23
Binary Numbers and Binary Coding
 Flexibility of representation
• Within constraints below, can assign any binary
combination (called a code word) to any data as long
as data is uniquely encoded.
 Information Types
• Numeric
 Must represent range of data needed
 Very desirable to represent data such that simple,
straightforward computation for common arithmetic
operations permitted
 Tight relation to binary numbers
• Non-numeric
 Greater flexibility since arithmetic operations not applied.
 Not tied to binary numbers
Chapter 1 24
Non-numeric Binary Codes
 Given n binary digits (called bits), a binary code

is a mapping from a set of represented elements
to a subset of the 2n binary numbers.
 Example: A
Color Binary Number
binary code Red 000
for the seven Orange 001
colors of the Yellow 010
rainbow Green 011
Blue 101
 Code 100 is Indigo 110
not used Violet 111
Chapter 1 25
Number of Bits Required
 Given M elements to be represented by a

binary code, the minimum number of
bits, n, needed, satisfies the following
relationships:
2n ³ M > 2(n – 1)
n = log2 M where x , called the ceiling
function, is the integer greater than or
equal to x.
 Example: How many bits are required to
represent decimal digits with a binary
code?
Chapter 1 26
Number of Elements Represented
 Given n digits in radix r, there are rn

distinct elements that can be represented.
 But, you can represent m elements, m <
rn
 Examples:
• You can represent 4 elements in radix r = 2
with n = 2 digits: (00, 01, 10, 11).
• You can represent 4 elements in radix r = 2
with n = 4 digits: (0001, 0010, 0100, 1000).
• This second code is called a "one hot" code.
Chapter 1 27
DECIMAL CODES - Binary Codes for Decimal
Digits
 There are over 8,000 ways that you can chose 10 elements from the 16 binary numbers of 4 bits. A
few are useful:
Decimal 8,4,2,1 Excess3 8,4, - 2, - 1 Gray
0 0000 0011 0000 0000
1 0001 0100 0111 0100
2 0010 0101 0110 0101
3 0011 0110 0101 0111
4 0100 0111 0100 0110
5 0101 1000 1011 0010
6 0110 1001 1010 0011
7 0111 1010 1001 0001
8 1000 1011 1000 1001
9 1001 1 100 1111 1000
Chapter 1 28
Binary Coded Decimal (BCD)
 The BCD code is the 8,4,2,1 code.

 8, 4, 2, and 1 are weights
 BCD is a weighted code
 This code is the simplest, most intuitive binary
code for decimal digits and uses the same
powers of 2 as a binary number, but only
encodes the first ten values from 0 to 9.
 Example: 1001 (9) = 1000 (8) + 0001 (1)
 How many “invalid” code words are there?
 What are the “invalid” code words?
Chapter 1 29
Excess 3 Code and 8, 4, –2, –1 Code
Decimal Excess 3 8, 4, –2, –1

0 0011 0000
1 0100 0111
2 0101 0110
3 0110 0101
4 0111 0100
5 1000 1011
6 1001 1010
7 1010 1001
8 1011 1000
9 1100 1111
 What interesting property is common
to these two codes?
Chapter 1 30
Warning: Conversion or Coding?
 Do NOT mix up conversion of a decimal

number to a binary number with coding
a decimal number with a BINARY
CODE.
 1310 = 11012 (This is conversion)
 13  0001|0011 (This is coding)
Chapter 1 31
BCD Arithmetic
 Given a BCD code, we use binary arithmetic to add the digits:
8 1000 Eight
+5 +0101 Plus 5
13 1101 is 13 (> 9)
 Note that the result is MORE THAN 9, so must be
represented by two digits!

 To correct the digit, subtract 10 by adding 6 modulo 16.
8 1000 Eight
+5 +0101 Plus 5
13 1101 is 13 (> 9)
+0110 so add 6
carry = 1 0011 leaving 3 + cy
0001 | 0011 Final answer (two digits)

 If the digit sum is > 9, add one to the next significant digit
Chapter 1 32
BCD Addition Example
 Add 2905BCD to 1897BCD showing

carries and digit corrections.
0
0001 1000 1001 0111
+ 0010 1001 0000 0101
Chapter 1 33
ALPHANUMERIC CODES - ASCII Character
Codes
 American Standard Code for Information
Interchange (Refer to Table 1 -4 in the text)
 This code is a popular code used to represent
information sent as character-based data. It uses
7-bits to represent:
• 94 Graphic printing characters.
• 34 Non-printing characters
 Some non-printing characters are used for text
format (e.g. BS = Backspace, CR = carriage
return)
 Other non-printing characters are used for record
marking and flow control (e.g. STX and ETX start
and end text areas).
Chapter 1 34
ASCII Properties
ASCII has some interesting properties:
 Digits 0 to 9 span Hexadecimal values 3016 to 3916 .

 Upper case A - Z span 4116 to 5A16 .
 Lower case a - z span 6116 to 7A16 .
 Lower to upper case translation (and vice versa)
occurs by flipping bit 6.
 Delete (DEL) is all bits set, a carryover from when
punched paper tape was used to store messages.

 Punching all holes in a row erased a mistake!
Chapter 1 35
PARITY BIT Error-Detection Codes
 Redundancy (e.g. extra information), in the

form of extra bits, can be incorporated into
binary code words to detect and correct errors.
 A simple form of redundancy is parity, an extra

bit appended onto the code word to make the
number of 1’s odd or even. Parity can detect all
single-bit errors and some multiple-bit errors.
 A code word has even parity if the number of
1’s in the code word is even.
 A code word has odd parity if the number of 1’s
in the code word is odd.
Chapter 1 36
4-Bit Parity Code Example
 Fill in the even and odd parity bits:

Even Parity Odd Parity
Message - Parity Message - Parity
000 - 000
-
001 - 001
-
010 - 010
-
011 - 011
-
100 - 100
-
101 - 101
-
110 - 110
-
111 - 111
 The codeword "1111" has even parity
- and the
codeword "1110" has odd parity. Both can be
used to represent 3-bit data.
Chapter 1 37
GRAY CODE – Decimal
Decimal 8,4,2,1 Gray
0 0000 0000
1 0001 0100
2 0010 0101
3 0011 0111
4 0100 0110
5 0101 0010
6 0110 0011
7 0111 0001
8 1000 1001
9 1001 1000
 What special property does the Gray code have

in relation to adjacent decimal digits?
Chapter 1 38
Logic and Computer Design Fundamentals
Chapter 2 – Combinational Logic Circuits
Part 1 – Gate Circuits and Boolean Equations
Charles Kime & Mano
© 2008 Pearson Education, Inc.
(Hyperlinks are active in View Show mode)

Overview
 Part 1 – Gate Circuits and Boolean Equations

• Binary Logic and Gates
• Boolean Algebra
• Standard Forms
 Part 2 – Circuit Optimization
• Two-Level Optimization
• Map Manipulation
• Practical Optimization (Espresso)
• Multi-Level Circuit Optimization
 Part 3 – Additional Gates and Circuits
• Other Gate Types
• Exclusive-OR Operator and Gates
• High-Impedance Outputs
Chapter 1 40
Binary Logic and Gates
 Binary variables take on one of two values.

 Logical operators operate on binary values and
binary variables.
 Basic logical operators are the logic functions
AND, OR and NOT.
 Logic gates implement logic functions.
 Boolean Algebra: a useful mathematical system
for specifying and transforming logic functions.
 We study Boolean algebra as a foundation for
designing and analyzing digital systems!
Chapter 1 41
Binary Variables
 Recall that the two binary values have
different names:
• True/False
• On/Off
• Yes/No
• 1/0
 We use 1 and 0 to denote the two values.
 Variable identifier examples:
• A, B, y, z, or X for now
1
• RESET, START_IT, or ADD1 later
Chapter 1 42
Logical Operations
 The three basic logical operations are:

• AND
• OR
• NOT
 AND is denoted by a dot (·).
 OR is denoted by a plus (+).
 NOT is denoted by an overbar ( ¯ ), a
single quote mark (') after, or (~) before
the variable.
Chapter 1 43
Notation Examples
 Examples:
• Y = A ×B
is read “Y is equal to A AND B.”
• z = x + y
is read “z is equal to x OR y.”
• X = A
is read “X is equal to NOT A.”
 Note: The statement:
1 + 1 = 2 (read “one plus one equals two”)
is not the same as
1 + 1 = 1 (read “1 or 1 equals 1”).
Chapter 1 44
Operator Definitions
 Operations are defined on the values "0" and "1" for each
operator:
AND OR NOT
0·0=0 0+0=0 0 = 1
0·1=0 0+1=1 1 = 0
1·0=0 1+0=1
1·1=1 1+1=1
Chapter 1 45
Truth Tables
 Truth table - a tabular listing of the values of a

function for all possible combinations of values on its
arguments
 Example: Truth tables for the basic logic operations:
AND
OR NOT
X Y Z = X+Y
X Y Z = X·Y X Z = X
0 0 0
0 0 0 0 1
0 1 0
0 1 1 1 0
1 0 0
1 0 1
1 1 1
1 1 1
Chapter 1 46
Logic Gate Symbols and Behavior
 Logic gates have special symbols:

X X
Z 5 X ·Y Z5 X1 Y X Z5 X
Y Y
AND gate OR gate
(a) Graphic symbols

 And waveform behavior in time as follows:
X 0 0 1 1
Y 0 1 0 1
(AND) X ·Y 0 0 0 1
(OR) X1 Y 0 1 1 1
(NOT) X 1 1 0 0
(b) Timing diagram
Chapter 1 47
Logic Diagrams and Expressions
Truth Table Equation

XYZ F = X + Y × Z
000 0 F = X + Y Z
001 1
010 0 Logic Diagram
011 0 X
100 1
Y F
101 1
110 1 Z
111 1
 Boolean equations, truth tables and logic diagrams describe

the same function!
 Truth tables are unique; expressions and logic diagrams are
not. This gives flexibility in implementing functions.
Chapter 1 48
Boolean Algebra
 An algebraic structure defined on a set of at least two elements, B, together with three binary operators (denoted
+, · and ) that satisfies the following basic identities:
.
1. X +0 = X 2. X 1 = X
.
3. X + 1 = 1 4. X 0 = 0
.
5. X+X = X 6. X X = X
.
7. X+X = 1 8. X X = 0
9. X=X
10. X+Y = Y+X 11. XY = YX Commutative
12. (X + Y) + Z = X + (Y + Z) 13. (XY) Z = X(Y Z) Associative
14. X(Y + Z) = XY + XZ 15. X + YZ = (X + Y) (X + Z) Distributive

. .
16. X+Y = X Y 17. X Y = X+Y DeMorgan ’s
Chapter 1 49
Some Properties of Identities & the Algebra
 If the meaning is unambiguous, we leave out the symbol “·”
 The identities above are organized into pairs. These pairs have names as follows:
1-4 Existence of 0 and 1 5-6 Idempotence
7-8 Existence of complement 9 Involution
10-11 Commutative Laws 12-13 Associative Laws
14-15 Distributive Laws 16-17 DeMorgan’s Laws
 The dual of an algebraic expression is obtained by interchanging + and · and interchanging 0’s
and 1’s.
 The identities appear in dual pairs. When there is only one identity on a line the identity is self-
dual, i. e., the dual expression = the original expression.
Chapter 1 50
Some Properties of Identities & the Algebra (Continued)
 Unless it happens to be self-dual, the dual of an

expression does not equal the expression itself.
 Example: F = (A + C) · B + 0
dual F = (A · C + B) · 1 = A · C + B
 Example: G = X · Y + (W + Z)
dual G =
 Example: H = A · B + A · C + B · C
dual H =
 Are any of these functions self-dual?
Chapter 1 51
Some Properties of Identities & the Algebra
(Continued)
 There can be more that 2 elements in B, i. e.,

elements other than 1 and 0. What are some
common useful Boolean algebras with more
than 2 elements?
1. Algebra of Sets
2. Algebra of n-bit binary vectors
 If B contains only 1 and 0, then B is called the
switching algebra which is the algebra we use
most often.
Chapter 1 52
Boolean Operator Precedence
 The order of evaluation in a Boolean
expression is:
1. Parentheses
2. NOT
3. AND
4. OR
 Consequence: Parentheses appear
around OR expressions
 Example: F = A(B + C)(C + D)
Chapter 1 53
Example 1: Boolean Algebraic Proof
 A + A·B = A (Absorption Theorem)

Proof Steps Justification (identity or theorem)
A + A·B
= A· 1 +A· B X=X·1
= A · ( 1 + B) X · Y + X · Z = X ·(Y + Z)(Distributive Law)
=A· 1 1+X=1
=A X·1=X
 Our primary reason for doing proofs is to learn:

• Careful and efficient use of the identities and theorems of
Boolean algebra, and
• How to choose the appropriate identity or theorem to apply
to make forward progress, irrespective of the application.
Chapter 1 54
Example 2: Boolean Algebraic Proofs
 AB + AC + BC = AB + AC (Consensus Theorem)
AB + AC + BC
= AB + AC + 1 · BC ?
= AB +AC + (A + A) · BC ?
=
Chapter 1 55
Example 3: Boolean Algebraic Proofs
 (X + Y)Z + X Y = Y ( X +Z )
( X + Y ) Z + X Y
=
Chapter 1 56
Useful Theorems
 x× y + x × y = y (x + y )(x + y ) = y M inimizatio n
 x  xy  x x   x  y  x Absorption
 x + x × y = x + y x× (x + y ) = x× y Simplifica tion
 x× y + x × z + y× z = x× y + x × z Consensus
(x + y )×(x + z )× (y + z ) = (x + y )×(x + z)
 x + y = x ×y x ×y = x + y DeMorgan' s Laws
Chapter 1 57
Proof of Simplification
x ×y + x ×y = y (x + y )(x + y ) = y
Chapter 1 58
Proof of DeMorgan’s Laws
x+ y = x ×y x ×y = x + y
Chapter 1 59
Boolean Function Evaluation
F1 = xy z
x y z F1 F2 F3 F4
F2 = x + yz 0 0 0 0 0
F3 = x y z + x y z + x y 0 0 1 0 1
F4 = x y + x z 0 1 0 0 0
0 1 1 0 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
Chapter 1 60
Expression Simplification
 An application of Boolean algebra

 Simplify to contain the smallest number
of literals (complemented and
uncomplemented variables):
A B + A C D + A B D + A C D + A B C D
= AB + ABCD + A C D + A C D + A B D
= AB + AB(CD) + A C (D + D) + A B D
= AB + A C + A B D = B(A + AD) +AC
= B (A + D) + A C 5 literals
Chapter 1 61
Complementing Functions
 Use DeMorgan's Theorem to

complement a function:
1. Interchange AND and OR operators
2. Complement each constant value and
literal
 Example: Complement F = xy z + x y z
F = (x + y + z)(x + y + z)
 Example: Complement G = (a + bc)d + e
G=
Chapter 1 62
Overview – Canonical Forms
 What are Canonical Forms?

 Minterms and Maxterms
 Index Representation of Minterms and
Maxterms
 Sum-of-Minterm (SOM) Representations
 Product-of-Maxterm (POM) Representations
 Representation of Complements of Functions
 Conversions between Representations
Chapter 1 63
Canonical Forms
 It is useful to specify Boolean functions in

a form that:
• Allows comparison for equality.
• Has a correspondence to the truth tables
 Canonical Forms in common usage:
• Sum of Minterms/Product (SOM/SOP)
• Product of Maxterms/Sum (POM/POS)
Chapter 1 64
Minterms
 Minterms are AND terms with every variable

present in either true or complemented form.
 Given that each binary variable may appear
normal (e.g., x) or complemented (e.g., x ), there
are 2n minterms for n variables.
 Example: Two variables (X and Y)produce
2 x 2 = 4 combinations:
(both normal)
XY
(X normal, Y complemented)
X Y
(X complemented, Y normal)
X Y
(both complemented)
X Y
 Thus there are four minterms of two variables.
Chapter 1 65
Maxterms
 Maxterms are OR terms with every variable in

true or complemented form.
 Given that each binary variable may appear
normal (e.g., x) or complemented (e.g., x), there
are 2n maxterms for n variables.
 Example: Two variables (X and Y) produce
2 x 2 = 4 combinations:
X + Y
(both normal)
+
(x normal, y complemented)
X Y
(x complemented, y normal)
X + Y
(both complemented)
X + Y
Chapter 1 66
Maxterms and Minterms
 Examples: Two variable minterms and

maxterms.
Index Minterm Maxterm
0 xy x+y
1 xy x+y
2 xy x+y
3 xy x+y
 The index above is important for describing
which variables in the terms are true and which
are complemented.
Chapter 1 67
Standard Order
 Minterms and maxterms are designated with a subscript
 The subscript is a number, corresponding to a binary
pattern
 The bits in the pattern represent the complemented or
normal state of each variable listed in a standard order.
 All variables will be present in a minterm or maxterm and
will be listed in the same order (usually alphabetically)
 Example: For variables a, b, c:
• Maxterms: (a + b + c), (a + b + c)
• Terms: (b + a + c), a c b, and (c + b + a) are NOT in
standard order.
• Minterms: a b c, a b c, a b c
• Terms: (a + c), b c, and (a + b) do not contain all
variables
Chapter 1 68
Purpose of the Index
 The index for the minterm or maxterm,

expressed as a binary number, is used to
determine whether the variable is shown in the
true form or complemented form.
 For Minterms:
• “1” means the variable is “Not Complemented” and
• “0” means the variable is “Complemented”.
 For Maxterms:
• “0” means the variable is “Not Complemented” and
• “1” means the variable is “Complemented”.
Chapter 1 69
Index Example in Three Variables
 Example: (for three variables)

 Assume the variables are called X, Y, and Z.
 The standard order is X, then Y, then Z.
 The Index 0 (base 10) = 000 (base 2) for three
variables). All three variables are complemented
for minterm 0 ( X , Y , Z ) and no variables are
complemented for Maxterm 0 (X,Y,Z).
• Minterm 0, called m is X Y Z .
0
• Maxterm 0, called M is (X + Y + Z).

0
• Minterm 6 ?
• Maxterm 6 ?
Chapter 1 70
Index Examples – Four Variables
Index Binary Minterm Maxterm

i Pattern mi Mi
0 0000 a b c d abcd
1 0001 a b c d ?
3 0011 ? a + b + c + d
5 0101 a b c d a + b + c + d
7 0111 ? a + b + c + d
10 1010
a b c d a + b + c + d
13 1101
a b c d ?
15 1111 abcd + + +
a b c d
Chapter 1 71
Minterm and Maxterm Relationship
 Review: DeMorgan's Theorem

x · y = x + y and x + y = x × y
 Two-variable example:
M 2
= x + y and m = x· y
2
Thus M2 is the complement of m2 and vice-versa.

 Since DeMorgan's Theorem holds for n variables,
the above holds for terms of n variables
 giving:
M = mi mi = Mi
i
and
Thus Mi is the complement of mi.
Chapter 1 72
Function Tables for Both
 Minterms of Maxterms of
2 variables 2 variables
xy m 0 m 1 m 2 m 3 xy M 0 M 1 M 2 M 3
00 1 0 0 0 00 0 1 1 1
01 0 1 0 0 01 1 0 1 1
10 0 0 1 0 10 1 1 0 1
11 0 0 0 1 11 1 1 1 0
 Each column in the maxterm function table is the

complement of the column in the minterm function
table since Mi is the complement of mi.
Chapter 1 73
Observations
 In the function tables:

• Each minterm has one and only one 1 present in the 2n terms
(a minimum of 1s). All other entries are 0.
• Each maxterm has one and only one 0 present in the 2n terms
All other entries are 1 (a maximum of 1s).
 We can implement any function by "ORing" the
minterms corresponding to "1" entries in the function
table. These are called the minterms of the function.
 We can implement any function by "ANDing" the
maxterms corresponding to "0" entries in the function
table. These are called the maxterms of the function.
 This gives us two canonical forms:
• Sum of Minterms (SOM)
• Product of Maxterms (POM)
for stating any Boolean function.
Chapter 1 74
Minterm Function Example
 Example: Find F1 = m1 + m4 + m7
 F1 = x y z + x y z + x y z
xyz index m1 + m4 + m7 = F1
000 0 0 + 0 + 0 =0
001 1 1 + 0 + 0 =1
010 2 0 + 0 + 0 =0
011 3 0 + 0 + 0 =0
100 4 0 + 1 + 0 =1
101 5 0 + 0 + 0 =0
110 6 0 + 0 + 0 =0
111 7 0 + 0 + 1 =1
Chapter 1 75
Minterm Function Example
 F(A, B, C, D, E) = m2 + m9 + m17 + m23

 F(A, B, C, D, E) =
Chapter 1 76
Maxterm Function Example
 Example: Implement F1 in maxterms:

F1 = M0 · M2 · M3 · M5 · M6
F 1 = (x + y + z) ·(x + y + z)·(x + y + z)
·( x + y + z )·( x + y + z)
xyz i M0  M2  M3  M5  M6 = F1
000 0 0  1  1  1  1 =0
001 1 1  1  1  1  1 =1
010 2 1  0  1  1  1 =0
011 3 1  1  0  1  1 =0
100 4 1  1  1  1  1 =1
101 5 1  1  1  0  1 =0
110 6 1  1  1  1  0 =0
111 7 1  1  1  1  1 =1
Chapter 1 77
Maxterm Function Example
 F( A, B, C, D) = M 3
× M 8
× M 11
× M 14
 F(A, B,C,D) =
Chapter 1 78
Canonical Sum of Minterms
 Any Boolean function can be expressed as a

Sum of Minterms.
• For the function table, the minterms used are the
terms corresponding to the 1's
• For expressions, expand all terms first to explicitly
list all minterms. Do this by “ANDing” any term
missing a variable v with a term ( + ).
v v
 Example: Implement f = x + x y
as a sum of
minterms.
First expand terms:
f = x( y + y ) + x y
Then distribute terms:
f = xy + x y + x y
Express as sum of minterms: f = m3 + m2 + m0
Chapter 1 79
Another SOM Example
 Example: F = A + B C
 There are three variables, A, B, and C which we
take to be the standard order.
 Expanding the terms with missing variables:
 Collect terms (removing all but one of duplicate

terms):
 Express as SOM:
Chapter 1 80
Shorthand SOM Form
 From the previous example, we started with:

F = A + B C
 We ended up with:
F = m1+m4+m5+m6+m7
 This can be denoted in the formal shorthand:
F( A , B, C)  m(1,4,5,6,7 )
 Note that we explicitly show the standard
variables in order and drop the “m”
designators.
Chapter 1 81
Canonical Product of Maxterms
 Any Boolean Function can be expressed as a Product of
Maxterms (POM).
• For the function table, the maxterms used are the terms
corresponding to the 0's.
• For an expression, expand all terms first to explicitly list all
maxterms. Do this by first applying the second distributive
law , “ORing” terms missing variable v with a term equal to
v× v
and then applying the distributive law again.
 Example: Convert to product of maxterms:
f ( x, y, z) = x + x y
Apply the distributive law:
x + x y = (x + x )(x + y ) = 1 × (x + y ) = x + y
Add missing variable z:
x + y + z × z = ( x + y + z ) (x + y + z )
Express as POM: f = M2 · M3
Chapter 1 82
Another POM Example
 Convert to Product of Maxterms:

f(A, B, C) = A C + B C + A B
 Use x + y z = (x+y)·(x+z) with x = (A C + B C), y = A ,
and z = B to get:
f = (A C + B C + A )(A C + B C + B )
 Then use x + x y = x + y
to get:
f = ( C + BC + A )(A C + C + B )
and a second time to get:
f = ( C + B + A )(A + C + B )
 Rearrange to standard order,
to give f = M5 · M2
f = ( A + B + C )(A + B + C)
Chapter 1 83
Function Complements
 The complement of a function expressed as a

sum of minterms is constructed by selecting the
minterms missing in the sum-of-minterms
canonical forms.
 Alternatively, the complement of a function
expressed by a Sum of Minterms form is simply
the Product of Maxterms with the same indices.
 Example: Given F ( x , y , z ) = S m (1, 3, 5, 7 )
F(x, y, z) = S m
( 0, 2,4,6 )
F(x, y, z) = P M
( 1, 3, 5 , 7 )
Chapter 1 84
Conversion Between Forms
 To convert between sum-of-minterms and product-

of-maxterms form (or vice-versa) we follow these
steps:
• Find the function complement by swapping terms in the
list with terms not in the list.
• Change from products to sums, or vice versa.
 Example:Given F as before: F( x, y , z )  m(1, 3,5,7 )
 Form the Complement: F ( x , y , z ) = S
( 0, 2,4,6 )
m
 Then use the other form with the same indices – this
forms the complement again, y , z ) the

F( x, giving Mother
( 0, 2,4form
,6 )
of the original function:
Chapter 1 85
Standard Forms
 Standard Sum-of-Products (SOP) form:

equations are written as an OR of AND terms
 Standard Product-of-Sums (POS) form:
equations are written as an AND of OR terms
 Examples:
• SOP: A B C + A B C + B
• POS: (A + B) · (A + B + C )· C
 These “mixed” forms are neither SOP nor POS
• (A B + C) (A + C)
• A B C + A C (A + B)
Chapter 1 86
Standard Sum-of-Products (SOP)
 A sum of minterms form for n variables

can be written down directly from a truth
table.
• Implementation of this form is a two-level
network of gates such that:
• The first level consists of n-input AND gates,
and
• The second level is a single OR gate (with
fewer than 2n inputs).
 This form often can be simplified so that
the corresponding circuit is simpler.
Chapter 1 87
Standard Sum-of-Products (SOP)
 A Simplification Example:
 F( A , B, C)  m(1,4,5,6,7 )
 Writing the minterm expression:
F = A B C + A B C + A B C + ABC + ABC
 Simplifying:
F=
 Simplified F contains 3 literals compared to 15 in

minterm F
Chapter 1 88
AND/OR Two-level Implementation of SOP
Expression
 The two implementations for F are shown

below – it is quite apparent which is simpler!
A
B
A
C F
A B
B C
C
A
B F
C
A
B
C
A
B
C
Chapter 1 89
SOP and POS Observations
 The previous examples show that:

• Canonical Forms (Sum-of-minterms, Product-of-
Maxterms), or other standard forms (SOP, POS)
differ in complexity
• Boolean algebra can be used to manipulate
equations into simpler forms.
• Simpler equations lead to simpler two-level
implementations
 Questions:
• How can we attain a “simplest” expression?
• Is there only one minimum cost circuit?
• The next part will deal with these issues.
Chapter 1 90
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 Permission is given to incorporate this material or
adaptations thereof into classroom presentations and
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 This Terms of Use slide or page is to be included within
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Chapter 1 91
Part 2 – Circuit Optimization
Charles Kime & Mano

Overview

• Boolean Algebra
• Standard Forms
Chapter 1 93
Circuit Optimization
 Goal: To obtain the simplest

implementation for a given function
 Optimization is a more formal approach
to simplification that is performed using
a specific procedure or algorithm
 Optimization requires a cost criterion to
measure the simplicity of a circuit
 Distinct cost criteria we will use:
• Literal cost (L)
• Gate input cost (G)
• Gate input cost with NOTs (GN)
Chapter 1 94
Literal Cost
 Literal – a variable or it complement

 Literal cost – the number of literal
appearances in a Boolean expression
corresponding to the logic circuit
diagram
 Examples:
• F = BD + A C + A
B C D
L=8
• F = BD + A C + A + AB
B B D C
L=
• F = (A + B)(A + D)(B + C + )( + C + D) L =
D B
• Which solution is best?
Chapter 1 95
Gate Input Cost
 Gate input costs - the number of inputs to the gates in the

implementation corresponding exactly to the given equation
or equations. (G - inverters not counted, GN - inverters counted)
 For SOP and POS equations, it can be found from the
equation(s) by finding the sum of:
• all literal appearances
• the number of terms excluding single literal terms,(G) and
• optionally, the number of distinct complemented single literals (GN).
 Example:
• F = BD + A BC + A C D G = 8, GN = 11
• F = BD + A B C + A B D+ AB C G = , GN =
• F = (A + B)(A + D)(B + C + D)( B
+ + D) G = , GN =
C
• Which solution is best?
Chapter 1 96
Cost Criteria (continued)
 Example 1: GN = G + 2 = 9
 F=A+ B C + B C
L= 5
G=L+2= 7
B
C
A F
 L (literal count) counts the AND inputs and the single
literal OR input.
 G (gate input count) adds the remaining OR gate inputs
 GN(gate input count with NOTs) adds the inverter inputs
Chapter 1 97
Cost Criteria (continued)
 Example 2: A
 F=AB C + A B C B
C
 L = 6 G = 8 GN = 11 F
 F = (A + C)( B + C)( A + B)
 L = 6 G = 9 GN = 12
 Same function and same
A
literal cost
B
 But first circuit has better C
gate input count and better F
gate input count with NOTs
 Select it!
Chapter 1 98
Boolean Function Optimization
 Minimizing the gate input (or literal) cost of a (a

set of) Boolean equation(s) reduces circuit cost.
 We choose gate input cost.
 Boolean Algebra and graphical techniques are
tools to minimize cost criteria values.
 Some important questions:
• When do we stop trying to reduce the cost?
• Do we know when we have a minimum cost?
 Treat optimum or near-optimum cost functions
for two-level (SOP and POS) circuits first.
 Introduce a graphical technique using Karnaugh
maps (K-maps, for short)
Chapter 1 99
Karnaugh Maps (K-map)
 A K-map is a collection of squares

• Each square represents a minterm
• The collection of squares is a graphical representation
of a Boolean function
• Adjacent squares differ in the value of one variable
• Alternative algebraic expressions for the same function
are derived by recognizing patterns of squares
 The K-map can be viewed as
• A reorganized version of the truth table
• A topologically-warped Venn diagram as used to
visualize sets in algebra of sets
Chapter 1 100
Some Uses of K-Maps
 Provide a means for:

• Finding optimum or near optimum
 SOP and POS standard forms, and
 two-level AND/OR and OR/AND circuit
implementations
for functions with small numbers of
variables
• Visualizing concepts related to manipulating
Boolean expressions, and
• Demonstrating concepts used by computer-
aided design programs to simplify large
circuits
Chapter 1 101
Two Variable Maps
 A 2-variable Karnaugh Map:

• Note that minterm m0 and y=0 y=1
minterm m1 are “adjacent” m 0= m 1=

x=0
and differ in the value of the x y x y
variable y m 2= m 3=
x=1
• Similarly, minterm m0 and x y x y
minterm m2 differ in the x variable.

• Also, m1 and m3 differ in the x variable as
well.
• Finally, m2 and m3 differ in the value of the
variable y
Chapter 1 102
K-Map and Truth Tables
 The K-Map is just a different form of the truth table.

 Example – Two variable function:
• We choose a,b,c and d from the set {0,1} to
implement a particular function, F(x,y).
Function Table K-Map
Input Function
Values Value y=0 y=1

(x,y) F(x,y)
x=0 a b
00 a
01 b x=1 c d
10 c
11 d
Chapter 1 103
K-Map Function Representation
 Example: F(x,y) = x F=x y=0 y=1
x=0 0 0
x=1 1 1
 For function F(x,y), the two adjacent cells

containing 1’s can be combined using the
Minimization Theorem:
F(x, y ) = x y + x y = x
Chapter 1 104
K-Map Function Representation
 Example: G(x,y) = x + y G = x+y y=0 y=1
x=0 0 1
x=1 1 1
 For G(x,y), two pairs of adjacent cells containing

1’s can be combined using the Minimization
Theorem:
G (x, y ) = (x y + x y )+ (xy + x y )= x + y
Duplicate x y
Chapter 1 105
Three Variable Maps
 A three-variable K-map:
yz=00 yz=01 yz=11 yz=10
x=0 m0 m1 m3 m2
x=1 m4 m5 m7 m6
 Where each minterm corresponds to the product

terms:
yz=00 yz=01 yz=11 yz=10
x=0 x y z x y z x y z x y z
x=1 x y z x y z x y z x y z
 Note that if the binary value for an index differs in one
bit position, the minterms are adjacent on the K-Map
Chapter 1 106
Alternative Map Labeling
 Map use largely involves:

• Entering values into the map, and
• Reading off product terms from the
map.
 Alternate labelings are useful:
y
yz
y y x 00 01 11 10
0 1 3 2 0 1 3 2
x 0
4 5 7 6
x x
1 4 5 7 6
z z z
z
Chapter 1 107
Example Functions
 By convention, we represent the minterms of F by a "1"

in the map and leave the minterms of F blank
 Example: y
F(x, y, z)  m(2,3,4,5) 0 1 3 2
1 1
4 5 7 6
x 1 1
 Example:
z
G(a, b, c)  m(3,4,6,7) y
 Learn the locations of the 8 0 1 3 2
1
indices based on the variable
4 5 7 6
order shown (x, most significant x 1 1 1
and z, least significant) on the z
map boundaries
Chapter 1 108
Combining Squares
 By combining squares, we reduce number of

literals in a product term, reducing the literal cost,
thereby reducing the other two cost criteria
 On a 3-variable K-Map:
• One square represents a minterm with three
variables
• Two adjacent squares represent a product term with
two variables
• Four “adjacent” terms represent a product term
with one variable
• Eight “adjacent” terms is the function of all ones (no
variables) = 1.
Chapter 1 109
Example: Combining Squares
 Example: Let F  m(2,3,6,7) y

0 1 3 2
1 1
4 5 7 6
x 1 1
z
 Applying the Minimization Theorem three
times:
F(x, y, z) = x y z + x y z + x y z + x y z
= yz + y z
 Thus the four=terms

y that form a 2 × 2 square
correspond to the term "y".
Chapter 1 110
Three-Variable Maps
 Reduced literal product terms for SOP standard

forms correspond to rectangles on K-maps
containing cell counts that are powers of 2.
 Rectangles of 2 cells represent 2 adjacent
minterms; of 4 cells represent 4 minterms that
form a “pairwise adjacent” ring.
 Rectangles can contain non-adjacent cells as
illustrated by the “pairwise adjacent” ring
above.
Chapter 1 111
Three-Variable Maps
 Topological warps of 3-variable K-maps

that show all adjacencies:
 Venn Diagram  Cylinder
0
4 X
6 5
7
Y 3 Z
2 1
Chapter 1 112
Three-Variable Maps
 Example Shapes of 2-cell Rectangles:

y
0 1 3 2
4 5 7 6
x
z
 Read off the product terms for the
rectangles shown
Chapter 1 113
Three-Variable Maps
 Example Shapes of 4-cell Rectangles:

y
0 1 3 2
4 5 7 6
x
z
 Read off the product terms for the
rectangles shown
Chapter 1 114
Three Variable Maps
 K-Maps can be used to simplify Boolean functions by
systematic methods. Terms are selected to cover the
“1s”in the map.

F(x, y, z)  m(1,2,3,5,7)
 Example: Simplify
z x y
y
1 1 1
x 1 1
F(x, y, z) = z + x y
Chapter 1 115
Three-Variable Map Simplification
 Use a K-map to find an optimum SOP

equation for F(X, Y, Z)  m(0,1,2,4,6,7)
Chapter 1 116
Four Variable Maps
 Map and location of minterms:
0 1 3 2
4 5 7 6
X
Variable Order 12 13 15 14
W
8 9 11 10
Chapter 1 117
Four Variable Terms
 Four variable maps can have rectangles corresponding to:

 A single 1 = 4 variables, (i.e. Minterm)
 Two 1s = 3 variables,
 Four 1s = 2 variables
 Eight 1s = 1 variable,
 Sixteen 1s = zero variables (i.e.
Constant "1")
Chapter 1 118
Four-Variable Maps
 Example Shapes of Rectangles:

Y
0 1 3 2
4 5 7 6
X
12 13 15 14
W
8 9 11 10
Chapter 1 119
Four-Variable Maps
 Example Shapes of Rectangles:

Y
0 1 3 2
4 5 7 6
X
12 13 15 14
W
8 9 11 10
Z
Chapter 1 120
Four-Variable Map Simplification
 F(W, X, Y, Z) = S m (0, 2,4,5,6,7, 8,10,13,15 )
Chapter 1 121
Four-Variable Map Simplification
 F(W, X, Y, Z) = Sm (3,4,5,7,9,1 3,14,15 )
Chapter 1 122
Systematic Simplification
 A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent
squares in the map into a rectangle with the number of squares a power of 2.
 A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers
(includes) one or more minterms.
 Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map.
 A set of prime implicants "covers all minterms" if, for each minterm of the function, at least one prime
implicant in the set of prime implicants includes the minterm.
Chapter 1 123
Example of Prime Implicants
 Find ALL Prime Implicants

CD ESSENTIAL Prime Implicants
C C
B D B D
1 1 1
1 1 1
BD 1 1 BD 1 1
B B
1 1 1 1
A A
1 1 1 1 1 1 1 1
A B
D D
AD Minterms covered by single prime implicant

B C
Chapter 1 124
Prime Implicant Practice
 Find all prime implicants for:

F(A, B, C, D)  m(0,2,3,8,9,10,11,12, 13,14,15)
Chapter 1 125
Another Example
 Find all prime implicants for:

G(A, B, C, D)  m(0,2,3,4,7,12,13,14,15)
• Hint: There are seven prime implicants!
Chapter 1 126
Five Variable or More K-Maps
 For five variable problems, we use two adjacent K-maps.

It becomes harder to visualize adjacent minterms for
selecting PIs. You can extend the problem to six
variables by using four K-Maps.
V=0 V=1
Y Y
X X
W W
Z Z
Chapter 1 127
Don't Cares in K-Maps
 Sometimes a function table or map contains entries for

which it is known:
• the input values for the minterm will never occur, or
• The output value for the minterm is not used
 In these cases, the output value need not be defined
 Instead, the output value is defined as a “don't care”
 By placing “don't cares” ( an “x” entry) in the function table
or map, the cost of the logic circuit may be lowered.
 Example 1: A logic function having the binary codes for the
BCD digits as its inputs. Only the codes for 0 through 9 are
used. The six codes, 1010 through 1111 never occur, so the
output values for these codes are “x” to represent “don’t
cares.”
Chapter 1 128
Don't Cares in K-Maps
 Example 2: A circuit that represents a very common situation that

occurs in computer design has two distinct sets of input variables:
• A, B, and C which take on all possible combinations, and
• Y which takes on values 0 or 1.
and a single output Z. The circuit that receives the output Z
observes it only for combinations of A, B, and C such A = 1 and B
= 1 or C = 0, otherwise ignoring it. Thus, Z is specified only for
those combinations, and for all other combinations of A, B, and C,
Z is a don’t care. Specifically, Z must be specified for AB + C = 1,
and is a don’t care for :
AB + C = (A + B)C = AC + BC = 1
 Ultimately, each don’t care “x” entry may take on either a 0 or 1
value in resulting solutions
 For example, an “x” may take on value “0” in an SOP solution
and value “1” in a POS solution, or vice-versa.
 Any minterm with value “x” need not be covered by a prime
implicant.
Chapter 1 129
Example: BCD “5 or More”
 The map below gives a function F1(w,x,y,z) which

is defined as "5 or more" over BCD inputs. With
the don't cares used for the 6 non-BCD
combinations:
y
F1 (w,x,y,z) = w + x z + x y G = 7
0
0
0
1
0
3
0
2  This is much lower in cost than F2 where
0
4
1
5
1
7
1
6
the “don't cares” were treated as "0s."
x
X X X X F2(w, x, y, z) = w x z + w x y + w x y
G = 12
 For this particular function, cost G for the
12 13 15 14
w
1 1 X X
8 9 11 10
POS solution for F1(w,x,y,z) is not changed
z by using the don't cares.
Chapter 1 130
Product of Sums Example
 Find the optimum POS solution:

F(A, B, C, D)  m(3,9,11,12 ,13,14,15) 
d (1,4,6)
• Hint: Use F
and complement it to get the
result.
Chapter 1 131
Optimization Algorithm
 Find all prime implicants.

 Include all essential prime implicants in the
solution
 Select a minimum cost set of non-essential
prime implicants to cover all minterms not yet
covered:
• Obtaining an optimum solution: See Reading
Supplement - More on Optimization
• Obtaining a good simplified solution: Use the
Selection Rule
Chapter 1 132
Prime Implicant Selection Rule
 Minimize the overlap among prime

implicants as much as possible. In
particular, in the final solution, make
sure that each prime implicant selected
includes at least one minterm not
included in any other prime implicant
selected.
Chapter 1 133
Selection Rule Example
 Simplify F(A, B, C, D) given on the K-

map. Selected Essential
C C
1 1 1 1 1
1 1 1 1 1 1 1 1
B B
1 1
A A
1 1 1 1
D D
Minterms covered by essential prime implicants
Chapter 1 134
Selection Rule Example with Don't Cares
 Simplify F(A, B, C, D) given on the K-map.

Selected Essential
C C
1 x 1 x
1 x x 1 1 x x 1
B B
x x
A A
1 1 x 1 1 x
D D
Chapter 1 135
Practical Optimization
 Problem: Automated optimization

algorithms:
• require minterms as starting point,
• require determination of all prime
implicants, and/or
• require a selection process with a potentially
very large number of candidate solutions to
be found.
 Solution: Suboptimum algorithms not
requiring any of the above in the general
case
Chapter 1 136
Example Algorithm: Espresso
 Illustration on a K-map:
C C
1 1 1 1 1X 1X 1X 1X
1 1 1 1 1 1
B B
1 1 1 1 1 1
A A
D D
Original F & EXPAND ESSENTIAL & IRREDUNDANT
COVER
Chapter 1 137
 Continued:
C C
X X X X X X X X
1 1 1 1 1 1
B B
1 1 1 1 1 1
A A
D D
REDUCE EXPAND
Chapter 1 138
 Continued:
C C
X X X X 1 1 1 1
1 1 1 1 1 1
B B
1 1 1 1 1 1
A A
D D
IRREDUNDANT COVER After REDUCE, EXPAND,
IRREDUNDANT COVER,
LAST GASP, QUIT

Chapter 1 139
 This solution costs 2 + 2 + 3 + 3 + 4 = 14

 Finding the optimum solution and comparing:
C
Essential
1 1 1 1
1 1 1
B
Selected 1 1 1
A
 There are two optimum solutions

D one of which is the
one obtained by Espresso.
Chapter 1 140
Multiple-Level Optimization
 Multiple-level circuits - circuits that are

not two-level (with or without input
and/or output inverters)
 Multiple-level circuits can have reduced
gate input cost compared to two-level
(SOP and POS) circuits
 Multiple-level optimization is performed
by applying transformations to circuits
represented by equations while
evaluating cost
Chapter 1 141
Transformations
 Factoring - finding a factored form from

SOP or POS expression
• Algebraic - No use of axioms specific to
Boolean algebra such as complements or
idempotence
• Boolean - Uses axioms unique to Boolean
algebra
 Decomposition - expression of a function
as a set of new functions
Chapter 1 142
Transformations (continued)
 Substitution of G into F - expression

function F as a function of G and some or
all of its original variables
 Elimination - Inverse of substitution
 Extraction - decomposition applied to
multiple functions simultaneously
Chapter 1 143
Transformation Examples
 Algebraic Factoring
F = A C D + A B C + ABC + AC D G = 16
• Factoring:
F = A ( C D + B C ) + A (BC + C D ) G = 16
• Factoring again:
F = A C ( B + D ) + AC (B + D ) G = 12
• Factoring again:
F=( + AC) (B + ) G = 10
A C D
Chapter 1 144
 Decomposition
• The terms B + D and A C + AC can be defined as
new functions E and H respectively,
decomposing F:
F = E H, E = B + D , and H = A C + AC G = 10
 This series of transformations has reduced G from
16 to 10, a substantial savings. The resulting
circuit has three levels plus input inverters.
Chapter 1 145
 Substitution of E into F
• Returning to F just before the final factoring step:
F = A C ( B + D ) + AC (B + D ) G = 12
• Defining E = B + , and substituting in F:
D
F = A C E + ACE G = 10
• This substitution has resulted in the same cost as the
decomposition
Chapter 1 146
 Elimination
• Beginning with a new set of functions:
X=B+C
Y=A+B
Z= AX+CY G = 10
• Eliminating X and Y from Z:
Z = A (B + C) + C (A + B) G = 10
• “Flattening” (Converting to SOP expression):
Z = B + C + AC + BC G = 12
A A
• This has increased the cost, but has provided an new
SOP expression for two-level optimization.
Chapter 1 147
 Two-level Optimization
• The result of 2-level optimization is:
Z= A B+ C G=4
 This example illustrates that:
• Optimization can begin with any set of equations,
not just with minterms or a truth table
• Increasing gate input count G temporarily during a
series of transformations can result in a final
solution with a smaller G
Chapter 1 148
 Extraction
• Beginning with two functions:
E = A B D + A BD
H = B C D + BCD G = 16
• Finding a common factor and defining it as a
function:
F = B D + BD
• We perform extraction by expressing E and H as
the three functions:
F= + BD, E = F, H = CF G = 10
B D A
• The reduced cost G results from the sharing of logic
between the two output functions
Chapter 1 149
Terms of Use
Education, Inc.
edition of Logic and Computer Design Fundamentals
as the course textbook.
 These materials or adaptations thereof are not to be
sold or otherwise offered for consideration.
Chapter 1 150
Part 3 – Additional Gates and Circuits
Charles Kime & Mano

Overview

• Boolean Algebra
• Standard Forms
Chapter 1 152
Other Gate Types
 Why?
• Implementation feasibility and low cost
• Power in implementing Boolean functions
• Convenient conceptual representation
 Gate classifications
• Primitive gate - a gate that can be described using a
single primitive operation type (AND or OR) plus an
optional inversion(s).
• Complex gate - a gate that requires more than one
primitive operation type for its description
 Primitive gates will be covered first
Chapter 1 153
Buffer
 A buffer is a gate with the function F = X:
X F
 In terms of Boolean function, a buffer is the
same as a connection!
 So why use it?
• A buffer is an electronic amplifier used to
improve circuit voltage levels and increase the
speed of circuit operation.
Chapter 1 154
NAND Gate
 The basic NAND gate has the following symbol,

illustrated for three inputs:
• AND-Invert (NAND)
X
Y F( X , Y, Z ) = X × Y × Z
Z
 NAND represents NOT AND, i. e., the AND

function with a NOT applied. The symbol shown
is an AND-Invert. The small circle (“bubble”)
represents the invert function.
Chapter 1 155
NAND Gates (continued)
 Applying DeMorgan's Law gives Invert-OR (NAND)

X
Y F( X , Y, Z ) = X + Y + Z
Z
 This NAND symbol is called Invert-OR, since inputs are

inverted and then ORed together.
 AND-Invert and Invert-OR both represent the NAND
gate. Having both makes visualization of circuit function
easier.
 A NAND gate with one input degenerates to an inverter.
Chapter 1 156
NAND Gates (continued)
 The NAND gate is the natural implementation for

CMOS technology in terms of chip area and speed.
 Universal gate - a gate type that can implement any
Boolean function.
 The NAND gate is a universal gate as shown in Figure 2-
24 of the text.
 NAND usually does not have a operation symbol defined
since
• the NAND operation is not associative, and
• we have difficulty dealing with non-associative mathematics!
Chapter 1 157
NOR Gate
 The basic NOR gate has the following symbol,

illustrated for three inputs:
• OR-Invert (NOR)
X
Y F( X, Y, Z) = X + Y + Z
Z
 NOR represents NOT - OR, i. e., the OR function

with a NOT applied. The symbol shown is an OR-
Invert. The small circle (“bubble”) represents the
invert function.
Chapter 1 158
NOR Gate (continued)
 Applying DeMorgan's Law gives Invert-AND

(NOR)
X
 This NOR symbol is called Invert-AND, since

inputs are inverted and then ANDed together.
 OR-Invert and Invert-AND both represent the
NOR gate. Having both makes visualization of
circuit function easier.
 A NOR gate with one input degenerates to an
inverter. Chapter 1 159
NOR Gate (continued)
 The NOR gate is a natural implementation for some

technologies other than CMOS in terms of chip area
and speed.
 The NOR gate is a universal gate
 NOR usually does not have a defined operation
symbol since
• the NOR operation is not associative, and
• we have difficulty dealing with non-associative
mathematics!
Chapter 1 160
Exclusive OR/ Exclusive NOR
 The eXclusive OR (XOR) function is an important

Boolean function used extensively in logic circuits.
 The XOR function may be;
• implemented directly as an electronic circuit (truly a gate) or
• implemented by interconnecting other gate types (used as a
convenient representation)
 The eXclusive NOR function is the complement of the
XOR function
 By our definition, XOR and XNOR gates are complex
gates.
Chapter 1 161
Exclusive OR/ Exclusive NOR
 Uses for the XOR and XNORs gate include:

• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
 Definitions
• The XOR function is: X Å Y = X Y + X Y
• The eXclusive NOR (XNOR) function, otherwise
known as equivalence is:
X Å Y = X Y + X Y
 Strictly speaking, XOR and XNOR gates do no
exist for more that two inputs. Instead, they are
replaced by odd and even functions.
Chapter 1 162
Truth Tables for XOR/XNOR
 Operator Rules: XOR XNOR

X Y XÅ Y X Y (X Å Y)
or X º Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
 The XOR function

1 1 0
means: 1 1 1
X OR Y, but NOT BOTH

 Why is the XNOR function also known as the
equivalence function, denoted by the operator ?
Chapter 1 163
XOR/XNOR (Continued)
 The XOR function can be extended to 3 or more variables.

For more than 2 variables, it is called an odd function or
modulo 2 sum (Mod 2 sum), not an XOR:
X Å Y Å Z = X Y Z + X Y Z + X Y Z + X Y Z
 The complement of the odd function is the even function.
 The XOR identities:
X Å 0 = X X Å 1 = X
X Å X = 0 X Å X = 1
X Å Y = Y Å X
( X Å Y) Å Z = X Å ( Y Å Z ) = X Å Y Å Z
Chapter 1 164
Symbols For XOR and XNOR
 XOR symbol:
 XNOR symbol:
 Shaped symbols exist only for two inputs
Chapter 1 165
XOR Implementations
 The simple SOP implementation uses the

following structure: X
X Y
 A NAND only implementation is:

X
X Y
Chapter 1 166
Odd and Even Functions
 The odd and even functions on a K-map form

“checkerboard” patterns.
 The 1s of an odd function correspond to minterms
having an index with an odd number of 1s.
 The 1s of an even function correspond to minterms
having an index with an even number of 1s.
 Implementation of odd and even functions for greater
than four variables as a two-level circuit is difficult, so
we use “trees” made up of :
• 2-input XOR or XNORs
• 3- or 4-input odd or even functions
Chapter 1 167
Example: Odd Function Implementation
 Design a 3-input odd function F = X Y+ Z+

with 2-input XOR gates
 Factoring, F = (X +Y) +Z
 The circuit:
Y
F
Z
Chapter 1 168
Example: Even Function Implementation
 Design a 4-input odd function F = W X+ Y

+ Z+
with 2-input XOR and XNOR gates
 Factoring, F = (W +X) +(Y +Z)
 The circuit:
X
F
Chapter 1 169
Parity Generators and Checkers
 In Chapter 1, a parity bit added to n-bit code to produce an n
+ 1 bit code:
• Add odd parity bit to generate code words with even parity
• Add even parity bit to generate code words with odd parity
• Use odd parity circuit to check code words with even parity
• Use even parity circuit to check code words with odd parity
 Example: n = 3. Generate even
X
parity code words of length four
Y
with odd parity generator: P
 Check even parity code words of Z
length four with odd parity checker: X

 Operation: (X,Y,Z) = (0,0,1) gives Y
E
(X,Y,Z,P) = (0,0,1,1) and E = 0. Z
If Y changes from 0 to 1 between P
generator and checker, then E = 1 indicates an error.
Chapter 1 170
Hi-Impedance Outputs
 Logic gates introduced thus far

• have 1 and 0 output values,
• cannot have their outputs connected together, and
• transmit signals on connections in only one direction.
 Three-state logic adds a third logic value, Hi-
Impedance (Hi-Z), giving three states: 0, 1, and Hi-Z
on the outputs.
 The presence of a Hi-Z state makes a gate output as
described above behave quite differently:
• “1 and 0” become “1, 0, and Hi-Z”
• “cannot” becomes “can,” and
• “only one” becomes “two”
Chapter 1 171
Hi-Impedance Outputs (continued)
 What is a Hi-Z value?

• The Hi-Z value behaves as an open circuit
• This means that, looking back into the circuit, the output
appears to be disconnected.
• It is as if a switch between the internal circuitry and the
output has been opened.
 Hi-Z may appear on the output of any gate, but we
restrict gates to:
• a 3-state buffer, or
• Optional: a transmission gate (See Reading Supplement:
More on CMOS Circuit-Level Design),
each of which has one data input and one control
input.
Chapter 1 172
The 3-State Buffer
 For the symbol and truth table, IN
is the data input, and EN, the Symbol
control input.
 For EN = 0, regardless of the IN OUT
value on IN (denoted by X), the

output value is Hi-Z. EN
 For EN = 1, the output value Truth Table

follows the input value.
 Variations: EN IN OUT
• Data input, IN, can be inverted 0 X Hi-Z

• Control input, EN, can be inverted
1 0 0
by addition of “bubbles” to signals.
1 1 1
Chapter 1 173
Resolving 3-State Values on a Connection
 Connection of two 3-state buffer Resolution Table

outputs, B1 and B0, to a wire, OUT
 Assumption: Buffer data inputs can B1 B0 OUT
take on any combination of values 0
and 1 0 Hi-Z 0
 Resulting Rule: At least one buffer
output value must be Hi-Z. Why? 1 Hi-Z 1
 How many valid buffer output Hi-Z 0 0
combinations exist?
 What is the rule for n 3-state buffers Hi-Z 1 1
connected to wire, OUT?
 How many valid buffer output Hi-Z Hi-Z Hi-Z
combinations exist?
Chapter 1 174
3-State Logic Circuit
 Data Selection Function: If s = 0, OL = IN0, else OL = IN1
 Performing data selection with 3-state buffers:
EN0 IN0 EN1 IN1 OL
0 X 1 0 0
0 X 1 1 1
IN0
1 0 0 X 0 OL
EN0
1 1 0 X 1 S
0 X 0 X X IN1
EN1
 Since EN0 = S and EN1 = S, one of the two buffer outputs is

always Hi-Z plus the last row of the table never occurs.
Chapter 1 175
More Complex Gates
 The remaining complex gates are SOP or

POS structures with and without an output
inverter.
 The names are derived using:
• A - AND
• O - OR
• I - Inverter
• Numbers of inputs on first-level “gates” or
directly to second-level “gates”
Chapter 1 176
More Complex Gates (continued)
 Example: AOI - AND-OR-Invert consists of a

single gate with AND functions driving an OR
function which is inverted.
 Example: 2-2-1 AO has two 2-input ANDS
driving an OR with one additional OR input
 These gate types are used because:
• the number of transistors needed is fewer than required
by connecting together primitive gates
• potentially, the circuit delay is smaller, increasing the
circuit operating speed
Chapter 1 177
Terms of Use
Education, Inc.
edition of Logic and Computer Design Fundamentals as
the course textbook.
 These materials or adaptations thereof are not to be sold or
otherwise offered for consideration.
Chapter 1 178
Chapter 3 – Combinational Logic Design
Part 1 – Implementation Technology and Logic Design
Charles Kime & Mano

Overview
 Part 1 – Design Procedure

• Steps
 Specification
 Formulation
 Optimization
 Technology Mapping
• Beginning Hierarchical Design
• Technology Mapping - AND, OR, and NOT to NAND or
NOR
• Verification
 Manual
 Simulation
Chapter 1 180
Overview (continued)
 Part 2 – Combinational Logic

• Functions and functional blocks
• Rudimentary logic functions
• Decoding using Decoders
 Implementing Combinational Functions with
Decoders
• Encoding using Encoders
• Selecting using Multiplexers
Multiplexers
Chapter 1 181
Combinational Circuits
 A combinational logic circuit has:

• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2 inputm
combinations to an output such that the current output

depends only on the current input values
 A block diagram:
Combinatorial
Logic
Circuit
m Boolean Inputs
n Boolean Outputs
Chapter 1 182
Design Procedure
1. Specification
• Write a specification for the circuit if one is not
already available
2. Formulation
• Derive a truth table or initial Boolean equations that
define the required relationships between the inputs
and outputs, if not in the specification
• Apply hierarchical design if appropriate
3. Optimization
• Apply 2-level and multiple-level optimization
• Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters
Chapter 1 183
Design Procedure
4. Technology Mapping
• Map the logic diagram or netlist to the
implementation technology selected
5. Verification
• Verify the correctness of the final design
manually or using simulation
Chapter 1 184
Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to
each BCD code word
• Implementation:
 multiple-level circuit
 NAND gates (including inverters)
Chapter 1 185
Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables Input BCD Output Excess-3
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
• Variables 0001 0100
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
- BCD 1010 0110 1001
0111 1010
to 1111 1000 1011
1001 1011
Chapter 1 186
3. Optimization z
C
y
C
a.
1 1 1 1
2-level using
0 1 3 2 0 1 3 2
1 1 1 1
K-maps
4 5 7 6 4 5 7 6
X X X X B X X X X B
12 13 15 14 12 13 15 14
W = A + BC + BD A 1
8 9
X
11
X
10
A 1
8 9
X
11
X
10
X = BC + BD + BC D
D D
Y = CD + C D
Z= D
x C C
w
1 1 1
0 1 3 2 0 1 3 2
1 1 1 1
4 5 7 6 4 5 7 6
X X X X B X X X X B
12 13 15 14 12 13 15 14
A 1 X X A 1 1 X X
8 9 11 10 8 9 11 10
D Chapter 1 D 187
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = B C + BD + B C D
Y = CD + C D
Z= D G = 7 + 10 + 6 + 0 = 23
• Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = B T1 + B C D
Y = CD + C D
Z= D G = 2 + 1 + 4 + 7 + 6 + 0 = 19
Chapter 1 188
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = B T1 + B C D
Y = CD + C D
Z = D G = 19
• An additional extraction not shown in the text since it uses a
Boolean transformation: ( = C +C DD = ): T1
W = A + BT1
X = B T1 + B T1
Y = CD + T1
Z= D G = 2 +1 + 4 + 6 + 4 + 0 = 16!
Chapter 1 189
4. Technology Mapping
• Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A A
W
W
B
X
B
X
C
C
DY Y
D
Z
Chapter 1 190
Beginning Hierarchical Design
 To control the complexity of the function mapping inputs to

outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a hierarchy
 Example: 9-input parity tree (see next slide)
• Top Level: 9 inputs, one output
• 2nd Level: Four 3-bit odd parity trees in two levels
• 3rd Level: Two 2-bit exclusive-OR functions
• Primitives: Four 2-input NAND gates
• Design requires 4 X 2 X 4 = 32 2-input NAND gates
Chapter 1 191
Hierarchy for Parity Tree Example
X0
X1
X2
9-Input
X3
X4 odd Z O
X5 function
X6 X0 A 0
3-Input
X7
X8 X1 A 1
odd B O
function
X A
(a) Symbol for circuit 2 2
X 3
A 0
A 0
3-Input 3-Input
X4 A odd B A odd B Z
1 O 1 O O
function function
X5 A 2
A 2
X6 A 0
3-Input
X7 A odd B
1 O
function
X8 A 2
(b) Circuit as interconnected 3-input odd
function blocks
A 0
A 1 B O
A 2
(c) 3-input odd function circuit as
interconnected exclusive-OR
blocks
(d) Exclusive-OR block as interconnected
NANDs
Chapter 1 192
Reusable Functions
 Whenever possible, we try to decompose a

complex design into common, reusable
function blocks
 These blocks are
• verified and well-documented
• placed in libraries for future use
Chapter 1 193
Top-Down versus Bottom-Up
 A top-down design proceeds from an abstract, high-level

specification to a more and more detailed design by
decomposition and successive refinement
 A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
 Design usually proceeds top-down to known building
blocks ranging from complete CPUs to primitive logic
gates or electronic components.
 Much of the material in this chapter is devoted to learning
about combinational blocks used in top-down design.
Chapter 1 194
Technology Mapping
 Mapping Procedures
• To NAND gates
• To NOR gates
• Mapping to multiple types of logic blocks in
covered in the reading supplement: Advanced
Technology Mapping.
Chapter 1 195
Mapping to NAND gates
 Assumptions:
• Gate loading and delay are ignored
• Cell library contains an inverter and n-input NAND
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points, and
• Canceling inverter pairs
Chapter 1 196
NAND Mapping Algorithm
1. Replace ANDs and ORs:

. .
. .
. .
. .
. .
. .
2. Repeat the following pair of actions until there is

at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
. .
. .
. .
Chapter 1 197
NAND Mapping Example
A A X
5
B B
6
Y OI
7 2
F 1
C C F
4
3
D D 8 9
E E
(a) (b)
A
B
X
5
C F
6
Y
5 7 D
(c) (d)
Chapter 1 198
Mapping to NOR gates
 Assumptions:
• Gate loading and delay are ignored
• Cell library contains an inverter and n-input NOR
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points, and
• Canceling inverter pairs
Chapter 1 199
NOR Mapping Algorithm
1. Replace ANDs and ORs:

. .
. .
. .
. .
. .
. .
2. Repeat the following pair of actions until there is

at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
. .
. .
. .
Chapter 1 200
NOR Mapping Example
A A
B
B
2
X
1
F
C
C F
3
D
D
E
A E
(a)
(b)
C
F
(c)
Chapter 1 201
Verification
 Verification - show that the final circuit designed

implements the original specification
 Simple specifications are:
• truth tables
• Boolean equations
• HDL code
 If the above result from formulation and are not
the original specification, it is critical that the
formulation process be flawless for the
verification to be valid!
Chapter 1 202
Basic Verification Methods
 Manual Logic Analysis

• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth table,
or
• Show that the Boolean equations for the final circuit are equal to
the specified Boolean equations
 Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL description
using test input values that fully validate correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification
Chapter 1 203
Verification Example: Manual Analysis
 BCD-to-Excess 3 Code Converter

• Find the SOP Boolean equations from the final circuit.
• Find the truth table from these equations
• Compare to the formulation truth table
 Finding the Boolean Equations:
T1 = C + D = C + D
W = A (T1 B) = A + B T1
X = (T1 B) (B ) = T1 + B
Y =C + D C= CD
D +B C D
D C C D
Chapter 1 204
Verification Example: Manual Analysis
 Find the circuit truth table from the equations and compare to
specification truth table:
Input BCD Output Excess -3
AB CD WXYZ
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1011
The tables match! Chapter 1 205

Verification Example: Simulation
 Simulation procedure:
• Use a schematic editor or text editor to enter a
gate level representation of the final circuit
• Use a waveform editor or text editor to enter a
test consisting of a sequence of input
combinations to be applied to the circuit
 This test should guarantee the correctness of the
circuit if the simulated responses to it are correct
 Short of applying all possible “care” input
combinations, generation of such a test can be
difficult
Chapter 1 206
 Enter BCD-to-Excess-3 Code Converter Circuit Schematic

A
INV W
NAND2
NAND2
INV
NOR2
B
INV
NAND2 X
NAND2
C
INV
NAND3 AOI symbol
D not available
INV AND2
Y
NOR2
AND2 AOI
Z
Chapter 1 207
 Enter waveform that applies all possible input combinations:
INPUTS
A
B
C
D
0 50 ns 100 ns
 Are all BCD input combinations present? (Low is a 0 and high is

a one)
Chapter 1 208
 Run the simulation of the circuit for 120 ns

INPUTS
A
B
C
D
OUTPUTS
W
X
Y
Z
 Do0the simulation output combinations

50 ns 100 ns
match the original truth
table?
Chapter 1 209
Terms of Use
Education, Inc.
Chapter 1 210
Chapter 3 – Combinational Logic Design
Part 2 – Combinational Logic
Charles Kime & Mano
2008 Pearson Education, Inc.

Overview
 Part 2 – Combinational Logic

• Functions and functional blocks
• Rudimentary logic functions
• Decoding using Decoders
Decoders
• Encoding using Encoders
• Selecting using Multiplexers
Multiplexers
Chapter 1 212
Functions and Functional Blocks
 The functions considered are those found to be very

useful in design
 Corresponding to each of the functions is a
combinational circuit implementation called a
functional block.
 In the past, functional blocks were packaged as
small-scale-integrated (SSI), medium-scale
integrated (MSI), and large-scale-integrated (LSI)
circuits.
 Today, they are often simply implemented within a
very-large-scale-integrated (VLSI) circuit.
Chapter 1 213
Rudimentary Logic Functions
 Functions of a single variable X

 Can be used on the TA BLE 4-1
inputs to functional Functions of One V a ria b le
blocks to implement X F =0 F =X F = X F=1
other than the block’s

0 0 0 1 1
intended function 1 0 1 0 1
V CC or V DD
1 F5 1 F5 1 X F5 X
(c)
0 F5 0 F5 0
X F5 X
(a) (b) (d)

Chapter 1 214
Multiple-bit Rudimentary Functions
 Multi-bit Examples:
A F3 A
2
3
1 2 2:1 F(2:1)
F2 1 4 4
F F
0 F1 0 1
0 (c)
A F0 A
3
(a) (b)
 A wide line is used to represent 4 3,1:0 F(3), F(1:0)
F
a bus which is a vector signal
(d)
 In (b) of the example, F = (F3, F2, F1, F0) is a bus.
 The bus can be split into individual bits as shown in (b)
 Sets of bits can be split from the bus as shown in (c)
for bits 2 and 1 of F.
 The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0
of F.
Chapter 1 215
Enabling Function
 Enabling permits an input signal to pass through

to an output
 Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value
 The value on the output when it is disable can be
Hi-Z (as for three-state buffers and transmission
X
gates), 0 , or 1 EN
F
 When disabled, 0 output (a)
 When disabled, 1 output
X
 See Enabling App in text EN
F
(b) Chapter 1 216

Decoding
 Decoding - the conversion of an n-bit input

code to an m-bit output code with
n £ m £ 2n such that each valid code word
produces a unique output code
 Circuits that perform decoding are called
decoders
 Here, functional blocks for decoding are
• called n-to-m line decoders, where m £ 2 , and
n
• generate 2 (or fewer) minterms for the n input

n
variables
Chapter 1 217
Decoder Examples
 1-to-2-Line Decoder A D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
 2-to-4-Line Decoder (a) (b)
A 0
A 1 A 0 D 0 D 1 D 2 D 3
A 1
0 0 1 0 0 0
D 0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D 1 5 A 1 A 0
(a)
D 2 5 A 1 A 0
 Note that the 2-4-line
made up of 2 1-to-2- D 3 5 A 1 A 0
line decoders and 4 AND gates.

(b)
Chapter 1 218
Decoder Expansion
 General procedure given in book for any decoder with n

inputs and 2n outputs.
 This procedure builds a decoder backward from the
outputs.
 The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1.
 These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached.
 The procedure can be modified to apply to decoders with
the number of outputs ≠ 2n
Chapter 1 219
Decoder Expansion - Example 1
 3-to-8-line decoder
• Number of output ANDs = 8
• Number of inputs to decoders driving output ANDs = 3
• Closest possible split to equal
• 2-to-4-line decoder
 Number of output ANDs = 4
 Number of inputs to decoders driving output ANDs = 2
 Closest possible split to equal
• Two 1-to-2-line decoders
 See next slide for result

Chapter 1 220
 Result 4 2-input ANDs 8 2-input ANDs
D0
A0
D1
A1
D2
2-to-4-Line D3
decoder
D4
A2 D5
1-to-2-Line decoders D6
D7
3-to-8 Line decoder
Chapter 1 221
• Number of output ANDs = 128
• Number of inputs to decoders driving output ANDs = 7
• Closest possible split to equal
 Number of output ANDs = 16
 Number of inputs to decoders driving output ANDs = 2
 Closest possible split to equal
• 2 2-to-4-line decoders
• Complete using known 3-8 and 2-to-4 line decoders
Chapter 1 222
Decoder with Enable
 In general, attach m-enabling circuits to the outputs

 See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
 Alternatively, can be viewed as distributing value of signal EN to
1 of 4 outputs EN
A
 In this case, called a
1
demultiplexer A 0
D 0
EN A 1 A 0 D0 D1 D2 D3 D1
0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0
(b)
Chapter 1 223
Combinational Logic Implementation
- Decoder and OR Gates
 Implement m functions of n variables with:

• Sum-of-minterms expressions
• One n-to-2n-line decoder
• m OR gates, one for each output
 Approach 1:
• Find the truth table for the functions
• Make a connection to the corresponding OR from the
corresponding decoder output wherever a 1 appears in
the truth table
 Approach 2
• Find the minterms for each output function
• OR the minterms together
Chapter 1 224
Decoder and OR Gates Example
 Implement the following set of odd parity functions of (A7,

A6, A5, A3)
P1 = A7 + A5 + A3 A7 0 P1
P2 = A7 + A6 + A3
1
A6
2
+ +
P4 = A7 A6 A5 A5 3
4 P2
 Finding sum of A4
5
minterms expressions 6
P1 = Sm(1,2,5,6,8,11,12,15)
8
9
P4
P2 = Sm(1,3,4,6,8,10,13,15) 10
P4 = Sm(2,3,4,5,8,9,14,15)
11
12
 Find circuit 13
14
 Is this a good idea? 15
Chapter 1 225
Encoding
 Encoding - the opposite of decoding - the conversion of

an m-bit input code to a n-bit output code with n £ m £
2n such that each valid code word produces a unique
output code
 Circuits that perform encoding are called encoders
 An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding to
the input values
 Typically, an encoder converts a code containing exactly
one bit that is 1 to a binary code corres-ponding to the
position in which the 1 appears.
Chapter 1 226
Encoder Example
 A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal digits 0
through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit D is a 1, then the output
i
(A3, A2, A1, A0) is the BCD code for i,
 The truth table could be formed, but
alternatively, the equations for each of the
four outputs can be obtained directly.
Chapter 1 227
Encoder Example (continued)
 Input Di is a term in equation Aj if bit Aj is 1 in

the binary value for i.
 Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
 F1 = D6 + D7 can be extracted from A2 and A1 Is
there any cost saving?
Chapter 1 228
Priority Encoder
 If more than one input value is 1, then the

encoder just designed does not work.
 One encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
 Among the 1s that appear, it selects the
most significant input position (or the least
significant input position) containing a 1
and responds with the corresponding
binary code for that position.
Chapter 1 229
Priority Encoder Example
 Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most
significant 1 present - Code outputs A2, A1, A0 and V where V indicates at
least one 1 present.
No. of Min- Inputs Outputs
terms/Row D4 D3 D2 D1 D0 A2 A1 A0 V
1 0 0 0 0 0 X X X 0
1 0 0 0 0 1 0 0 0 1
2 0 0 0 1 X 0 0 1 1
4 0 0 1 X X 0 1 0 1
8 0 1 X X X 0 1 1 1
16 1 X X X X 1 0 0 1
 Xs in input part of table represent 0 or 1; thus table entries correspond to
product terms instead of minterms. The column on the left shows that all 32
minterms are present in the product terms in the table
Chapter 1 230
Priority Encoder Example (continued)
 Could use a K-map to get equations, but can

be read directly from table and manually
optimized if careful:
A2 = D4
A1 = D4 D3 + D2 =
D4 D3 D4 1F , F1 = (D3 + D2)
A0 = D4 D3 + D4 D3 D2D1 = D4(D3 + D1)
D2
V = D4 + F1 + D1 + D0
Chapter 1 231
Selecting
 Selecting of data or information is a critical

function in digital systems and computers
 Circuits that perform selecting have:
• A set of information inputs from which the selection is
made
• A single output
• A set of control lines for making the selection
 Logic circuits that perform selecting are called
multiplexers
 Selecting can also be done by three-state logic or
transmission gates
Chapter 1 232
Multiplexers
 A multiplexer selects information from an

input line and directs the information to an
output line
 A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
 A multiplexer can be designed to have m
information inputs with m < 2n as well as n
selection inputs
Chapter 1 233
2-to-1-Line Multiplexer
 Since 2 = 21, n = 1
 The single selection variable S has two values:
• S = 0 selects input I 0
• S = 1 selects input I 1
 The equation:
Y = S I0 + SI1
Enabling
 The circuit: Decoder Circuits
I0
Y
S
I1
Chapter 1 234
2-to-1-Line Multiplexer (continued)
 Note the regions of the multiplexer circuit shown:

• 1-to-2-line Decoder
• 2 Enabling circuits
• 2-input OR gate
 To obtain a basis for multiplexer expansion, we combine
the Enabling circuits and OR gate into a 2 ´ 2 AND-OR
circuit:
• 2 ´ 2 AND-OR
 In general, for an 2n-to-1-line multiplexer:
• n-to-2n-line decoder
• 2n ´ 2 AND-OR
Chapter 1 235
Example: 4-to-1-line Multiplexer
 22 ´ 2 AND-OR
Decoder
S1
4 3 2 AND-OR
S0
Decoder
S1
S0
Y
I1
Y
I2
I3
Chapter 1 236
Multiplexer Width Expansion
 Select “vectors of bits” instead of “bits”

 Use multiple copies of 2n ´ 2 AND-OR in parallel
4 3 2 AND-OR
 Example: I 0,0
Y0
4-to-1-line
.
.
.
quad multi- A0
D0
I 3,0
I 0,1
4 3 2 AND-OR
plexer . Y1
2-to-4-Line decoder . .
. .
.
D3
A1 I 3,1 4 3 2 AND-OR
I 0,2
Y2
.
.
.
I 3,2 4 3 2 AND-OR
I 0,3
Y3
I 3,3
Chapter 1 237
Other Selection Implementations
 Three-state logic in place of AND-OR

S0
I0
I1
S1
I2
I3
 Gate input cost = 14 compared to 22 (or 18)

for gate implementation
Chapter 1 238
- Multiplexer Approach 1
 Implement m functions of n variables with:

• Sum-of-minterms expressions
• An m-wide 2n-to-1-line multiplexer
 Design:
• Find the truth table for the functions.
• In the order they appear in the truth table:
 Apply the function input variables to the multiplexer inputs Sn
- 1, … , S0
 Label the outputs of the multiplexer with the output variables

• Value-fix the information inputs to the multiplexer
using the values from the truth table (for don’t cares,
apply either 0 or 1)
Chapter 1 239
Example: Gray to Binary Code
 Design a circuit to Gray Binary
convert a 3-bit Gray ABC xyz
0 0 0 0 0 0
code to a binary code 10 0 0 01
 The formulation gives 1 10 010
010 01 1
the truth table on the 01 1 10 0
right 1 1 1 101
 It is obvious from this 101
0 01
1 10
1 1 1
table that X = C and the
Y and Z are more complex
Chapter 1 240
Gray to Binary (continued)
 Rearrange the table so Gray Binary

that the input combinations ABC xyz
000 000
are in counting order 001 111
010 011
 Functions y and z can 011 100
100 001
be implemented using
101 110
a dual 8-to-1-line 110 010
multiplexer by: 111 101
• connecting A, B, and C to the multiplexer select inputs
• placing y and z on the two multiplexer outputs
• connecting their respective truth table values to the inputs
Chapter 1 241
0
0 D00 D10
1 D01 1 D11
1 D02 1 D12
D03 0 D13
0
0 D04 1 D14
Out Y Out Z
1 D05 0 D15
1 D06 0 D16
0 D07 1 D17
A S2 A S2
8-to-1 8-to-1
B S1 B S1
MUX MUX
S0 C S0
C
 Note that the multiplexer with fixed inputs is identical to a

ROM with 3-bit addresses and 2-bit data!
Chapter 1 242
- Multiplexer Approach 2
 Implement any m functions of n + 1 variables by using:

• An m-wide 2n-to-1-line multiplexer
• A single inverter
 Design:
• Find the truth table for the functions.
• Based on the values of the first n variables, separate the truth table
rows into pairs
• For each pair and output, define a rudimentary function of the final
variable (0, 1, X, ) X
• Using the first n variables as the index, value-fix the information
inputs to the multiplexer with the corresponding rudimentary
functions
• Use the inverter to generate the rudimentary function X
Chapter 1 243
Example: Gray to Binary Code
 Design a circuit to Gray Binary
convert a 3-bit Gray ABC xyz
0 0 0 0 0 0
code to a binary code 10 0 0 01
 The formulation gives 1 10 010
010 01 1
the truth table on the 01 1 10 0
right 1 1 1 101
 It is obvious from this 101
0 01
1 10
1 1 1
table that X = C and the
Y and Z are more complex
Chapter 1 244
 Rearrange the table so that the input combinations are in

counting order, pair rows, and find rudimentary functions
Gray Binary Rudimentary Rudimentary
AB C xyz Functions of C Functions of C
for y for z
000 000
F=C F=C
001 111
010 011
F=C F=C
011 100
100 001
F=C F=C
101 110
110 010
F=C F=C
111 101
Chapter 1 245
 Assign the variables and functions to the multiplexer inputs:

C C
D00 D10
C D01 C D11
C C
C D02 Out Y C D12 Out Z
C D03 C D13
8-to-1 8-to-1
A S1 A S1
B S0 MUX B S0 MUX
 Note that this approach (Approach 2) reduces the cost by almost
half compared to Approach 1.
 This result is no longer ROM-like
 Extending, a function of more than n variables is decomposed into
several sub-functions defined on a subset of the variables. The
multiplexer then selects among these sub-functions.
Chapter 1 246
Terms of Use
Education, Inc.
Chapter 1 247
Chapter 4 – Arithmetic Functions
Charles Kime & Mano

Overview
 Iterative combinational circuits

 Binary adders
• Half and full adders
• Ripple carry and carry lookahead adders
 Binary subtraction
 Binary adder-subtractors
• Signed binary numbers
• Signed binary addition and subtraction
• Overflow
 Binary multiplication
 Other arithmetic functions
• Design by contraction
Chapter 1 249
Iterative Combinational Circuits
 Arithmetic functions
• Operate on binary vectors
• Use the same subfunction in each bit position
 Can design functional block for subfunction and
repeat to obtain functional block for overall
function
 Cell - subfunction block
 Iterative array - a array of interconnected cells
 An iterative array can be in a single dimension
(1D) or multiple dimensions
Chapter 1 250
Block Diagram of a 1D Iterative Array
A n-1 B n-1 A1 B0
X n-1 X2 X1
Xn X0
Cell n-1 Y n-1 Y2 Cell 1 Y1 Cell 0
Yn Y0
C n-1 C1 C0
 Example: n = 32
• Number of inputs = ?
• Truth table rows = ?
• Equations with up to ? input variables
• Equations with huge number of terms
• Design impractical!
 Iterative array takes advantage of the regularity to make
design feasible
Chapter 1 251
Functional Blocks: Addition
 Binary addition used frequently

 Addition Development:
• Half-Adder (HA), a 2-input bit-wise addition
functional block,
• Full-Adder (FA), a 3-input bit-wise addition
functional block,
• Ripple Carry Adder, an iterative array to
perform binary addition, and
• Carry-Look-Ahead Adder (CLA), a hierarchical
structure to improve performance.
Chapter 1 252
Functional Block: Half-Adder
 A 2-input, 1-bit width binary adder that performs the

following computations:
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
 A half adder adds two bits to produce a two-bit sum
 The sum is expressed as a
X Y C S
sum bit , S and a carry bit, C
0 0 0 0
 The half adder can be specified as
a truth table for S and C  0 1 0 1
1 0 0 1
1 1 1 0
Chapter 1 253
Logic Simplification: Half-Adder
 The K-Map for S, C is: S C

Y Y
 This is a pretty trivial map!
By inspection: 0 1 1 0 1
X 1 2 3 X 2 1 3
S = X × Y + X × Y = X Å Y
S = ( X + Y )×( X + Y )
 and
C = X × Y
C = (( X×Y ) )
 These equations lead to several implementations.
Chapter 1 254
Five Implementations: Half-Adder
 We can derive following sets of equations for a half-adder:
(a) S = X × Y + X × Y ( d ) S = ( X + Y )× C
C = X × Y C = ( X + Y )
( b ) S = ( X + Y )×( X + Y ) (e) S = X Å Y
C = X × Y C = X × Y
( c ) S = ( C + X× Y)
 (a), C(b),
= and (e) are
X × Y
SOP, POS, and XOR implementations
for S.
 In (c), the C function is used as a term in the AND-NOR
implementation of S, and in (d), the function is used in a
POS term for S. C
Chapter 1 255
Implementations: Half-Adder
 The most common half

adder implementation is: X
S
(e)
Y
S = X Å Y C
C = X × Y
 A NAND only implementation is:

C
X
S = ( X + Y )× C
C = (( X×Y ) ) S
Chapter 1 256
Functional Block: Full-Adder
 A full adder is similar to a half adder, but includes a carry-

in bit from lower stages. Like the half-adder, it computes
a sum bit, S and a carry bit, C.
• For a carry-in (Z) of Z 0 0 0 0
0, it is the same as X 0 0 1 1
the half-adder: +Y +0 +1 +0 +1
CS 0 0 01 01 10
• For a carry- in
(Z) of 1: Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 1 1
Chapter 1 257
Logic Optimization: Full-Adder
 Full-Adder Truth Table: X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
 Full-Adder K-Map: 1
1
0
1
1
0
1
1
0
0
1 1 1 1 1
S Y C Y
1 1 1
0 1 3 2 0 1 3 2
X 1 1 X 1 1 1
4 5 7 6 4 5 7 6
Z Z
Chapter 1 258
Equations: Full-Adder
 From the K-Map, we get:

S = X Y Z + X Y Z + X Y Z + X Y Z
C = X Y + X Z + Y Z
 The S function is the three-bit XOR function (Odd
Function):
S = X Å Y Å Z
 The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or
if the sum is 1 and a carry-in (Z) occurs. Thus C can be
re-written as:
C = X Y + ( X Å Y ) Z
 The term X·Y is carry generate.
 The term XY is carry propagate.
Chapter 1 259
Implementation: Full Adder
 Full Adder Schematic Ai Bi

Gi
 Here X, Y, and Z, and C
(from the previous pages)
are A, B, Ci and Co,
respectively. Also,
Pi
G = generate and
Ci
P = propagate.
 Note: This is really a combination
of a 3-bit odd function (for S)) and
Carry logic (for Co): Ci+1
Si
(G = Generate) OR (P =Propagate AND Ci = Carry In)

Co = G + P · Ci
Chapter 1 260
Binary Adders
 To add multiple operands, we “bundle” logical signals

together into vectors and use functional blocks that operate
on the vectors
Description Subscript Name
 Example: 4-bit ripple carry 3210
adder: Adds input vectors Carry In 0110 Ci
A(3:0) and B(3:0) to get Augend 1011 Ai

a sum vector S(3:0) Addend 0011 Bi
 Note: carry out of cell i Sum 1110 Si
becomes carry in of cell 0011 Ci+1

Carry out
i+1
Chapter 1 261
4-bit Ripple-Carry Binary Adder
 A four-bit Ripple Carry Adder made from four 1-

bit Full Adders:
B3 A3 B2 A2 B1 A1 B0 A
C3 C2 C1
FA FA FA C0
C4 S3 S2 S1 S0
Chapter 1 262
Unsigned Subtraction
 Algorithm:
• Subtract the subtrahend N from the minuend M
• If no end borrow occurs, then M ³ N, and the result is a
non-negative number and correct.
• If an end borrow occurs, the N > M and the difference
M - N + 2n is subtracted from 2n, and a minus sign is
appended to the result.
 Examples: 0 1
1001 0100
- 0111 - 0111
0010 1101
10000
- 1101
Chapter 1 263
Unsigned Subtraction (continued)
 The subtraction, 2n - N, is taking the 2’s

complement of N
 To do both unsigned addition and unsigned
A B
subtraction requires:
 Quite complex!
Borrow
 Goal: Shared simpler Binary adder Binary subtractor
logic for both addition

and subtraction Selective
2's complementer
Complement
 Introduce complements
as an approach Subtract/Add
0
Quadruple 2-to-1
1
S
multiplexer
Result
Chapter 1 264
Complements
 Two complements:
• Diminished Radix Complement of N
 (r - 1)’s complement for radix r
 1’s complement for radix 2
 Defined as (rn - 1) - N
• Radix Complement
 r’s complement for radix r
 2’s complement in binary
 Defined as rn - N
 Subtraction is done by adding the complement of the
subtrahend
 If the result is negative, takes its 2’s complement
Chapter 1 265
Binary 1's Complement
 For r = 2, N = 011100112, n = 8 (8 digits):

(rn – 1) = 256 -1 = 25510 or 111111112
 The 1's complement of 011100112 is then:
11111111
– 01110011
10001100
 Since the 2n – 1 factor consists of all 1's and since
1 – 0 = 1 and 1 – 1 = 0, the one's complement is
obtained by complementing each individual bit
(bitwise NOT).
Chapter 1 266
Binary 2's Complement
 For r = 2, N = 011100112, n = 8 (8 digits),

we have:
(rn ) = 25610 or 1000000002
 The 2's complement of 01110011 is then:
100000000
– 01110011
10001101
 Note the result is the 1's complement plus 1,
a fact that can be used in designing
hardware
Chapter 1 267
Alternate 2’s Complement Method
 Given: an n-bit binary number, beginning at the least

significant bit and proceeding upward:
• Copy all least significant 0’s
• Copy the first 1
• Complement all bits thereafter.
 2’s Complement Example:
10010100
• Copy underlined bits:
100
• and complement bits to the left:
01101100
Chapter 1 268
Subtraction with 2’s Complement
 For n-digit, unsigned numbers M and N, find M 

N in base 2:
• Add the 2's complement of the subtrahend N to the
minuend M:
M + (2n  N) = M  N + 2n
• If M  N, the sum produces end carry rn which is
discarded; from above, M - N remains.
• If M < N, the sum does not produce an end carry and,
from above, is equal to 2n  ( N  M ), the 2's
complement of ( N  M ).
• To obtain the result  (N – M) , take the 2's
complement of the sum and place a  to its left.
Chapter 1 269
Unsigned 2’s Complement Subtraction Example 1
 Find 010101002 – 010000112
1
01010100 01010100
2’s comp
– 01000011 + 10111101
00010001
 The carry of 1 indicates that no correction
of the result is required.
Chapter 1 270
Unsigned 2’s Complement Subtraction Example 2
 Find 010000112 – 010101002

0
01000011 01000011
– 01010100 2’s comp+ 10101100
2’s comp
11101111
00010001
 The carry of 0 indicates that a correction of
the result is required.
 Result = – (00010001)
Chapter 1 271
Signed Integers
 Positive numbers and zero can be represented by unsigned

n-digit, radix r numbers. We need a representation for
negative numbers.
 To represent a sign (+ or –) we need exactly one more bit
of information (1 binary digit gives 21 = 2 elements which
is exactly what is needed).
 Since computers use binary numbers, by convention, the
most significant bit is interpreted as a sign bit:
s an–2  a2a1a0
where:
s = 0 for Positive numbers
s = 1 for Negative numbers
and ai = 0 or 1 represent the magnitude in some form.
Chapter 1 272
Signed Integer Representations
Signed-Magnitude – here the n – 1 digits are

interpreted as a positive magnitude.
Signed-Complement – here the digits are interpreted
as the rest of the complement of the number. There
are two possibilities here:
• Signed 1's Complement
 Uses 1's Complement Arithmetic
• Signed 2's Complement
 Uses 2's Complement Arithmetic
Chapter 1 273
Signed Integer Representation Example
 r =2, n=3
Number Sign - Mag. 1's Comp. 2's Comp.
+3 011 011 011
+2 010 010 010
+1 001 001 001
+0 000 000 000
– 0 100 111 —
– 1 101 110 111
– 2 110 101 110
– 3 111 100 101
– 4 — — 100
Chapter 1 274
Signed-Magnitude Arithmetic
 If the parity of the three signs is 0:

1. Add the magnitudes.
2. Check for overflow (a carry out of the MSB)
3. The sign of the result is the same as the sign of the
first operand.
 If the parity of the three signs is 1:
1. Subtract the second magnitude from the first.
2. If a borrow occurs:
• take the two’s complement of result
• and make the result sign the complement of the
sign of the first operand.
3. Overflow will never occur.
Chapter 1 275
Sign-Magnitude Arithmetic Examples
 Example 1: 0010
+ 0101
 Example 2: 0010
+ 1101
 Example 3: 1010
- 0101
Chapter 1 276
Signed-Complement Arithmetic
 Addition:
1. Add the numbers including the sign bits,
discarding a carry out of the sign bits (2's
Complement), or using an end-around carry (1's
Complement).
2. If the sign bits were the same for both numbers
and the sign of the result is different, an overflow has
occurred.
3. The sign of the result is computed in step 1.
 Subtraction:
Form the complement of the number you are
subtracting and follow the rules for addition.
Chapter 1 277
Signed 2’s Complement Examples
 Example 1: 1101
+ 0011
 Example 2: 1101
- 0011
Chapter 1 278
2’s Complement Adder/Subtractor
 Subtraction can be done by addition of the 2's Complement.

1. Complement each bit (1's Complement.)
2. Add 1 to the result.
 The circuit shown computes A + B and A – B:
 For S = 1, subtract,
the 2’s complement B A
3 B A
3 B 2 A B A
2 1 1 0 0
of B is formed by using S
XORs to form the 1’s

comp and adding the 1
applied to C0.
C3 C2 C1 C0
 For S = 0, add, B is FA FA FA FA
passed through
unchanged C4 S3 S2 S1 S0
Chapter 1 279
Overflow Detection
 Overflow occurs if n + 1 bits are required to contain the

result from an n-bit addition or subtraction
 Overflow can occur for:
• Addition of two operands with the same sign
• Subtraction of operands with different signs
 Signed number overflow cases with correct result sign
0 0 1 1
+0 - 1 - 0 +1
0 0 1 1
 Detection can be performed by examining the result signs
which should match the signs of the top operand
Chapter 1 280
Overflow Detection
 Signed number cases with carries Cn and Cn-1 shown for correct result
signs:
0 00 01 11 1
0 0 1 1
+ 0 - 1 - 0 +1
0 0 1 1
 Signed number cases with carries shown for erroneous result signs
(indicating overflow):
0 10 11 01 0
0 0 1 1
+ 0 - 1 -0 + 1
1 1 0 0
 Simplest way to implement overflow V = Cn + Cn - 1
 This works correctly only if 1’s complement and the addition of the
carry in of 1 is used to implement the complementation! Otherwise
fails for - 10 ... 0
Chapter 1 281
Other Arithmetic Functions
 Convenient to design the functional blocks

by contraction - removal of redundancy
from circuit to which input fixing has been
applied
 Functions
• Incrementing
• Decrementing
• Multiplication by Constant
• Division by Constant
• Zero Fill and Extension
Chapter 1 282
Design by Contraction
 Contraction is a technique for simplifying

the logic in a functional block to implement
a different function
• The new function must be realizable from the
original function by applying rudimentary
functions to its inputs
• Contraction is treated here only for application
of 0s and 1s (not for X and X)
• After application of 0s and 1s, equations or the
logic diagram are simplified by using rules
given on pages 224 - 225 of the text.
Chapter 1 283
Design by Contraction Example
 Contraction of a ripple carry adder to incrementer for n = 3

• Set B = 001
A2 A1 A0
X 0 0 1
0 4 1
X 5
2
C3 5 X C1 3
C0 5 0
S2 S1
A2 A1 A0
S2 S1 S0
(b)
• The middle cell can be repeated to make an incrementer with n > 3.

Chapter 1 284
Incrementing & Decrementing
 Incrementing
• Adding a fixed value to an arithmetic variable
• Fixed value is often 1, called counting (up)
• Examples: A + 1, B + 4
• Functional block is called incrementer
 Decrementing
• Subtracting a fixed value from an arithmetic variable
• Fixed value is often 1, called counting (down)
• Examples: A - 1, B - 4
• Functional block is called decrementer
Chapter 1 285
Multiplication/Division by 2n
 (a) Multiplication B3 B2 B1 B0
by 100
• Shift left by 2 C5 C4 C3 C2
0
C1
0
C0
 (b) Division (a)
by 100 B3 B2 B1 B0
• Shift right by 2
• Remainder 0 0
preserved
C3 C2 C1 C0 C 21 C 22
(b)
Chapter 1 286
Multiplication by a Constant
 Multiplication of B(3:0) by 101

 See text Figure 513 (a) for contraction
B 3 B 2 B 1 B 0 0 0 B 3 B 2 B 1 B 0
4-bit Adder
Carry
output Sum
C 6 C 5 C 4 C 3 C 2 C 1 C 0
Chapter 1 287
Zero Fill
 Zero fill - filling an m-bit operand with 0s to

become an n-bit operand with n > m
 Filling usually is applied to the MSB end of
the operand, but can also be done on the
LSB end
 Example: 11110101 filled to 16 bits
• MSB end: 0000000011110101
• LSB end: 1111010100000000
Chapter 1 288
Extension
 Extension - increase in the number of bits at the

MSB end of an operand by using a complement
representation
• Copies the MSB of the operand into the new positions
• Positive operand example - 01110101 extended to 16
bits:
0000000001110101
• Negative operand example - 11110101 extended to 16
bits:
1111111111110101
Chapter 1 289
Terms of Use
Education, Inc.
Chapter 1 290
Chapter 5 – Sequential Circuits
Part 1 – Storage Elements and Sequential Circuit Analysis
Charles Kime & Mano

Overview
 Part 1 - Storage Elements and Analysis

• Introduction to sequential circuits
• Types of sequential circuits
• Storage elements
 Latches
 Flip-flops
• Sequential circuit analysis
 State tables
 State diagrams
 Equivalent states
 Moore and Mealy Models
 Part 2 - Sequential Circuit Design
 Part 3 – State Machine Design
Chapter 1 292
Introduction to Sequential Circuits
Inputs Outputs
Combina-tional
 A Sequential
Logic
circuit contains:
Storage
• Storage elements: Elements
Latches or Flip-Flops Next
• Combinational Logic: State State
 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are signals
from storage elements.
 The remaining outputs, Next State are inputs
to storage elements.
Chapter 1 293
Introduction to Sequential Circuits
Inputs Outputs
Combina-tional
Logic
Storage
Elements
 Combinatorial Logic Next
• Next state function State State
Next State = f(Inputs, State)
• Output function (Mealy)
Outputs = g(Inputs, State)
• Output function (Moore)
Outputs = h(State)
 Output function type depends on specification and affects the
design significantly
Chapter 1 294
Types of Sequential Circuits
 Depends on the times at which:

• storage elements observe their inputs, and
• storage elements change their state
 Synchronous
• Behavior defined from knowledge of its signals at discrete
instances of time
• Storage elements observe inputs and can change state only in
relation to a timing signal (clock pulses from a clock)
 Asynchronous
• Behavior defined from knowledge of inputs an any instant of time
and the order in continuous time in which inputs change
• If clock just regarded as another input, all circuits are
asynchronous!
• Nevertheless, the synchronous abstraction makes complex designs
tractable!
Chapter 1 295
Discrete Event Simulation
 In order to understand the time behavior of a

sequential circuit we use discrete event simulation.
 Rules:
• Gates modeled by an ideal (instantaneous) function and
a fixed gate delay
• Any change in input values is evaluated to see if it
causes a change in output value
• Changes in output values are scheduled for the fixed
gate delay after the input change
• At the time for a scheduled output change, the output
value is changed along with any inputs it drives
Chapter 1 296
Simulated NAND Gate
 Example: A 2-Input NAND gate with a 0.5 ns. delay:

F(Instantaneous)
A
DELAY 0.5 ns. F
 Assume A and B have been 1 for a long time

 At time t=0, A changes to a 0 at t= 0.8 ns, back to 1.
t (ns) A B F(I) F Comment
–  1 1 0 0 A=B=1 for a long time
0 1 Þ 0 1 1 Ü 0 0 F(I) changes to 1
0.5 0 1 1 1 Ü 0 F changes to 1 after a 0.5 ns delay
0.8 1 Ü 0 1 1 Þ 0 1 F(Instantaneous) changes to 0
0.13 1 1 0 1 Þ 0 F changes to 0 after a 0.5 ns delay
Chapter 1 297
Gate Delay Models
 Suppose gates with delay n ns are

represented for n = 0.2 ns, n = 0.4 ns,
n = 0.5 ns, respectively:
0.2 0.4 0.5
Chapter 1 298
Circuit Delay Model
 Consider a simple A
2-input multiplexer: 0.4
 With function: 0.2
Y
• Y = A for S = 1 0.5
• Y = B for S = 0 S
B 0.4
A
B
S
Y
 “Glitch” is due to delay of inverter
Chapter 1 299
Storing State
 What if A con-
nected to Y? 0.4
 Circuit becomes: 0.2
• Y = B for S = 1, and S Y
Y(t) dependent on
0.4
Y(t – 0.9) for S = 0 B
B
S
 YThe simple combinational circuit has now become a sequential

circuit because its output is a function of a time sequence of input
signals!
Y is stored value in shaded area
Chapter 1 300
Storing State (Continued)
 Simulation example as input signals change with time.

Changes occur every 100 ns, so that the tenths of ns delays
are negligible.
Time B S Y Comment
1 0 0 Y “remembers” 0
1 1 1 Y = B when S = 1
1 0 1 Now Y “remembers” B = 1 for S = 0
0 0 1 No change in Y when B changes

0 1 0 Y = B when S = 1
0 0 0 Y “remembers” B = 0 for S = 0
1 0 0 No change in Y when B changes
 Y represent the state of the circuit, not just an output.
Chapter 1 301
Storing State (Continued)
 Suppose we place
an inverter in the
“feedback path.” 0.4
0.2
0.2
0.5
S Y
B 0.4
 The following behavior results:
 The circuit is said B S Y Comment
to be unstable. 0 1 0 Y = B when S = 1
 For S = 0, the 1 1 1
circuit has become 1 0 1 Now Y “remembers” A
what is called an 1 0 0 Y, 1.1 ns later
oscillator. Can be 1 0 1 Y, 1.1 ns later

Y, 1.1 ns later
used as crude clock. 1 0 0
Chapter 1 302
Basic (NAND) S – R Latch
 “Cross-Coupling” S (set)
Q
two NAND gates gives
the S -R Latch:
 Which has the time Q
R (reset)
sequence behavior:
Time R S Q Q Comment
1 1 ? ? Stored state unknown
1 0 1 0 “Set” Q to 1
 S = 0, R = 0 is 1 1 1 0 Now Q “remembers” 1
0 1 0 1 “Reset” Q to 0
forbidden as 1 1 0 1 Now Q “remembers” 0
input pattern 0 0 1 1 Both go high
1 1 ? ? Unstable!
Chapter 1 303
Basic (NOR) S – R Latch
 Cross-coupling two R (reset)

Q
NOR gates gives the
S – R Latch:
 Which has the time S (set) Q
sequence
behavior:
Time R S Q Q Comment
0 0 ? ? Stored state unknown
0 1 1 0 “Set” Q to 1
0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low
0 0 ? ? Unstable!
Chapter 1 304
Clocked S - R Latch
 Adding two NAND S

gates to the basic Q
S - R NAND latch
C
gives the clocked
S – R latch: Q
R
 Has a time sequence behavior similar to the basic S-R

latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
Chapter 1 305
Clocked S - R Latch (continued)
 The Clocked S-R Latch can be described by a table:

Q(t) S R Q(t+1) Comment
S
Q 0 0 0 0 No change
C 0 0 1 0 Clear Q
0 1 0 1 Set Q
Q
R 0 1 1 ??? Indeterminate
1 0 0 1 No change
 The table describes
1 0 1 0 Clear Q
what happens after the 1 1 0 1 Set Q
clock [at time (t+1)] 1 1 1 ??? Indeterminate
based on:
• current inputs (S,R) and
• current state Q(t).
Chapter 1 306
D Latch
 Adding an inverter D
to the S-R Latch, Q
gives the D Latch: C
 Note that there are Q
no “indeterminate”
states! The graphic symbol for a
Q D Q(t+1) Comment
D Latch is:
0 0 0 No change D Q
0 1 1 Set Q
1 0 0 Clear Q
C Q
1 1 1 No Change
Chapter 1 307
Flip-Flops
 The latch timing problem

 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops
Chapter 1 308
The Latch Timing Problem
 In a sequential circuit, paths may exist through

combinational logic:
• From one storage element to another
• From a storage element back to the same storage
element
 The combinational logic between a latch output
and a latch input may be as simple as an
interconnect
 For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has value
1
Chapter 1 309
The Latch Timing Problem (continued)
 Consider the following circuit:
D Q Y
Clock Q
 Suppose that initially Y = 0. C
Clock
Y
 As long as C = 1, the value of Y continues to change!
 The changes are based on the delay present on the loop
through the connection from Y back to Y.
 This behavior is clearly unacceptable.
 Desired behavior: Y changes only once per clock pulse
Chapter 1 310
The Latch Timing Problem (continued)
 A solution to the latch timing problem is to

break the closed path from Y to Y within the
storage element
 The commonly-used, path-breaking
solutions replace the clocked D-latch with:
• a master-slave flip-flop
• an edge-triggered flip-flop
Chapter 1 311
S-R Master-Slave Flip-Flop
 Consists of two clocked S

S S
S-R latches in series
Q Q Q
C C C
with the clock on the
R R
second latch inverted Q R Q Q
 The input is observed

by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the difference
in clocking values (C = 1 and C = 0).
 The behavior demonstrated by the example with D driven
by Y given previously is prevented since the clock must
change from 1 to 0 before a change in Y based on D can
occur.
Chapter 1 312
Flip-Flop Problem
 The change in the flip-flop output is delayed by the

pulse width which makes the circuit slower or
 S and/or R are permitted to change while C = 1
• Suppose Q = 0 and S goes to 1 and then back to 0 with R
remaining at 0
 The master latch sets to 1
 A 1 is transferred to the slave
• Suppose Q = 0 and S goes to 1 and back to 0 and R goes
to 1 and back to 0
 The master latch sets and then resets
 A 0 is transferred to the slave
• This behavior is called 1s catching
Chapter 1 313
Flip-Flop Solution
 Use edge-triggering instead of master-slave

 An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
 Edge-triggered flip-flops can be built directly at
the electronic circuit level, or
 A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.
Chapter 1 314
Edge-Triggered D Flip-Flop
 The edge-triggered
D D S
D flip-flop is the Q Q Q
same as the master- C
C C
slave D flip-flop Q R Q Q
 It can be formed by:

• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be avoided
since the 1s-catching behavior is not present with D
replacing S and R inputs
 The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
Chapter 1 315
Positive-Edge Triggered D Flip-Flop
 Formed by D D Q S
adding inverter
Q Q
to clock input C C
Q R Q Q
 Q changes to the value on D applied at the positive

clock edge within timing constraints to be
specified
 Our choice as the standard flip-flop for most
sequential circuits
Chapter 1 316
Standard Symbols for Storage
Elements
S S D D
R R C C
SR SR D with 1 Control D with 0 Control
 Master-Slave: (a) Latches
Postponed output S S D D
indicators C C
R R C C
Triggered SR Triggered SR Triggered D Triggered D
 Edge-Triggered: (b) Master-Slave Flip-Flops
Dynamic
indicator
D D
C C
Triggered D Triggered D
(c) Edge-Triggered Flip-Flops

Chapter 1 317
Direct Inputs
 At power up or at reset, all or part

of a sequential circuit usually is S
initialized to a known state before D Q
it begins operation
 This initialization is often done C Q
outside of the clocked behavior R
of the circuit, i.e., asynchronously.

 Direct R and/or S inputs that control the state of the latches
within the flip-flops are used for this initialization.
 For the example flip-flop shown
• 0 applied to R resets the flip-flop to the 0 state
• 0 applied to S sets the flip-flop to the 1 state
Chapter 1 318
Sequential Circuit Analysis
 General Model
• Current State Inputs
Combina-tional
Outputs
at time (t) is Logic

stored in an Storage
array of Elements
flip-flops. Next
State
• Next State at time (t+1) State
is a Boolean function of CLK
State and Inputs.

• Outputs at time (t) are a Boolean function of
State (t) and (sometimes) Inputs (t).
Chapter 1 319
Example 1 (from Fig. 5-15)
 Input: x(t)
x
 Output: y(t) D Q A
A

C Q
State: (A(t), B(t))

 What is the Output
Function? D Q B
CP C Q
 What is the Next State y
Function?
Chapter 1 320
Example 1 (from Fig. 5-15) (continued)
 Boolean equations
for the functions: x
• A(t+1) = A(t)x(t) D Q A
+ B(t)x(t) C Q A
Next State
• B(t+1) = A(t)x(t)
• y(t) = x(t)(B(t) + A(t)) D Q B
CP C Q'
Output
Chapter 1 321
Example 1(from Fig. 5-15) (continued)
 Where in time are inputs, outputs and states
defined?
0 0
0
1
Chapter 1 322
State Table Characteristics
 State table – a multiple variable table with the

following four sections:
• Present State – the values of the state variables for each
allowed state.
• Input – the input combinations allowed.
• Next-state – the value of the state at time (t+1) based on
the present state and the input.
• Output – the value of the output as a function of the
present state and (sometimes) the input.
 From the viewpoint of a truth table:
• the inputs are Input, Present State
• and the outputs are Output, Next State
Chapter 1 323
Example 1: State Table (from Fig. 5-15)
 The state table can be filled in using the next state and
output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A
(t)x(t) y(t) =x (t)
(B(t) + A(t))
Present State Input Next State Output

A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Chapter 1 324
Example 1: Alternate State Table
 2-dimensional table that matches well to a K-map. Present

state rows and input columns in Gray code order.
• A(t+1) = A(t)x(t) + B(t)x(t)
• B(t+1) =A (t)x(t)
• y(t) =x (t)(B(t) + A(t))
Present Next State Output
State x(t)=0 x(t)=1 x(t)=0 x(t)=1
A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
Chapter 1 325
State Diagrams
 The sequential circuit function can be represented

in graphical form as a state diagram with the
following components:
• A circle with the state name in it for each state
• A directed arc from the Present State to the Next State
for each state transition
• A label on each directed arc with the Input values
which causes the state transition, and
• A label:
 On each circle with the output value produced, or
 On each directed arc with the output value
produced.
Chapter 1 326
State Diagrams
 Label form:
• On circle with output included:
 state/output
 Moore type output depends only on state
• On directed arc with the output included:
 input/output
 Mealy type output depends on state and
input
Chapter 1 327
Example 1: State Diagram
x=0/y=0 x=0/y=1
 Which type? x=1/y=0
 Diagram gets AB
00 10
confusing for
x=0/y=1
large circuits x=1/y=0
 For small circuits, x=0/y=1

x=1/y=0
usually easier to
understand than 01 11
the state table x=1/y=0
Chapter 1 328
Equivalent State Definitions
 Two states are equivalent if their response

for each possible input sequence is an
identical output sequence.
 Alternatively, two states are equivalent if
their outputs produced for each input
symbol is identical and their next states for
each input symbol are the same or
equivalent.
Chapter 1 329
Equivalent State Example
 Text Figure 5-17(a): 0

1
 For states S3 and S2, S0/0

S1
• the output for input 0/1
0 is 1 and input 1 is 0, 0/1 0/1 1/0

and
• the next state for input 1/0
0 is S0 and for input S2 S3
1 is S2. 1/0
• By the alternative definition, states S3 and S2

are equivalent.
Chapter 1 330
Equivalent State Example
 Replacing S3 and S2 0/0

1/0
by a single state gives

state diagram: S0
0/1
S1
 Examining the new diagram,

states S1 and S2 are equivalent since 0/1 1/0
• their outputs for input
0 is 1 and input 1 is 0,
and
• their next state for input
S2
0 is S0 and for input 1/0

1 is S2,
 Replacing S1 and S2 by a 0/0
1/0
single state gives state

diagram: S0
0/1
S1
1/0
Chapter 1 331
Moore and Mealy Models
 Sequential Circuits or Sequential Machines

are also called Finite State Machines
(FSMs). Two formal models exist:
 Moore Model  Mealy Model
Named after E.F. Moore Named after G. Mealy

Outputs are a function ONLY of states Outputs are a function of inputs AND
Usually specified on the states. states
Usually specified on the state transition
arcs.
Chapter 1 332
Moore and Mealy Example Diagrams
 Mealy Model State Diagram

maps inputs and state to outputs x=1/y=0
x=0/y=0
0 1
 Moore Model State Diagram x=0/y=0 x=1/y=1

x=0
maps states to outputs
0/0
x=0
x=1
x=1
x=0
2/1
1/0
x=1
Chapter 1 333
Moore and Mealy Example Tables
 Moore Model state table maps state to

outputs Present Next State Output
State x=0 x=1
0 0 1 0
1 0 2 0
2 0 2 1
 Mealy Model state table maps inputs and

state to outputs Present Next State Output
State x=0 x=1 x=0 x=1
0 0 1 0 0
1 0 1 0 1
Chapter 1 334
Mixed Moore and Mealy Outputs
 In real designs, some outputs may be Moore type

and other outputs may be Mealy type.
 Example: Figure 5-17(a) can be modified to
illustrate this 0
1
• State 00: Moore
• States 01, 10, 00/0
0/1
01
and 11: Mealy

 Simplifies output 0/1
0/1 1/0
specification
1/0
10 11
1/0
Chapter 1 335
Example 2: Sequential Circuit Analysis
 Logic Diagram: D Q
A
Z
C R Q
D
B
Q
C R Q
D
C
Q
Clock C R Q
Reset
Chapter 1 336
Example 2: Flip-Flop Input Equations
 Variables
• Inputs: None
• Outputs: Z
• State Variables: A, B, C
 Initialization: Reset to (0,0,0)
 Equations
• A(t+1) = Z=
• B(t+1) =
• C(t+1) =
Chapter 1 337
Example 2: State Table
X’ = X(t+1)
ABC A’B’C’ Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Chapter 1 338
Example 2: State Diagram
ABC
Reset 000
111 100 001
011 010 101
 Which states are used?

 What is the function of 110
the circuit?
Chapter 1 339
Terms of Use
Education, Inc.
Chapter 1 340
Part 2 – Sequential Circuit Design
Charles Kime & Mano

Overview
 Part 1 - Storage Elements and Sequential

Circuit Analysis
 Part 2- Sequential Circuit Design
 Specification
 Formulation
 State Assignment
 Flip-Flop Input and Output Equation Determination
 Verification
Chapter 1 342
The Design Procedure
 Specification
 Formulation - Obtain a state diagram or state table
 State Assignment - Assign binary codes to the states
 Flip-Flop Input Equation Determination - Select flip-flop
types and derive flip-flop equations from next state entries in the table
 Output Equation Determination - Derive output equations from
output entries in the table
 Optimization - Optimize the equations
 Technology Mapping - Find circuit from equations and map to
flip-flops and gate technology
 Verification - Verify correctness of final design
Chapter 1 343
Specification
 Component Forms of Specification

• Written description
• Mathematical description
• Hardware description language*
• Tabular description*
• Equation description*
• Diagram describing operation (not just structure)*
 Relation to Formulation
• If a specification is rigorous at the binary level (marked
with * above), then all or part of formulation may be
completed
Chapter 1 344
Formulation: Finding a State Diagram
 A state is an abstraction of the history of the past applied

inputs to the circuit (including power-up reset or system
reset).
• The interpretation of “past inputs” is tied to the synchronous
operation of the circuit. E. g., an input value (other than an
asynchronous reset) is measured only during the setup-hold time
interval for an edge-triggered flip-flop.
 Examples:
• State A represents the fact that a 1 input has occurred among the
past inputs.
• State B represents the fact that a 0 followed by a 1 have occurred
as the most recent past two inputs.
Chapter 1 345
Formulation: Finding a State Diagram
 In specifying a circuit, we use states to remember

meaningful properties of past input sequences that are
essential to predicting future output values.
 A sequence recognizer is a sequential circuit that produces
a distinct output value whenever a prescribed pattern of
input symbols occur in sequence, i.e, recognizes an input
sequence occurence.
 We will develop a procedure specific to sequence
recognizers to convert a problem statement into a state
diagram.
 Next, the state diagram, will be converted to a state table
from which the circuit will be designed.
Chapter 1 346
Sequence Recognizer Procedure
 To develop a sequence recognizer state diagram:
•Begin in an initial state in which NONE of the initial portion of the
sequence has occurred (typically “reset” state).
• Add a state that recognizes that the first symbol has occurred.
• Add states that recognize each successive symbol occurring.
• The final state represents the input sequence (possibly less the
final input value) occurence.
• Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred.
• Add other arcs on non-sequence inputs which transition to states
that represent the input subsequence that has occurred.
 The last step is required because the circuit must recognize the input
sequence regardless of where it occurs within the overall sequence
applied since “reset.”.
Chapter 1 347
State Assignment
 Each of the m states must be assigned a

unique code
 Minimum number of bits required is n such
that
n ≥ log2 m
where x is the smallest integer ≥ x
 There are useful state assignments that use
more than the minimum number of bits
 There are 2n - m unused states
Chapter 1 348
Sequence Recognizer Example
 Example: Recognize the sequence 1101

• Note that the sequence 1111101 contains 1101 and "11" is a proper
sub-sequence of the sequence.
 Thus, the sequential machine must remember that the first
two one's have occurred as it receives another symbol.
 Also, the sequence 1101101 contains 1101 as both an
initial subsequence and a final subsequence with some
overlap, i. e., 1101101 or 1101101.
 And, the 1 in the middle, 1101101, is in both
subsequences.
 The sequence 1101 must be recognized each time it occurs
in the input sequence.
Chapter 1 349
Example: Recognize 1101
 Define states for the sequence to be recognized:

• assuming it starts with first symbol,
• continues through each symbol in the sequence to be recognized,
and
• uses output 1 to mean the full sequence has occurred,
• with output 0 otherwise.
 Starting in the initial state (Arbitrarily named "A"):
• Add a state that recognizes
the first "1." 1/0
• State "A" is the initial state, and state "B" isA the state which
B
represents the fact that the "first" one in the input subsequence has
occurred. The output symbol "0" means that the full recognized
sequence has not yet occurred.
Chapter 1 350
Example: Recognize 1101 (continued)
 After one more 1, we have:

• C is the state obtained
when the input sequence 1/0 1/0
has two "1"s. A B C
 Finally, after 110 and a 1, we have:
1/0 1/0 0/0 1/1

A B C D
• Transition arcs are used to denote the output function (Mealy Model)
• Output 1 on the arc from D means the sequence has been recognized
• To what state should the arc from state D go? Remember: 1101101 ?
• Note that D is the last state but the output 1 occurs for the input applied in
D. This is the case when a Mealy model is assumed.
Chapter 1 351
1/0 1/0 0/0 1/1

A B C D
 Clearly the final 1 in the recognized sequence

1101 is a sub-sequence of 1101. It follows a 0
which is not a sub-sequence of 1101. Thus it
should represent the same state reached from the
initial state after a first 1 is observed. We obtain:
1/0 1/0 0/0

A B C D
1/1
Chapter 1 352
1/0 1/0 0/0

A B C D
1/1
 The state have the following abstract meanings:
• A: No proper sub-sequence of the sequence has
occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that the last 1 has
occurred and thus, the sequence is recognized.
Chapter 1 353
 The other arcs are added to each state for inputs

not yet listed. Which arcs are missing?
1/0 1/0 0/0

A B C D
 Answer:
1/1
"0" arc from A
"0" arc from B
"1" arc from C
"0" arc from D.
Chapter 1 354
 State transition arcs must represent the fact that an

input subsequence has occurred. Thus we get:
0/0 1/0
1/0 1/0 0/0

A B C D
0/0
1/1
 Note that the 1 arc from state0/0C to state C implies

that State C means two or more 1's have occurred.
Chapter 1 355
Formulation: Find State Table
 From the State Diagram, we can fill in the State Table.

 There are 4 states, one 0/0
0/0 1/0
input, and one output.
We will choose the form A
1/0
B
1/0
C
0/0
D
with four rows, one for
each current state. 0/0
1/1
 From State A, the 0 and 0/0 1

input transitions have been
filled in along with Present Next State
the Output
outputs. A 0 0
A B
B
Chapter 1 356
Formulation: Find State Table
 From the state diagram, we complete the

state table. 0/0 1/0
1/0 1/0 0/0

A B C D
0/0
1/1
0/0
A A B 0 0
B A C 0 0
C D C 0 0
 What
D
wouldA
the
B
state diagram
0 1
and state table look
like for the Moore model?
Chapter 1 357
Example: Moore Model for Sequence 1101
 For the Moore Model, outputs are associated with

states.
 We need to add a state "E" with output value 1 for
the final 1 in the recognized input sequence.
• This new state E, though similar to B, would generate an
output of 1 and thus be different from B.
 The Moore model for a sequence recognizer usually
has more states than the Mealy model.
Chapter 1 358
Example: Moore Model (continued)
 We mark outputs on 0 1 states
for Moore model 0

1 1
 Arcs now show only A/0 B/0 C/0 D/0
state transitions
0 1
 Add a new state E to 1
produce the output 1 0

E/1
 Note that the new state, E

produces the same behavior 0 in
the future as state B. But it gives a different output at the
present time. Thus these states do represent a different
abstraction of the input history.
Chapter 1 359
Example: Moore Model (continued)
 The state table is shown 0 1
below 1 1
0
A/0 B/0 C/0 D/0
 Memory aid re more

state in the Moore model: 0 1
1
“Moore is More.” 0 E/1
State x=0 x=1 y
A A B 0
B A C 0
C D C 0
D A E 0
E A C 1
Chapter 1 360
State Assignment – Example 1
A A B 0 0
B A B 0 1
 How may assignments of codes with a

minimum number of bits?
• Two – A = 0, B = 1 or A = 1, B = 0
 Does it make a difference?
• Only in variable inversion, so small, if any.
Chapter 1 361
State Assignment – Example 2
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
 How may assignments of codes with a minimum

number of bits?
• 4  3  2  1 = 24
 Does code assignment make a difference in cost?
Chapter 1 362
State Assignment – Example 2 (continued)
 Counting Order Assignment: A = 0 0, B = 0 1, C =

1 0, D = 1 1
 The resulting coded state table:
State x = 0 x = 1 x = 0 x = 1
00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
Chapter 1 363
 Gray Code Assignment: A = 0 0, B = 0 1, C = 1 1,

D=10
 The resulting coded state table:
State x = 0 x = 1 x = 0 x = 1
00 00 01 0 0
01 00 11 0 0
11 10 11 0 0
10 00 01 0 1
Chapter 1 364
Find Flip-Flop Input and Output Equations:
Example 2 – Counting Order Assignment
 Assume D flip-flops
 Interchange the bottom two rows of the state table, to obtain K-maps for D1, D2,
and Z:
D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 0 0 0
Y2 Y2 Y2
0 0 0 1 0 0
Y1 Y1 Y1
1 1 1 0 0 1
Chapter 1 365
Optimization: Example 2: Counting Order
Assignment
 Performing two-level optimization:

D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 0 0 0
Y2 Y2 Y2
0 0 0 1 0 0
Y1 Y1 Y1
1 1 1 0 0 1
D1 = Y1Y2 + XY1Y2
D2 = XY1Y2 + XY1Y2 + XY1Y2
Z = XY1Y2 Gate Input Cost = 22
Chapter 1 366
Find Flip-Flop Input and Output Equations:
Example 2 – Gray Code Assignment
 Assume D flip-flops
 Obtain K-maps for D1, D2, and Z:
D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 1 0 0
Y2 Y2 Y2
1 1 0 1 0 0
Y1 Y1 Y1
0 0 0 1 0 1
Chapter 1 367
Optimization: Example 2: Assignment 2
 Performing two-level optimization:

D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 1 0 0
Y2 Y2 Y2
1 1 0 1 0 0
Y1 Y1 Y1
0 0 0 1 0 1
D1 = Y1Y2 + XY2 Gate Input Cost = 9
D2 = X Select this state assignment to
Z = XY1Y2 complete design in slide
Chapter 1 368
One Flip-flop per State (One-Hot) Assignment
 Example codes for four states: (Y3, Y2, Y1, Y0) =

0001, 0010, 0100, and 1000.
 In equations, need to include only the variable that
is 1 for the state, e. g., state with code 0001, is
represented in equations by Y0 instead of
Y3 Y2 Y1 Y0 because all codes with 0 or two or
more 1s have don’t care next state values.
 Provides simplified analysis and design
 Combinational logic may be simpler, but flip-flop
cost higher – may or may not be lower cost
Chapter 1 369
 One-Hot Assignment : A = 0001, B = 0010, C =

0100, D = 1000 The resulting coded state table:
State x = 0 x = 1 x=0x=1
0001 0001 0010 0 0
0010 0001 0100 0 0
0100 1000 0100 0 0
1000 0001 0010 0 1
Chapter 1 370
Optimization: Example 2: One Hot Assignment
 Equations read from 1 next state variable

entries in table:
D0 = X(Y0+ Y1 + Y3) or X Y2
D1 = X(Y0+ Y3)
D2 = X(Y1+ Y2) or X(Y0+ Y3 )
D3 = X Y 2
Z = XY3 Gate Input Cost = 15
 Combinational cost intermediate plus cost of
two more flip-flops needed.
Chapter 1 371
Map Technology
 Library:  Initial Circuit:

• D Flip-flops
with Reset
(not inverted) D
Y1
• NAND gates
with up to 4 C
R
inputs and
Z
inverters
Y2
X D
Clock C
R
Reset
Chapter 1 372
Mapped Circuit - Final Result
Y1
D
C
R
Y2
X D
Clock C
R
Reset
Chapter 1 373
Sequential Design: Example 3
 Design a sequential modulo 3 accumulator for 2-bit

operands
 Definitions:
• Modulo n adder - an adder that gives the result of the
addition as the remainder of the sum divided by n
 Example: 2 + 2 modulo 3 = remainder of 4/3 = 1
• Accumulator - a circuit that “accumulates” the sum of its
input operands over time - it adds each input operand to
the stored sum, which is initially 0.
 Stored sum: (Y1,Y0), Input: (X1,X0), Output: (Z1,Z0)
Chapter 1 374
Example 3 (continued)
 Complete the state diagram:
00
Reset A/00
01
C/10 B/01
Chapter 1 375
 Complete the state table

X1X0 00 01 11 10 Z1Z0
Y1Y0
Y1(t+1), Y1(t+1), Y1(t+1), Y1(t+1),
Y0(t+1) Y0(t+1) Y0(t+1) Y0(t+1)
A (00) 00 X 00
B (01) X 01
- (11) X X X X 11
C (10) X 10
 State Assignment: (Y1,Y0) = (Z1,Z0)
 Codes are in gray code order to ease use of K-maps in the next step
Chapter 1 376
 Find optimized flip-flop input equations for D flip-flops

D1 X1 D0 X1
X X
X X
Y0 Y0
X X X X X X X X
Y1 Y1
X X
X0 X0
 D1 =
 D0 =
Chapter 1 377
Circuit - Final Result with AND, OR, NOT
X1
Y1
D Z1
X0
C
R
Y0
D Z0
C
R
Reset
Clock
Chapter 1 378
Other Flip-Flop Types
 J-K and T flip-flops

• Behavior
• Implementation
 Basic descriptors for understanding and using
different flip-flop types
• Characteristic tables
• Characteristic equations
• Excitation tables
 For actual use, see Reading Supplement - Design
and Analysis Using J-K and T Flip-Flops
Chapter 1 379
J-K Flip-flop
 Behavior
• Same as S-R flip-flop with J analogous to S and K
analogous to R
• Except that J = K = 1 is allowed, and
• For J = K = 1, the flip-flop changes to the opposite
state
• As a master-slave, has same “1s catching” behavior as
S-R flip-flop
• If the master changes to the wrong state, that state will
be passed to the slave
 E.g., if master falsely set by J = 1, K = 1 cannot reset it during
the current clock cycle
Chapter 1 380
J-K Flip-flop (continued)
 Implementation  Symbol
• To avoid 1s catching
behavior, one solution
used is to use an
J
edge-triggered D as
the core of the flip-flop
C
J D
K
C
Chapter 1 381
T Flip-flop
 Behavior
• Has a single input T
 For T = 0, no change to state
 For T = 1, changes to opposite state
 Same as a J-K flip-flop with J = K = T
 As a master-slave, has same “1s catching”
behavior as J-K flip-flop
 Cannot be initialized to a known state using the T
input
• Reset (asynchronous or synchronous) essential
Chapter 1 382
T Flip-flop (continued)
 Implementation  Symbol
• To avoid 1s catching
behavior, one solution
used is to use an T
edge-triggered D as
the core of the flip-flop
C
D
T
Chapter 1 383
Basic Flip-Flop Descriptors
 Used in analysis
• Characteristic table - defines the next state of
the flip-flop in terms of flip-flop inputs and
current state
• Characteristic equation - defines the next state
of the flip-flop as a Boolean function of the
flip-flop inputs and the current state
 Used in design
• Excitation table - defines the flip-flop input
variable values as function of the current state
and next state
Chapter 1 384
D Flip-Flop Descriptors
 Characteristic Table
D Q(t + 1) Operation
0 0 Reset
1 1 Set
 Characteristic Equation
Q(t+1) = D
 Excitation Table
Q(t +1) D Operation
0 0 Reset
1 1 Set
Chapter 1 385
T Flip-Flop Descriptors
T Q(t + 1) Operation
0 Q (t) No change
1 Q (t) Complement
Q(t+1) = T Å Q
Q(t
+ 1) T Operation
Q (t) 0 No change
Q (t) 1 Complement
Chapter 1 386
S-R Flip-Flop Descriptors
S R Q(t + 1) Operation
0 0 Q (t) No change
0 1 0 Reset
1 0 1 Set
 Characteristic
1 1
Equation
? Undefined
Q(t+1) = S + R Q, S.R = 0
Q(t) Q(t+ 1) S R Operation
0 0 0 X No change
0 1 1 0 Set
1 0 0 1 Reset
1 1 X 0 No change
Chapter 1 387
J-K Flip-Flop Descriptors
J K Q(t + 1) Operation
0 0 Q (t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q (t) Complement
Q(t+1) = J Q + K Q
Q(t) Q(t 1) J K Operation
+
0 0 0 X No change
0 1 1 X Set
1 0 X 1 Reset
1 1 X 0 No Change
Chapter 1 388
Flip-flop Behavior Example
 Use the characteristic tables to find the output waveforms for
the flip-flops shown:
Clock
D,T
D QD
QT
T
Chapter 1 389
Flip-Flop Behavior Example (continued)
 Use the characteristic tables to find the output waveforms for
the flip-flops shown:
Clock
S,J
R,K
S QSR ?
C
R
J QJK
C
K
Chapter 1 390
Terms of Use
Education, Inc.
Chapter 1 391
Part 3 – State Machine Design
Charles Kime & Mano

Overview
 Part 1 - Storage Elements and Analysis

 Part 2 - Sequential Circuit Design
• Issues with traditional state diagrams and table representations
• The state machine diagram model
• Constraint checking
• State machine diagram application and design
Chapter 1 393
Finite State Machines
 A finite state machine (FSM) consists of three sets I, O,

and S and two functions f and g in which:
• I is a set of input combinations,
• O is a set of output combinations,
• S is a set of states
• f is the next state function f(I, S), and
• g is the output function f(S) [Moore model] or the output function
f(I, S) [Mealy model].
 The FSM is a fundamental mathematical model used for
sequential circuits.
 The details of the traditional state diagrams and state tables
as we have defined them are just two of many ways of
representing FSMs.
Chapter 1 394
Issues with Traditional State Diagram and
Table Representations
 Both of these traditional representations

require:
• Enumeration of all input combinations for each
state in defining next states
• Enumeration of all input combinations for each
state in defining Mealy outputs
• Enumeration of all applicable output
combinations for each state (Moore) and for
each input combination-state pair (Mealy).
 For state diagrams, all Mealy outputs must
be specified on transition arcs
Chapter 1 395
Issues with Traditional State Diagram and
Table Representations
 These requirements may be acceptable for

sequential circuits with relatively few
inputs, and outputs.
 For larger numbers of inputs and outputs
both representations become intractable.
 The specification of outputs only on
transition arcs complicates the specification
of outputs for Mealy circuits unnecessarily.
Chapter 1 396
The State Machine Diagram Model
 In response to the issues listed, a broader state

machine diagram (SMD) representation has been
devised.
 Many other authors have used similar
representations to overcome some of the issues we
have listed.
 The SMD achieves the flexibility of the
algorithmic state machine (ASM) (used in some
previous editions of this text), without adopting
the constraints of the ASM notation.
Chapter 1 397
The State Machine Diagram
 Uses state nodes and transition arcs as in the

traditional state diagram
 Adds notation for defining Mealy outputs on states
as well as transitions
 Is based on input conditions, transition conditions,
output conditions and output actions:
• Input condition: a Boolean expression or equation
which evaluates to either 0 or 1.
• Transition condition, (TC): an input condition on a
transition arc which evaluates to either 0 or 1.
• Output condition (OC): a input condition that if equal
to 1 causes an output action to occur and if 0 does not
cause the output to occur.
Chapter 1 398
State Machine Diagram
 Output Action Examples

• Single Variables
 Appearance of variable Z attached a state specifies
that Z = 1. Z is implicitly 0 otherwise.
 Appearance of variable Z attached to a transition
condition (and possibly an output condition) from a
state implies that Z = 1 for the condition(s) satisfied.
Z is implicitly 0 otherwise unless Z is a Moore
output (unconditional) attached to the state or is part
of a TCI label attached to a state.
 Separate default value statements may be used to
explicitly specify by default Z = 0 or Z = 1.
Chapter 1 399
State Machine Diagram
 Output Action Examples

• Vector Variables
 Appearance of an equation Z = vector value attached to a state
specifies the value of Z for the state.
 Appearance of an equation Z = vector value attached to a
transition condition (and possibly an output condition) from a
state specifies the value of Z for the state, transition condition
and output condition. The value of Z attached to a transition
may also be specified by a Moore output (unconditional)
attached to the state or as part of a TCI label attached to a
state. Otherwise, Z takes on a default value if one is specified .
The default value for a vector must be specified (including
possibly don’t cares).
• Register Transfer Outputs
 Useful for describing controlled datapath operations (see
Chapter 7)
Chapter 1 400
 A unconditional transition has no

transition condition on its arc or a
transition condition consisting of the
constant 1.
 A conditional transition has one or
more transition conditions on its arc. If
any one of the conditions evaluates to
1, the transition occurs.
Chapter 1 401
 Moore output actions, are unconditional, depending only on

the state, and are attached by a line to the respective state.
 Transition condition-independent (TCI) Mealy output actions
are preceded by their output condition and a slash and are
attached by a line to the respective state. The output action
occurs if the output condition evaluates to 1.
 Transition condition-dependent (TCD) Mealy output actions
are attached by a line to their respective transition condition.
The output action occurs if the output condition evaluates to 1.
 Transition and output condition-dependent (TCOD) Mealy
output actions are preceded by an output condition and a slash
and are attached by a line to their respective transition
condition. The output action occurs if the transition condition
and the output condition both evaluate to 1.
Chapter 1 402
 To summarize, in a given state, an output

action occurs if it is (a) unconditional (Moore),
(b) TCI and its output condition OC evaluates
to 1, (c) TCD and its transition condition TD
evaluates to 1, or (d) TOCD and its transition
condition TC and output condition OC both
evaluate to 1.
 Moore and TCI output actions attached to a
state, apply to all transitions from the state.
Chapter 1 403
 This may seem complex, but note the following:

• Only the unconditional output type applies to pure
Moore machines
• TDC outputs represents the traditional Mealy model
and can be used exclusively at some potential cost in
complexity including an increase in the number of
states.
• Mixing of Moore and Mealy types and the TCI and
TCOD types provide optional opportunities to simplify
the state diagram and state table and their specifications
Chapter 1 404
Examples Of Transition & Output Conditions
 Input Variables A, B, C A×B A×B
 Output Variables Y, Z S0 S1 S0 S1
Default: Y = 0, Z = 0 A + B
A + B
Y, Z A/Y, B/Z
S2 S2
Ex. 1: Moore Outputs Ex. 2: TCI Outputs
C/Y
A×B/Y A×B
S0 S1 S0 S1
C/Y
(A + B)/Z
(A + B)
S2 S2
Ex. 3: TCD Outputs Ex. 4: TCOD Outputs
Chapter 1 405
Constraint Checking
 TC Constraints
• Constraint 1: In state Si, for all possible TC pairs (Tij, Tik) on arcs to
distinct next states from Si,
Tij × Tik = 0
• Constraint 2: In state Si, for all possible TCs, Tij
S Tij = 1
 OC Constraints
• Constraint 1: For every output action in state Si or on its transitions having
coincident output variables with differing values, the corresponding pair
of output condition (Oij, Oik) must be mutually exclusive, i. e., satisfy
Oij × Oik = 0
• Constraint 2:For every output variable, the output conditions for state Si or
its transitions must cover all possible combinations of input variables that
can occur, i. e.,
S Oij = 1
• For both output constraints above, TCs must be used in evaluating O ij for
output actions of TCD and TCOD output action types
• See text for using don’t cares and defaults.
Chapter 1 406
Constraint Checking Example
Defaults: Y = 0, Z = 0  Transition Constraints:

Y, Z A/Y, B/Z
• S0: A××(
B× (A + B) = 0;
A×B + (A + B) = 1
A×B • S1: A×C×(A + C) = 0;
S0 S1 A×C + (A + C) = 1
A + B BC/Z
• S2: B×C× (B + C) = 0;
A
A×C B×C + (B + C) = 1
A + C
• S3: A × A = 0;
A+A= 1
B×C/Y
 Output Constraints:
A • Satisfied for all four states by the
(B + C)/Z given output conditions and values
and the default constraints.
S3 S2
B×C/Y
Chapter 1 407
Constraint Violation Examples
 Transition Constraints X
• Example A: X×Y ¹ 0 and X + Y ¹ 1, A
S0
Y
S1
so two constraints are violated

• Example B: X×XY = 0, but X + XY ¹ 1.
B
S0 S2
so constraint 2 is violated X
 Outputs XY
S1
• Example C: For values Z = 1 and Z = 0, S2
X×Y ¹ 0, so constraint 1 is violated

• Constraint X + Y + Y = 1, C S0
Y
S1
due to the default value of Z on Y, so Y/Z
constraint 2 is satisfied X/Z S2

• Example D: In general, for a given state, since the output
condition for a Moore type output action is 1, no output action on
a same output variable with a different value is permitted on the
transitions.
Chapter 1 408
State Table Format
State State Transition Next Next Output Ac-

Code Condition State State tions (and
Code OCs)
State State Unused Unconditional Next State Moore or TCI
Name 1 Code 1 Next State 1 Code 1 Output (and
OC)
Transition Next State 11 Next State TCD or TOCD
Cond. 11 Code 11 Output 11(and
OC)
Additional Transition Conditions and Entries for State Name
1
State Entries for State Names i, i = 2, …n
Name i
Chapter 1 409
State Table Example
 State table for constraint checking example

State State Transition Next Next Output Actions
Code Condition State State (OCs)
Code
S0 00 Y,Z
A×B S1 01
A+ B S2 10
S1 01 A/Y, B/Z
A×C S2 10
A+ C S3 11
 Continued on next slide
Chapter 1 410
State Table Example (continued)
 State table for constraint checking example

State State Transition Next Next Output Actions
Code Condition State State (OCs)
Code
S2 10
B×C S3 11 Y*
B+C S0 00 Z*
S3 11
A S0 00 B×C/Y*
A S1 01 B×C/Y*
 * is reminder of an output action dependent on transition

condition
Chapter 1 411
State Machine Design Procedure
 Define the input and output variables for the

circuit or system and meaning of 0 and 1 values of
each variable
 Draw the state machine diagram or formulate the
state machine table for the circuit or system
 If a state machine diagram is used, convert it to a
state machine table
 From the state machine table, derive optimized
next state equations and output equations for the
circuit or system
Chapter 1 412
Example State Machine Design –
Elevator Control – Inputs
 Circuit: Elevator control for two-floor elevator
 Warning: Does not include safety features or all user buttons!
 C1(C2) – Call button (outside elevator) to floor 1(2)
 0 – no action; 1 – call for elevator
 G1(G2) – Go button (inside elevator) to floor 1(2)
• 0 – no action; 1 – go to floor command
 F1(F2) – Senses elevator at floor 1(2)
• 0 – elevator not at floor; 1 – elevator at floor
 S1(S2) – Senses elevator approaching floor 1(2) (Controls slowdown of
elevator)
• 0 – elevator not approaching floor; 1 – elevator approaching floor
 DO – Doors open
• 0 – doors not fully open; 1 – doors fully open
 TO – End of time interval from button push to elevator movement starting
• 0 – waiting for time interval to end; 1 – time interval has ended
 DC – Doors closed
• 0 – doors not closed; 1 – doors closed
Chapter 1 413
Example – Elevator Control - Outputs
• Up – elevator to go up
 0 – no action; 1 – commands elevator to go up
• Down – commands elevator to go down
 0 – no action; 1 – commands elevator to go down
• TS – timer start
 0 – no action; 1 – initialize and start timer
• SD – slow down
 0 – elevator moves as normal speed; 1 – elevator approaching
target floor slows down
• OD – Open Doors
 0 – no action; 1 – open doors
• CD – Close Doors
 0 – no action; 1 – close doors
Chapter 1 414
Example – Elevator Operation –
Specifications
 The elevator parks at the floor to which it has last taken passengers
with doors open.
 Call button Ci calls elevator to a floor.
 If the elevator is not at the floor, TS is used to initialize and start the
timer;
 After TO becomes 1, the doors close, and when DC is active, the Up
or Down output is activated.
 The Si sensor detects the floor approach and activates output SD to
slow elevator.
 The Fi sensor detects the elevator at the floor, forces both Up and Dn
to 0, and opens the doors.
 Passenger(s) enter elevator and push the Gi button.
 After TO becomes 1, the doors close, and when DC is active, the Up
or Down output is activated.
 The Si sensor detects the approach and activates output SD to slow
elevator.
 The Fi sensor detects the elevator at the floor, forces both Up and Dn
to 0, and opens the doors, permitting passengers to exit.
Chapter 1 415
Example – Elevator Control – States
 Initial proposed states:

• U (Up)
• Dn (Down)
• Hd (Hold)
 Series of actions required in Hd state:
• Open doors
• Use timer to wait for passengers
• Close doors
 Expand Hd to 3 states: Hd_A, Hd_B, Hd_C
 One-Hot State Vector:
(U, Dn, Hd_C, Hd_B, Hd_A)
Chapter 1 416
Example – Elevator Control – SMD
S1/SD
F1
F1 Dn
Down
DO×(F1×(C2 + G2) + F2(C1 + G1))

DC×F2
TO
TO
Hd_A Hd_B Hd_C DC×(F1 + F2)/CD
DO/OD
DC×F1
Up
DO×(F1×(C2 + G2) + F2(C1 + G1))/TS F2 F2

U
S2/SD
Chapter 1 417
Example – Elevator Control – SMT
State State Transition Next Next Output

Code Condition State State Actions
Code (OCs)
DO/OD
Hd_A 00001 (DO×(F1×(C2 + Hd_A 00001
G2) + F2 ×(C1 +
G1))
DO×(F1×(C2 + G2) Hd_B 00010 TS*
+ F2 ×(C1 + G1)
Hd_B 00010 TO Hd_B 00010
TO Hd_C 00100
Hd_C 00100 DC×(F1 + F2) Hd_C 00100 CD*
DC×F2 Dn 01000
DC×F1 Up 10000
Chapter 1 418
Example – Elevator Control – SMT
State State Transition Next Next Output

Code Condition State State Actions
Code (OCs)
Dn 01000 Down,
S1/SD
F1 Dn 01000
F1 Hd_A 00001
U Up, S2/SD
F2 Up 10000
F2 Hd_A 00001
Chapter 1 419
Example – Elevator Control - Equations
 Flip-Flop Input  Output

• X = DO×((F1×(C2 + G2)  Down = Dn
+ F2 ×(C1 + G1))  Up = U
• Y = DC×(F1 + F2)
 SD = Dn×S1 + U×S2
• DHd_A = Hd_A×X + Dn×F2 +
 TS = Hd_A×X
U×F1
• DHd_B = Hd_A×X + Hd_B×TO
 OD = Hd_A×DO
• DHd_C = Hd_B×TO + Hd_C×Y

 CD = Hd_C×Y
• DDn = Hd_C× DC×F2 + Dn×F1

• DU = Hd_C×DC×F1 +U×F2
Chapter 1 420
Terms of Use
Education, Inc.
Chapter 1 421
Chapter 6 – Selected Design Topics
Part 1 – The Design Space
Charles Kime & ManoA

Overview
 Part 1 – The Design Space

• Integrated Circuits
 Levels of Integration
• CMOS Circuit Technology
 CMOS Transistor Models
 Circuits of Switches
 Fully Complementary CMOS Circuits
 Technology Parameters
 Part 2 – Propagation Delay and Timing
 Part 3 – Asynchronous Interactions
 Part 4 - Programmable Implementation
Technologies
Chapter 1 423
Integrated Circuits
 Integrated circuit (informally, a “chip”) is a

semiconductor crystal (most often silicon) containing
the electronic components for the digital gates and
storage elements which are interconnected on the chip.
 Terminology - Levels of chip integration
• SSI (small-scale integrated) - fewer than 10 gates
• MSI (medium-scale integrated) - 10 to 100 gates
• LSI (large-scale integrated) - 100 to thousands of gates
• VLSI (very large-scale integrated) - thousands to 100s of
millions of gates
Chapter 1 424
MOS Transistor
0 V olts
0 V olts
G (G ate) V V olts
DD
S (Source) D (D rain)
n-Channel T ransistor : OFF - no D-to-S Cur r ent
Channel
length Location of
conducting
layer
Substrate
Chapter 1 425
MOS Transistor
V D D Volts
0 Volts G (G ate) V D D Volts
S (Source) D (D rain)
n-Channel Transistor: ON - D -to-S Current
Channel
length Location of
conducting
layer
Substrate
Chapter 1 426
Switch Models for MOS Transistors
 n-Channel – Normally Open (NO) Switch Contact

D
G
X •
X: X: X
•
S
Symbol Switch Model: Simplifed
Switch Model
 p-Channel – Normally Closed (NC) Switch Contact
S
G
X • • X: X
X:
•
D
Switch Model Simplified
Symbol
Switch Model
Chapter 1 427
Circuits of Switch Models
 Series
X: X
X A ND Y
Y: Y
Series
 Parallel
X: X Y: Y X O R Y
Parallel
Chapter 1 428
Fully-Complementary CMOS Circuit
 Circuit structure for fully-complementary CMOS

gate logic 1 +V
F using
•
p-type
•
•
transistors
(NC switches)
• F
X1 •
X2 F using
• n-type
•• •
•
• • transistors
Xn • (NO switches)
logic 0
Chapter 1 429
CMOS Circuit Design Example
 Find a CMOS gate with the following

function: F = X Z + Y Z = (X + Y)Z
 Beginning with F0, and using F
F0 Circuit: F = X Y + Z
 The switch model circuit in terms of NO
switches:
X: X
Z: Z
Y: Y
Chapter 1 430
 The switch model circuit for F1 in terms of NC

contacts is the dual of the switch model circuit for
F0:
X: X Y: Y
Z: Z
 The function for this circuit is:
F1 Circuit: F = (X + Y) Z
which is the correct F.
Chapter 1 431
+V
 Replacing the From F 1 •
switch models
• •
with CMOS
•
transistors;
note input •
Z must be • •
used. X •
Z •
Y •
From F 0
•
Chapter 1 432
Technology Parameters
 Specific gate implementation technologies are characterized

by the following parameters:
• Fan-in – the number of inputs available on a gate
• Fan-out – the number of standard loads driven by a gate output
• Logic Levels – the signal value ranges for 1 and 0 on the inputs and 1
and 0 on the outputs (see Figure 1-1)
• Noise Margin – the maximum external noise voltage superimposed on
a normal input value that will not cause an undesirable change in the
circuit output
• Cost for a gate - a measure of the contribution by the gate to the cost
of the integrated circuit
• Propagation Delay – The time required for a change in the value of a
signal to propagate from an input to an output
• Power Dissipation – the amount of power drawn from the power
supply and consumed by the gate
Chapter 1 433
Fan-out
 Fan-out can be defined in terms of a

standard load
• Example: 1 standard load equals the load
contributed by the input of 1 inverter.
• Transition time -the time required for the gate
output to change from H to L, tHL, or from L to
H, tLH
• The maximum fan-out that can be driven by a
gate is the number of standard loads the gate
can drive without exceeding its specified
maximum transition time
Chapter 1 434
Cost
 In an integrated circuit:
• The cost of a gate is proportional to the chip area
occupied by the gate
• The gate area is roughly proportional to the number and
size of the transistors and the amount of wiring
connecting them
• Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
• So gate input count is a rough measure of gate cost
 If the actual chip layout area occupied by the gate
is known, it is a far more accurate measure
Chapter 1 435
Terms of Use
Education, Inc.
Chapter 1 436
Chapter 6 –Selected Design Topics
Part 2 – Propagation Delay and Timing
Charles Kime & Mano

Overview

• Propagation Delay
• Delay Models
• Cost/Performance Tradeoffs
• Flip-Flop Timing
• Circuit & System Level Timing
Technologies
Chapter 1 438
Propagation Delay
 Propagation delay is the time for a change on an input of a

gate to propagate to the output.
 Delay is usually measured at the 50% point with respect to
the H and L output voltage levels.
 High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
 High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
 An HL input transition causes:
• an LH output transition if the gate inverts and
• an HL output transition if the gate does not invert.
Chapter 1 439
Propagation Delay (continued)
IN
IN OUT OUT t PHL t PLH
t pd 5 max (t PHL , tPLH )

 Propagation delays measured at the midpoint
between the L and H values
 What is the expression for the tPHL delay for:
• a string of n identical buffers?
• a string of n identical inverters?
Chapter 1 440
Propagation Delay Example
 Find tPHL, tPLH and tpd for the signals given

IN (volts)
OUT (volts)
t (ns)
1.0 ns per division
Chapter 1 441
Delay Models
 Transport delay - a change in the output in

response to a change on the inputs occurs after a
fixed specified delay
 Inertial delay - similar to transport delay, except
that if the input changes such that the output is to
change twice in a time interval less than the
rejection time, the output changes do not occur.
Models typical electronic circuit behavior, namely,
rejects narrow “pulses” on the outputs
Chapter 1 442
Delay Model Example
A B:
No Delay
(ND)
a b c d e
Transport
Delay (TD)
Inertial
Delay (ID)
0 2 4 6 8 10 12 14 16 Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns

Chapter 1 443
Circuit Delay
 Suppose gates with delay n ns are

represented for n = 0.2 ns, n = 0.4 ns,
n = 0.5 ns, respectively:
0.2 0.4 0.5
Chapter 1 444
Circuit Delay
 Consider a simple A
2-input multiplexer: 0.4
Y
• Y = A for S = 1 0.5
• Y = B for S = 0 S
B 0.4
A
B
S
Y
 “Glitch” is due to delay of inverter
Chapter 1 445
Fan-out and Delay
 The fan-out loading a gate’s output affects the

gate’s propagation delay
 Example:
• One realistic equation for t pd for a NAND gate with 4
inputs is:
tpd = 0.07 + 0.021 SL ns
• SL is the number of standard loads the gate is driving, i.
e., its fan-out in standard loads
• For SL = 4.5, tpd = 0.165 ns
 If this effect is considered, the delay of a gate in
a circuit takes on different values depending on
the circuit load on its output.
Chapter 1 446
Cost/Performance Tradeoffs
 Gate-Level Example:
• NAND gate G with 20 standard loads on its output has a delay of
0.45 ns and has a normalized cost of 2.0
• A buffer H has a normalized cost of 1.5. The NAND gate driving
the buffer with 20 standard loads gives a total delay of 0.33 ns
• In which if the following cases should the buffer be added?
1. The cost of this portion of the circuit cannot be more than 2.5
2. The delay of this portion of the circuit cannot be more than 0.40 ns
3. The delay of this portion of the circuit must be less than 0.30 ns and the
cost less than 3.0
 Tradeoffs can also be accomplished much higher in the
design hierarchy
 Constraints on cost and performance have a major role in
making tradeoffs
Chapter 1 447
Flip-Flop Timing Parameters
 ts - setup time t wH $ t wH,min
C t wL $ t wL,min
 th - hold time
t s th
 tw - clock S /R
t
pulse width
p-,min
t p-,max
 tpx - propa- Q
(a) Pulse-triggered (positive pulse)
gation delay t wH $ t wH,min
• tPHL - High-to-
C t wL $ t wL,min
Low
ts t h
• tPLH - Low-to-
D
High t p-,min
• tpd - max (tPHL, t p-,max
tPLH) Q
(b) Edge-triggered (negative edge)

Chapter 1 448
Flip-Flop Timing Parameters
 ts - setup time
• Master-slave - Equal to the width of the triggering
pulse
• Edge-triggered - Equal to a time interval that is
generally much less than the width of the the triggering
pulse
 th - hold time - Often equal to zero
 tpx - propagation delay
• Same parameters as for gates except
• Measured from clock edge that triggers the output
change to the output change
Chapter 1 449
Circuit and System Level Timing
 Consider a system
comprised of ranks D
C
Q
Q'
D
C
Q
Q'
of flip-flops D Q D Q
connected by logic: C Q' C Q'
 If the clock period is D
C
Q
Q'
D
C
Q
Q'
too short, some D Q D Q
data changes will not C Q' C Q'
propagate through the D Q D Q
circuit to flip-flop
C Q' C Q'
inputs before the setup

CLOCK CLOCK
time interval begins
Chapter 1 450
 New Timing Components

•t p - clock period - The interval between occurrences of
a specific clock edge in a periodic clock
• tpd,COMB - total delay of combinational logic along the
path from flip-flop output to flip-flop input
• tslack - extra time in the clock period in addition to the
sum of the delays and setup time on a path
 Can be either positive or negative
 Must be greater than or equal to zero on all paths for correct
operation
Chapter 1 451
 Timing components along a path from flip-flop to

flip-flop
tp
C
t pd,FF t pd,COMB ts t slack
(a) Edge-triggered (positive edge)
tp
C
t pd,FF t pd,COMB t slack ts
(b) Pulse-triggered (negative pulse)
Chapter 1 452
 Timing Equations
tp = tslack + (tpd,FF + tpd,COMB + ts)
• For t slack greater than or equal to zero,
tp ≥ max (tpd,FF + tpd,COMB + ts)
for all paths from flip-flop output to flip-flop input
 Can be calculated more precisely by using tPHL and
tPLH values instead of tpd values, but requires
consideration of inversions on paths
Chapter 1 453
Calculation of Allowable tpd,COMB
 Compare the allowable combinational delay for a

specific circuit:
a) Using edge-triggered flip-flops
b) Using master-slave flip-flops
 Parameters
• t (max) = 1.0 ns
pd,FF
• t (max) = 0.3 ns for edge-triggered flip-flops

s
• t = t = 1.0 ns for master-slave flip-flops

s wH
• Clock frequency = 250 MHz
Chapter 1 454
Calculation of Allowable tpd,COMB
 Calculations: tp = 1/clock frequency = 4.0 ns

• Edge-triggered: 4.0 ≥ 1.0 + tpd,COMB + 0.3, tpd,COMB ≤ 2.7 ns
• Master-slave: 4.0 ≥ 1.0 + tpd,COMB + 1.0, tpd,COMB ≤ 2.0 ns
 Comparison: Suppose that for a gate, average tpd = 0.3 ns
• Edge-triggered: Approximately 9 gates allowed on a path
• Master-slave: Approximately 6 to 7 gates allowed on a path
Chapter 1 455
Terms of Use
Education, Inc.
Chapter 1 456
Chapter 6 – Selected Design Topics
Part 4 – Programmable Implementation Technologies
Charles Kime & Mano

Overview

Technologies
• Why Programmable Logic?
• Programming Technologies
• Read-Only Memories (ROMs)
• Programmable Logic Arrays (PLAs)
• Programmable Array Logic (PALs)
Chapter 1 458
Why Programmable Logic?
 Facts:
• It is most economical to produce an IC in large
volumes
• Many designs required only small volumes of ICs
 Need an IC that can be:
• Produced in large volumes
• Handle many designs required in small volumes
 A programmable logic part can be:
• made in large volumes
• programmed to implement large numbers of different
low-volume designs
Chapter 1 459
Programmable Logic - More Advantages
 Many programmable logic devices are field-

programmable, i. e., can be programmed outside of the
manufacturing environment
 Most programmable logic devices are erasable and
reprogrammable.
• Allows “updating” a device or correction of errors
• Allows reuse the device for a different design - the ultimate in re-
usability!
• Ideal for course laboratories
 Programmable logic devices can be used to prototype
design that will be implemented for sale in regular ICs.
• Complete Intel Pentium designs were actually prototyped with
specialized systems based on large numbers of VLSI
programmable devices!
Chapter 1 460
Programming Technologies
 Programming technologies are used to:

• Control connections
• Build lookup tables
• Control transistor switching
 The technologies
• Control connections
 Mask programming
 Fuse
 Antifuse
 Single-bit storage element
Chapter 1 461
Programming Technologies
 The technologies (continued)

• Build lookup tables
 Storage elements (as in a memory)
• Transistor Switching Control
 Stored charge on a floating transistor gate
• Erasable
• Electrically erasable
• Flash (as in Flash Memory)
 Storage elements (as in a memory)
Chapter 1 462
Technology Characteristics
 Permanent - Cannot be erased and reprogrammed

 Mask programming
 Fuse
 Antifuse
 Reprogrammable
• Volatile - Programming lost if chip power lost
 Single-bit storage element
• Non-Volatile
 Erasable
 Electrically erasable
 Flash (as in Flash Memory)
Chapter 1 463
Programmable Configurations
 Read Only Memory (ROM) - a fixed array of AND

gates and a programmable array of OR gates
 Programmable Array Logic (PAL)Ò - a
programmable array of AND gates feeding a fixed
array of OR gates.
 Programmable Logic Array (PLA) - a programmable
array of AND gates feeding a programmable array of
OR gates.
 Complex Programmable Logic Device (CPLD)
/Field- Programmable Gate Array (FPGA) -
complex enough to be called “architectures” - See
VLSI Programmable Logic Devices reading supplement
PAL is a registered trademark of Lattice Semiconductor Corp. Chapter 1 464
ROM, PAL and PLA Configurations
Fixed Programmable Programmable

Inputs AND array Outputs
Connections OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array
(b) Programmable array logic (PAL) device
Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array
(c) Programmable logic array (PLA) device
Chapter 1 465
Read Only Memory
 Read Only Memories (ROM) or Programmable Read

Only Memories (PROM) have:
• N input lines,
• M output lines, and
• 2N decoded minterms.
 Fixed AND array with 2N outputs implementing all
N-literal minterms.
 Programmable OR Array with M outputs lines to
form up to M sum of minterm expressions.
Chapter 1 466
Read Only Memory
 A program for a ROM or PROM is simply a

multiple-output truth table
• If a 1 entry, a connection is made to the
corresponding minterm for the corresponding
output
• If a 0, no connection is made
 Can be viewed as a memory with the inputs as
addresses of data (output values), hence ROM or
PROM names!
Chapter 1 467
Read Only Memory Example
 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)

 The fixed "AND" array is a
“decoder” with 3 inputs and 8 D7 X X X
outputs implementing minterms. D6
D5 X X
 The programmable "OR“ D4 X
array uses a single line to A A2

D3
D2
X
represent all inputs to an B A1 D1 X X

X
OR gate. An “X” in the C
A0 D0
array corresponds to attaching the

minterm to the OR
 Read Example: For input (A2,A1,A0)
F3 F2 F1 F0
= 011, output is (F3,F2,F1,F0 ) = 0011.

 What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
Chapter 1 468
Programmable Array Logic (PAL)
 The PAL is the opposite of the ROM, having a
programmable set of ANDs combined with fixed ORs.
 Disadvantage
• ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
 Advantages
• For given internal complexity, a PAL can have larger N and M
• Some PALs have outputs that can be complemented, adding POS
functions
• No multilevel circuit implementations in ROM (without external
connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
Chapter 1 469
Programmable Array Logic Example
AND gates inputs
 4-input, 3-output PAL 0 1 2 3 4 5

X
6 7 8 9
with fixed, 3-input OR

Product
1
term
X X
terms
2 1
 What are the equations I 1 5 A

X X X
for F1 through F4? 4

X X
F1 = A B
+ C 5
X X
F 2
F2 = A
B C + AC + AB 6
I2 5 B
F3 = X X
F4 = 8
X X
F 3
I3 5 C
X X
10
X X
11 F 4
12
I4
Chapter 1 470
Programmable Logic Array (PLA)
 Compared to a ROM and a PAL, a PLA is the

most flexible having a programmable set of ANDs
combined with a programmable set of ORs.
 Advantages
• A PLA can have large N and M permitting
implementation of equations that are impractical for a
ROM (because of the number of inputs, N, required
• A PLA has all of its product terms connectable to all
outputs, overcoming the problem of the limited inputs
to the PAL Ors
• Some PLAs have outputs that can be complemented,
adding POS functions
Chapter 1 471
Programmable Logic Array (PLA)
 Disadvantages
• Often, the product term count limits the application of a
PLA.
• Two-level multiple-output optimization is required to
reduce the number of product terms in an
implementation, helping to fit it into a PLA.
• Multi-level circuit capability available in PAL not
available in PLA. PLA requires external connections to
do multi-level circuits.
Chapter 1 472
Programmable Logic Array Example
A
 What are the equations for F1 and F2?
B  Could the PLA implement the
functions without the XOR gates?

C
X X 1 X X
AB
X X 2 X
BC X Fuse intact
Fuse blown
X 3
X X
AC
X 4 X
X
AB
X
C C B B A A 0
X
1
 3-input, 3-output PLA
F 1
with 4 product terms

F 2
Chapter 1 473
Terms of Use
Education, Inc.
Chapter 1 474
Chapter 7 – Registers and Register Transfers
Part 1 – Registers, Microoperations and Implementations
Charles Kime & Mano

Overview
 Part 1 - Registers, Microoperations and

Implementations
• Registers and load enable
• Register transfer operations
• Microoperations - arithmetic, logic, and shift
• Microoperations on a single register
 Multiplexer-based transfers
 Shift registers
 Part 2 - Counters, Register Cells, Buses, & Serial
Operations
 Part 3 – Control of Register Transfers
Chapter 1 476
Registers
 Register – a collection of binary storage

elements
 In theory, a register is sequential logic
which can be defined by a state table
 More often, think of a register as storing a
vector of binary values
 Frequently used to perform simple data
storage and data movement and processing
operations
Chapter 1 477
Example: 2-bit Register
 How many states are there? A1

In1 Y1
D Q
 How many input combinations?
Output combinations? C
A0
 What is the output function? In0 D Q Y0
 What is the next state function? CP C
 Moore or Mealy? Current Next State Output
State Table: State A1(t+ 1 ) A0(t+ 1) (=A1 A0)

For In1 In0 =
A1 A0 00 01 10 11 Y1 Y0
0 0 00 01 10 11 0 0
0 1 00 01 10 11 0 1
1 0 00 01 10 11 1 0
1 1 00 01 10 11 1 1
 What are the quantities above for an n-bit register?
Chapter 1 478
Register Design Models
 Due to the large numbers of states and input

combinations as n becomes large, the state
diagram/state table model is not feasible!
 What are methods we can use to design registers?
• Add predefined combinational circuits to registers
 Example: To count up, connect the register flip-flops to an
incrementer
• Design individual cells using the state diagram/state
table model and combine them into a register
 A 1-bit cell has just two states
 Output is usually the state variable
Chapter 1 479
Register Storage
 Expectations:
• A register can store information for multiple clock cycles
• To “store” or “load” information should be controlled by a signal
 Reality:
• A D flip-flop register loads information on every clock cycle
 Realizing expectations:
• Use a signal to block the clock to the register,
• Use a signal to control feedback of the output of the register back to its
inputs, or
• Use other SR or JK flip-flops, that for (0,0) applied, store their state
 Load is a frequent name for the signal that controls register
storage and loading
• Load = 1: Load the values on the data inputs
• Load = 0: Store the values in the register
Chapter 1 480
Registers with Clock Gating
 The Load signal enables the clock signal to pass through if 1

and prevents the clock signal from passing through if 0.
 Example: For Positive Edge-Triggered or Negative Pulse
Master-Slave Flip-flop:
Clock
Load
Gated Clock to FF
 What logic is needed for gating?
 What is the problem? Gated Clock = Clock + Load
Clock Skew of gated clocks with respect to clock or each other
Chapter 1 481
Registers with Load-Controlled Feedback
 A more reliable way to selectively load a register:
• Run the clock continuously, and
• Selectively use a load control to change the register contents.
 Example: 2-bit register
with Load Control:
2-to-1 Multiplexers
 For Load = 0,
loads register contents
(hold current values)
 For Load = 1, A1
Y1
loads input values Load D Q
(load new values) In1

C
 Hardware more complex
than clock gating, but A0
Y0
free of timing problems D
C
Q
In0
Clock
Chapter 1 482
Register Transfer Operations
 Register Transfer Operations – The movement

and processing of data stored in registers
 Three basic components:
• set of registers
• operations
• control of operations
 Elementary Operations -- load, count, shift, add,
bitwise "OR", etc.
• Elementary operations called microoperations
Chapter 1 483
Register Notation
R 76543210
15 8 7 0 15 0
PC(H) PC(L) R2
 Letters and numbers – denotes a register (ex. R2, PC, IR)

 Parentheses ( ) – denotes a range of register bits (ex. R1(1),
PC(7:0), PC(L))
 Arrow () – denotes data transfer (ex. R1  R2, PC(L) 
R0)
 Comma – separates parallel operations
 Brackets [ ] – Specifies a memory address (ex. R0  M[AR],
R3  M[PC] )
Chapter 1 484
Conditional Transfer
 If (K1 =1) then (R2  R1)

K
is shortened to 1
K1: (R2  R1) n

Load
R1 R2
where K1 is a control
variable specifying a
conditional execution Clock
of the microoperation.
Clock
K1
Transfer Occurs Here
No Transfers Occur Here
Chapter 1 485
Microoperations
 Logical Groupings:
• Transfer - move data from one register to another
• Arithmetic - perform arithmetic on data in registers
• Logic - manipulate data or use bitwise logical operations
• Shift - shift data in registers
Arithmetic operations Logical operations
+ Addition  Logical OR
– Subtraction  Logical AND
* Multiplication  Logical Exclusive OR
/ Division
 Not
Chapter 1 486
Example Microoperations
 Add the content of R1 to the content of R2

and place the result in R1.
R1 R1 + R2
 Multiply the content of R1 by the content of
R6 and place the result in PC.
PC  R1 * R6
 Exclusive OR the content of R1 with the
content of R2 and place the result in R1.
R1  R1  R2
Chapter 1 487
Example Microoperations (Continued)
 Take the 1's Complement of the contents of

R2 and place it in the PC.
 PC  R2
 On condition K1 OR K2, the content of R1
is Logic bitwise Ored with the content of
R3 and the result placed in R1.
 (K1 + K2): R1  R1  R3
 NOTE: "+" (as in K1 + K2) and means
“OR.” In R1  R1 + R3, + means “plus.”
Chapter 1 488
Control Expressions
 The control expression for an  Example:

operation appears to the left
of the operation and is X K1 : R1  R1 + R2
separated from it by a colon X K1 : R1  R1 + R2 + 1

 Control expressions specify  Variable K1 enables the add or subtract
the logical condition for the
operation to occur operation.
 Control expression values of:  If X =0, then X =1 so X K1 = 1,
• Logic "1" -- the operation activating the addition of R1 and R2.

occurs.  If X = 1, then X K1 = 1, activating the addition
• Logic "0" -- the operation is
does not occur. of R1 and the two's complement of R2
(subtract).
Chapter 1 489
Arithmetic Microoperations
 From Symbolic Designation Description

Table R0 ¬ R1 + R2 Addition
7-3: R0 ¬ R1 Ones Complement
R0 ¬ R1 + 1 Two's Complement
R0 ¬ R2 + R1 + 1 R2 minus R1 (2's Comp)
R1 ¬ R1 + 1 Increment (count up)
R1 ¬ R1 – 1 Decrement (count down)
 Note that any register may be specified for source

1, source 2, or destination.
 These simple microoperations operate on the
whole word
Chapter 1 490
Logical Microoperations
 From Table 7-4:
Symbolic Description
Designation
R0 ¬ R1 Bitwise NOT
R0 ¬ R1 Ú R2 Bitwise OR (sets bits)
R0 ¬ R1 Ù R2 Bitwise AND (clears bits)
R0 ¬ R1 Å R2 Bitwise EXOR (complements bits)
Chapter 1 491
Logical Microoperations (continued)
 Let R1 = 10101010,
and R2 = 11110000
 Then after the operation, R0 becomes:
R0 Operation
01010101 R0  R1
11111010 R0  R1  R2
10100000 R0  R1  R2
01011010 R0  R1  R2
Chapter 1 492
Shift Microoperations
 From Table 7-5: Symbolic Description

 Let R2 = 11001001 Designation
 Then after the R1 ¬ sl R2 Shift Left
operation, R1 R1 ¬ sr R2 Shift Right
becomes: R1 Operation
10010010 R1 ¬ sl R2
01100100 R1 ¬ sr R2
 Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data
shifted in, or to “catch” the data shifted out.
 Other shifts are possible (rotates, arithmetic) (see Chapter 10).
Chapter 1 493
Register Transfer Structures
 Multiplexer-Based Transfers - Multiple inputs are selected

by a multiplexer dedicated to the register
 Bus-Based Transfers - Multiple inputs are selected by a
shared multiplexer driving a bus that feeds inputs to
multiple registers
 Three-State Bus - Multiple inputs are selected by
3-state drivers with outputs connected to a bus that feeds
multiple registers
 Other Transfer Structures - Use multiple multiplexers,
multiple buses, and combinations of all the above
Chapter 1 494
Multiplexer-Based Transfers
 Multiplexers connected to register inputs produce flexible

transfer structures (Note: Clocks are omitted for clarity)
 The transfers are: K1: R0  R1
K2×K1: R0  R2
Load
K
R2 2
K
1
Load
n S
0 n
MUX R0
n
Load 1
R1
Chapter 1 495
Shift Registers
 Shift Registers move data laterally within the register toward its
MSB or LSB position
 In the simplest case, the shift register is simply a set of
D flip-flops connected in a row like this:
In A B C Out
DQ DQ DQ DQ
CP
 Data input, In, is called a serial input or the shift right input.
 Data output, Out, is often called the serial output.
 The vector (A, B, C, Out) is called the parallel output.
Chapter 1 496
Shift Registers (continued)
 The behavior of the

A B C
serial shift register In
D Q D Q D Q D Q
Out
is given in the listing

on the lower right
 T0 is the register
Clock CP
state just before
the first clock CP In A B C Out
pulse occurs T0 0 ? ? ? ?
 T1 is after the T1 1 0 ? ? ?
first pulse and T2 1 1 0 ? ?
before the second.
T3 0 1 1 0 ?
 Initially unknown
T4 1
states are denoted by “?” T5 1
 Complete the last three T6 1
rows of the table
Chapter 1 497
Parallel Load Shift Registers
 By adding a mux DA DB
between each shift register A B
stage, data can be IN D

Q
D
Q
shifted or loaded
 If SHIFT is low, SHIFT
A and B are CP
replaced by the data on DA and DB lines, else data shifts right

on each clock.
 By adding more bits, we can make n-bit parallel load shift
registers.
 A parallel load shift register with an added “hold” operation
that stores data unchanged is given in Figure 7-10 of the text.
Chapter 1 498
Shift Registers with Additional Functions
 By placing a 4-input multiplexer in front of each D flip-

flop in a shift register, we can implement a circuit
with shifts right, shifts left, parallel load, hold.
 Shift registers can also be designed to shift more than a
single bit position right or left
 Shift registers can be designed to shift a variable number
of bit positions specified by a variable called a shift
amount.
Chapter 1 499
Terms of Use

Education, Inc.
Chapter 1 500
Part 2 – Counters, Register Cells, Buses, & Serial Operations
Charles Kime & Mano

Overview
 Part 1 – Registers, Microoperations and

Implementations
 Part 2 – Counters, register cells, buses, & serial
operations
• Microoperations on single register (continued)
 Counters
• Register cell design
• Multiplexer and bus-based transfers for multiple registers
• Serial transfers and microoperations
Chapter 1 502
Counters
 Counters are sequential circuits which "count" through a

specific state sequence. They can count up, count down,
or count through other fixed sequences. Two distinct types
are in common usage:
 Ripple Counters
• Clock connected to the flip-flop clock input on the LSB bit flip-
flop
• For all other bits, a flip-flop output is connected to the clock input,
thus circuit is not truly synchronous!
• Output change is delayed more for each bit toward the MSB.
• Resurgent because of low power consumption
 Synchronous Counters
• Clock is directly connected to the flip-flop clock inputs
• Logic is used to implement the desired state sequencing
Chapter 1 503
Ripple Counter
 How does it work?

D A
• When there is a positive Clock

edge on the clock input CR
of A, A complements
• The clock input for flip- D B
flop B is the complemented CR

output of flip-flop A Reset
• When flip A changes

from 1 to 0, there is a CP
positive edge on the
clock input of B A
causing B to
B
complement
0 1 2 3 0 1
Chapter 1 504
Ripple Counter (continued)
 The arrows show the

cause-effect relation- CP
ship from the prior
slide => A
 The corresponding B
sequence of states => 0 1 2 3 0 1
(B,A) = (0,0), (0,1), (1,0), (1,1), (0,0), (0,1), …

 Each additional bit, C, D, …behaves like bit B,
changing half as frequently as the bit before it.
 For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),
(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …
Chapter 1 505
 These circuits are called ripple counters because

each edge sensitive transition (positive in the
example) causes a change in the next flip-flop’s
state.
 The changes “ripple” upward through the chain of
flip-flops, i. e., each transition occurs after a
clock-to-output delay from the stage before.
 To see this effect in detail look at the waveforms
on the next slide.
Chapter 1 506
 Starting with C = B = A = 1, equivalent to (C,B,A)

= 7 base 10, the next clock increments the count to
(C,B,A) = 0 base 10. In fine timing detail:
• The clock to output delay
tPHL causes an increasing tPHL
delay from clock edge for CP
each stage transition. tPHL
• Thus, the count “ripples” A
from least to most tpHL
significant bit. B
• For n bits, total worst case

delay is n tPHL. C
Chapter 1 507
Synchronous Counters
 To eliminate the "ripple" effects, use a common clock for

each flip-flop and a combinational circuit to generate the
next state.
 For an up-counter,
use an incrementer =>
Incre-menter
A3 S3 D3 Q3
A2 S2 D2 Q2
A1 S1 D1 Q1
A0 S0 D0 Q0
Clock
Chapter 1 508
Synchronous Counters (continued)
 Internal details => Incrementer

D Q0
 Internal Logic Count enable EN
C
• XOR complements each bit
• AND chain causes complement
D Q1
of a bit if all bits toward LSB
C
from it equal 1
 Count Enable
• Forces all outputs of AND D Q2
chain to 0 to “hold” the state C
 Carry Out
• Added as part of incrementer D Q3
• Connect to Count Enable of C
additional 4-bit counters to Carry

form larger counters output CO
Clock
(a) Logic Diagram-Serial Gating
Chapter 1 509
Synchronous Counters (continued)
Q0
EN
 Carry chain
• series of AND gates through which the Q1
carry “ripples” C1
• Yields long path delays
• Called serial gating
Q2
 Replace AND carry chain with ANDs => C2
in parallel
• Reduces path delays Q3
• Called parallel gating
CTR 4
C3
• Like carry lookahead EN Q0
• Lookahead can be used on COs Q1
Q2
and ENs to prevent long paths in Q3
large counters CO CO
 Symbol for Synchronous Counter Symbol Logic Diagram-Parallel Gating
Chapter 1 510
Other Counters
 See text for:

• Down Counter - counts downward instead of upward
• Up-Down Counter - counts up or down depending on value a
control input such as Up/Down
• Parallel Load Counter - Has parallel load of values available
depending on control input such as Load
 Divide-by-n (Modulo n) Counter
• Count is remainder of division by n; n may not be a
power of 2 or
• Count is arbitrary sequence of n states specifically
designed state-by-state
• Includes modulo 10 which is the BCD counter
Chapter 1 511
Counter with Parallel Load
 Add path for input data

Load
• enabled for Load = 1

Count
D 0 D Q 0
 Add logic to: C
• disable count logic for Load = 1

• disable feedback from outputs
for Load = 1 D 1 D Q 1
• enable count logic for Load = 0 C
and Count = 1
 The resulting function table:
D 2 D Q 2
Load Count Action C
0 0 Hold Stored Value

0 1 Count Up Stored Value D 3 D Q 3
1 X Load D C
Carry
Output CO
Clock
Chapter 1 512
Design Example: Synchronous BCD
 Use the sequential logic model to design a synchronous

BCD counter with D flip-flops
 State Table => Current State Next State
 Input combinations Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1
1010 through 1111 0 0 0 0 0 0 0 1
are don’t cares 0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
Chapter 1 513
Synchronous BCD (continued)
 Use K-Maps to two-level optimize the next state equations

and manipulate into forms containing XOR gates:
D1 = Q1
D2 = Q2 + Q1Q8
D4 = Q4 + Q1Q2
D8 = Q8 + (Q1Q8 + Q1Q2Q4)
 The logic diagram can be draw from these equations
• An asynchronous or synchronous reset should be added
 What happens if the counter is perturbed by a power
disturbance or other interference and it enters a state other
than 0000 through 1001?
Chapter 1 514
 Find the actual values of the six next states for the don’t
care combinations from the equations
 Find the overall state diagram to assess behavior for the
don’t care states (states in decimal)
0
Present State Next State
9 1
Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 14
1 0 1 0 1 0 1 1
8 2
1 0 1 1 0 1 1 0 15
12
1 1 0 0 1 1 0 1
1 1 0 1 0 1 0 0 7 11 13 3
1 1 1 0 1 1 1 1
6 10
4
1 1 1 1 0 0 1 0
5
Chapter 1 515
 For the BCD counter design, if an invalid state is entered,

return to a valid state occurs within two clock cycles
 Is this adequate? If not:
• Is a signal needed that indicates that an invalid state has been
entered? What is the equation for such a signal?
• Does the design need to be modified to return from an invalid state
to a valid state in one clock cycle?
• Does the design need to be modified to return from a invalid state
to a specific state (such as 0)?
 The action to be taken depends on:
• the application of the circuit
• design group policy
 See pages 244 of the text.
Chapter 1 516
Counting Modulo N
 The following techniques use an n-bit binary counter with

asynchronous or synchronous clear and/or parallel load:
• Detect a terminal count of N in a Modulo-N count sequence to
asynchronously Clear the count to 0 or asynchronously Load in value 0
(These lead to counts which are present for only a very short time and
can fail to work for some timing conditions!)
• Detect a terminal count of N - 1 in a Modulo-N count sequence to Clear
the count synchronously to 0
• Detect a terminal count of N - 1 in a Modulo-N count sequence to
synchronously Load in value 0
• Detect a terminal count and use Load to preset a count of the terminal
count value minus (N - 1)
 Alternatively, custom design a modulo N counter as done for
BCD
Chapter 1 517
Counting Modulo 7: Detect 7 and
Asynchronously Clear
 A synchronous 4-bit binary counter

with an asynchronous Clear is
used to make a Modulo D3 Q3
7 counter. D2 Q2
 Use the Clear feature to D1 Q1
detect the count 7 and D0 Q0
clear the count to 0. This Clock CP

gives a count of 0, 1, 2, 3, 4, 0 LOAD
5, 6, 7(short)0, 1, 2, 3, 4, 5, CLEAR
6, 7(short)0, etc.
 DON’T DO THIS! Existence of state 7 may not be long
enough to reliably reset all flip-flops to 0. Referred to as a
“suicide” counter! (Count “7” is “killed,” but the
designer’s job may be dead as well!)
Chapter 1 518
Counting Modulo 7: Synchronously Load on
Terminal Count of 6
 A synchronous 4-bit binary

0 D3 Q3
counter with a synchronous
0 D2 Q2
load and an asynchronous
0
clear is used to make a D1 Q1
Modulo 7 counter 0 D0 Q0
 Use the Load feature to Clock CP
detect the count "6" and

LOAD
Reset CLEAR
load in "zero". This gives
a count of 0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 0, ...
 Using don’t cares for states
above 0110, detection of 6 can be done with
Load = Q4 Q2
Chapter 1 519
Counting Modulo 6: Synchronously Preset 9 on
Reset and Load 9 on Terminal Count 14
 A synchronous, 4-bit binary

counter with a synchronous 1 D3 Q3
Load is to be used to make a 0 D2 Q2
Modulo 6 counter. 0 D1 Q1
 Use the Load feature to 1 D0 Q0
preset the count to 9 on Clock CP

Reset and detection of Reset LOAD
count 14. CLEAR
1
 This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12,
13, 14, 9, …
 If the terminal count is 15 detection is usually built in as
Carry Out (CO)
Chapter 1 520
Register Cell Design
 Assume that a register consists of identical cells

 Then register design can be approached as
follows:
• Design representative cell for the register
• Connect copies of the cell together to form the register
• Applying appropriate “boundary conditions” to cells
that need to be different and contract if appropriate
 Register cell design is the first step of the above
process
Chapter 1 521
Register Cell Specifications
 A register
 Data inputs to the register
 Control input combinations to the register
• Example 1: Not encoded
 Control inputs: Load, Shift, Add
 At most, one of Load, Shift, Add is 1 for any clock cycle
(0,0,0), (1,0,0), (0,1,0), (0,0,1)
• Example 2: Encoded
 Control inputs: S1, S0
 All possible binary combinations on S1, S0
(0,0), (0,1), (1,0), (1,1)
Chapter 1 522
Register Cell Specifications
 A set of register functions (typically specified as

register transfers)
• Example:
Load: A ← B
Shift: A ← sr B
Add: A ← A + B
 A hold state specification
• Example:
 Control inputs: Load, Shift, Add
 If all control inputs are 0, hold the current register state
Chapter 1 523
Multiplexer Approach
 Uses an n-input multiplexer with a variety of transfer

sources and functions
K0
.
.
.
K n2 1
...
Dedicated 4
logic 0 Encoder
. ...
.
. Sm S0 Load
. .
Dedicated 4 . .
logic k 2 1 . . MUX
k2 1 4
4 R0
k
. .
. Registers or . .
. . .
. shared logic 4
n2 1
Chapter 1 524
Multiplexer Approach
 Load enable by OR of control signals K0, K1, … Kn-1

- assumes no load for 00…0
 Use:
• Encoder + Multiplexer (shown) or
• n x 2 AND-OR
to select sources and/or K0
.
.
.
transfer functions K n2 1
...
Dedicated 4
logic 0 Encoder
. ...
.
. Sm S0 Load
. .
Dedicated 4 . .
logic k 2 1 . . MUX
k2 1 4
4 R0
k
. .
. Registers or . .
. . .
. shared logic 4
n2 1
Chapter 1 525
Example 1: Register Cell Design
 Register A (m-bits) Specification:

• Data input: B
• Control inputs (CX, CY)
• Control input combinations (0,0), (0,1) (1,0)
• Register transfers:
• CX: A ← B v A
• CY :A ← B + A
• Hold state: (0,0)
Chapter 1 526
Example 1: Register Cell Design (continued)
 Load Control
Load = CX + CY
 Since all control combinations appear as if
encoded (0,0), (0,1), (1,0) can use multiplexer
without encoder:
S1 = CX
S0 = CY
D0 = Ai Hold A
D1 = Ai ← Bi + Ai CY = 1
D2 = Ai ← Bi v Ai CX = 1
 Note that the decoder part of the 3-input
multiplexer can be shared between bits if desired
Chapter 1 527
Sequential Circuit Design Approach
 Find a state diagram or state table

• Note that there are only two states with the state
assignment equal to the register cell output value
 Use the design procedure in Chapter 5 to
complete the cell design
 For optimization:
• Use K-maps for up to 4 to 6 variables
• Otherwise, use computer-aided or manual
optimization
Chapter 1 528
Example 1 Again
 State Table:
Hold Ai v Bi Ai + Bi
CX = 0 CX = 1 CX = 1 CY = 1 CY = 1
Ai CY = 0 Bi = 0 Bi = 1 Bi = 0 Bi = 1
0 0 0 1 0 1
1 1 1 1 1 0
• Four variables give a total of 16 state table entries
• By using:
 Combinations of variable names and values
 Don’t care conditions (for CX = CY = 1)
only 8 entries are required to represent the 16 entries
Chapter 1 529
Example 1 Again (continued)
 K-map - Use variable ordering CX, CY, Ai Bi and assume a

D flip-flop
Di Ai
0 0 1 1
0 1 0 1
CY
X X X X
CX
0 1 1 1
Bi
Chapter 1 530
Example 1 Again (continued)
 The resulting SOP equation:

Di = CX Bi + CY Ai Bi + Ai Bi + CY Ai
 Using factoring and DeMorgan’s law:
Di = CX Bi + Ai (CY Bi) + Ai(CY Bi )
Di = CX Bi + Ai + (CY Bi)
The gate input cost per cell = 2 + 8 + 2 + 2 = 14
 The gate input cost per cell for the previous version
is:
Per cell: 19
Shared decoder logic: 8
 Cost gain by sequential design > 5 per cell
 Also, no Enable on the flip-flop makes it cost less
Chapter 1 531
Multiplexer and Bus-Based Transfers for
Multiple Registers
 Multiplexer dedicated to each register

 Shared transfer paths for registers
• A shared transfer object is a called a bus
(Plural: buses)
 Bus implementation using:
• multiplexers
• three-state nodes and drivers
 In most cases, the number of bits is the
length of the receiving register
Chapter 1 532
Dedicated MUX-Based Transfers
 Multiplexer connected
S0 L0
to each register input n

0
S
MUX
n
Load
produces a very flexible

n
1 R0
transfer structure =>

 Characterize the
S1 L1
simultaneous transfers n
0
S
MUX
n
Load
possible with this

n
1 R1
structure.
S2 L2
n S n
Load
0
n MUX
1 R2
Chapter 1 533
Multiplexer Bus
 A single bus driven by a

L0
Load
multiplexer lowers cost,

n
R0
but limits the available

transfers => S1 S0
L1
 Characterize the n
0
S1 S0
1
MUX
n n
Load
possible with this

n
2 R1
structure.
 Characterize the cost L2
savings compared to n
Load
dedicated multiplexers R2
Chapter 1 534
Three-State Bus
 The 3-input MUX can be L0
replaced by a 3-state node Load

n
(bus) and 3-state buffers. R0
n
 Cost is further reduced, but

transfers are limited E0
L1
 Characterize the
Load
possible with this structure. n R1
 Characterize the cost

savings and compare E1
L2
 Other advantages? Load

n
n R2
E2
Chapter 1 535
Serial Transfers and Microoperations
 Serial Transfers
• Used for “narrow” transfer paths
• Example 1: Telephone or cable line
 Parallel-to-Serial conversion at source
 Serial-to-Parallel conversion at destination
• Example 2: Initialization and Capture of the contents of
many flip-flops for test purposes
 Add shift function to all flip-flops and form large shift register
 Use shifting for simultaneous Initialization and Capture operations
 Serial microoperations
• Example 1: Addition
• Example 2: Error-Correction for CDs
Chapter 1 536
Serial Microoperations
 By using two shift registers for operands, a full adder, and a flip
flop (for the carry), we can add two numbers serially, starting at
the least significant bit.
 Serial addition is a low cost way to add large numbers of
operands, since a “tree” of full adder cells can be made to any
depth, and each new level doubles the number of operands.
 Other operations can be performed serially as well, such as
parity generation/checking or more complex error-check codes.
 Shifting a binary number left is equivalent to multiplying by 2.
 Shifting a binary number right is equivalent to dividing by 2.
Chapter 1 537
Serial Adder
 The circuit shown uses two shift Load/Right Shift Registers
registers for operands A(3:0) Serial
and B(3:0). In A
 A full adder, and one more B

FA
flip flop (for the carry) is used A3 A2 A1 A0
Parallel Load
Sum
to compute the sum. Serial

Cin
Cout
 The result is stored in the In
A register and the final

carry in the flip-flop B3 B2 B1 B0
Parallel Load
Q D
CP
 With the operands and the

(Clock and Load/Shift
Control not shown)
result in shift registers, a tree of full adders can be

used to add a large number of operands. Used as a common
digital signal processing technique.
Chapter 1 538
Terms of Use
Education, Inc.
Chapter 1 539
Part 3 – Control of Register Transfers
Charles Kime& Mano

Overview
 Part 1 – Registers, Microoperations and

Implementations
 Part 2 – Counters, Register Cells, Buses, & Serial
Operations
• Introduction to register transfer systems
• Register transfer system design procedure
• A design example
• Microprogrammed control
Chapter 1 541
Introduction to Register Transfer Systems
 Datapath and Control Unit

Control signals
Control Control Status signals

D atapath
inputs unit
D ata
outputs
Control D ata
outputs inputs
• Set of registers, mostly in Datapath with some in

Control Unit
• Register transfers performed on registers
• Control that supervises the sequencing of the register
Chapter 1 542
Programmable and Non-Programmable
Systems
 Programmable System – a portion of the input

consists of a sequence of instructions called a
program, typically stored in a memory and
addressed by a program counter. The Control Unit
is responsible for fetching and executing these
instructions.
 Non-programmable System – the control unit does
not deal with fetching and executing instructions,
but contains all of the information for sequencing
register transfers based on inputs and on status bits
from the datapath.
 Only non-programmable designs are considered
here.
Chapter 1 543
Register Transfer System Design Procedure
 Write a detailed system specification

 Determine all data, control and status input signals, all data, control and
status output signals, and registers of the datapath and control unit.
 Find a state machine diagram for the system including register transfers for
the datapath and control unit as outputs.
 Determine all internal control and status signals. Use these signals to
separate output conditions and actions, including register transfers, from
the state machine diagram flow and represent them in tabular form.
 Draw a block diagram of the datapath including all control and status
inputs and outputs. Draw a block diagram of the control if it includes
register transfer hardware.
 Design any specialized register transfer logic as needed for the datapath
and the control.
 Design the control unit logic.
 Verify the correct operation of the combined datapath and control unit. If
verification fails, debug the system and verify the changed system.
Chapter 1 544
Design Example – DASHWATCH - Specs
 Very Inexpensive Stop Watch for “dash” runners

 Times intervals to at most 99.99 seconds
 Stopwatch action plus storage of best performance
time per session (session ended by turning off
power or pushing RESET)
 Inputs START, STOP, CSS (compare and store
shortest), RESET
 Registers: 4-digit BCD Counter and 16-bit Parallel
Load Register
 Output: 4 digit BCD LCD with decimal point
Chapter 1 545
DASHWATCH Inputs, Outputs, and Registers
TA BLE 7-15
Inputs, Outputs, and Registers of the D ashWatch
Symbol Function Type
START Initialize timer to 0 and start timer Control input

STO P Stop timer and display timer Control input
CSS Compare, store and display shortest dash time Control input
R E SE T Set shortest value to 10011001 Control input
B1 D igit 1 data vector a, b, c, d, e, f, g to display D ata output vector
B0 D igit 0 data vector a, b, c, d, e, f, g to display D ata output vector
DP D ecimal point to display (= 1) D ata output
B -1 D igit –1 data vector a, b, c, d, e, f, g to display D ata output vector
B -2 D igit –2 data vector a, b, c, d, e, f, g to display D ata output vector
B The 29-bit display input vector (B1, B 0, DP, B–1, B –2) D ata output vector
TM 4-D igit BCD counter 16-Bit register

SP
SD
Parallel load register 16-Bit
Chapter 1 546
DASHWATCH State Machine Diagram with
Register Transfer Outputs
R ESE T
S1 SD (9999) BCD
STA RT S2 TM (0000) BCD
STA RT
STO P S3 TM (TM 1 1) BCD , D IS 5 TM
CSS?STA RT STO P
CSS?STA RT S4 D IS = TM
CSS
S5
TM > SD TM , SD
STA RT
S7 S6 SD TM
STA RT D IS 5 SD
Chapter 1 547
State Machine Diagram Design
 Specify only Moore outputs (no particular reason)

 S1: Reset state - in this state, initialize SD to 1001100110011001
(99.99), the maximum possible dash time.
 S2: Because of Moore output spec, S1 cannot be used for this state
since SD is not to be initialized again to 99.99 after having passed
through states S4 or S7. TM is initialized to (0000)BCD for next dash.
 S3: State during dash. Entered with START and exited with STOP.
While in state, 1 (0.01 seconds) is added to TM for each clock pulse.
(Clock frequency is 100 Hz), and DIS shows TM value.
 S4: Decision state whether to Compare, Store, and display Shortest
dash time, or to continue to display TM. Also START begins new
dash.
 S5: State for comparison of TM to SD.
 S6: State for loading TM into SD if TM is smaller.
 S7: State for START to begin new dash and display of SD as shortest
dash time.
Chapter 1 548
DASHWATCH Output Control/Status Table
TA BLE 7-16
D atapath Output A ctions and Status Generation with Control and Status Signals
Control or
Status
Action or Status Signals Meaning for Values 1 and 0
TM ← (0000) BCD R STM 1: R eset TM to 0 (synchronous reset)

0: No reset of TM
TM ← (TM + 1) BCD E NTM 1: BCD count up TM by 1, 0: hold TM value
SD ← (9999) BCD U PDATE 0: Select 1001100110011001 for loading SD

LSR 1: E nable load SD, 0: disable load SD
SD ← TM U PDATE 1: Select TM for loading SD
LSR Same as above
D IS = TM DS 0: Select TM for D IS
D IS = SD 1: Select SD for D IS
TM < SD A LTB 1: TM less than SD

TM ≥SD 0: TM greater than or equal to
Chapter 1 549
Determination of Internal Control/Status
Signals
 TM – Timer
• Reset to 0000: RSTM
• Enable to Count Up: ENTM
 SD – Shortest Dash
• Load SD: LSR = 1;
• Select input 9999: UPDATE = 0
• Select input TM: UPDATE = 1
 DIS – Display (B1, B0, DP, B– 1, B– 2)
• Select input TM: DS = 0
• Select input SD: DS = 1
 Compare TM and SD (Status)
• TM < SD: ALTB = 1
• TM ³ SD: ALTB = 0
Chapter 1 550
DASHWATCH Datapath
TM
C0 E NTM
4-Digit BCD Counter
R STM SR ST
A LTB A < B Comparator

D1 D0
SD DS S 16-Bit 2-to-1 MU X
LSR LOA D
Storage R egister DIS
R E SE T R E SE T D
4-D igit BCD -to-7
Segment Converter
16-Bit 2-to-1 MU X
U P DA TE S
D1 D0
4-D igit LCD D isplay
DP
Contracted 1001100110011001
Chapter 1 551
DASHWATCH – Datapath Development
 TM: 4-digit BCD Counter with Synchronous Reset

• Based on previous BCD adder digit design
• synchronous reset SRST added
• SRST = RSTM
• C0 (Incoming carry) = ENTM
 A < B Comparator
• Compares TM to SD
• Designed as left-to-right iterative cell array with output C0
 SD: Standard 16-bit parallel load register
• LOAD = LSR
• Contracted standard 2-way, 16-bit multiplexer used to select
between 9999BCD and TM as parallel load input D
• S = UPDATE
Chapter 1 552
DASHWATCH – Datapath Development –
Display Logic
 2-way 16-bit multiplexer

• Selects between TM and SD
• S = DS
 4-digit BCD-to-7 Segment Converter
• Uses previous design
 4-digit 7-Segment Display with Decimal Point
• 2-digit fractional part
• Decimal Point control = DP
• DP = 1
Chapter 1 553
DASHWATCH – SMD with Control Signal
Outputs Replacing Register Transfers
S1 LSR
R E SE T
STA RT S2 R STM
STA RT
STO P S3 E NTM
CSS?STA RT STO P
CSS?STA RT S4
CSS
S5
A LTB A LTB
STA RT S7 S6 U P DA TE ,LSR
STA RT
DS
(b) Chapter 1 554
DASHWATCH – FF Input Equations
 One-Hot State Assignment – 7 bits

 State S1 entered only by using asynchronous RESET
D S1 S1( t 1) 0
D S2 S2( t 1) S1 S2 ST A R T S4 CSS ST A R T S7 ST A R T
D S3 S3( t 1) S2 ST A R T S3 ST O P
D S4 S4( t 1) S3 ST O P S4 CSS ST A R T
D S5 S5( t 1) S4 CSS
D S6 S5 A L T B
D S7 S7( t 1) S5 A L T
Chapter 1 555
DASHWATCH – Output Equations
L SR = S1 + S6
R ST M = S2
E N T M = S3
UPDAT E = S6
DS =
Chapter 1 556
Microprogrammed Control
 Microprogrammed Control — a control unit with binary

control values stored as words in memory.
 Microinstructions — words in the control memory.
 Microprogram — a sequence of microinstructions.
 Control Memory — RAM or ROM memory holding the
microinstructions.
 Writeable Control Memory — RAM Memory into which
microinstructions may be written
Chapter 1 557
Microprogrammed Control (continued)
Control
inputs Status signals from datapath
Next-address
generator
Sequencer
Control address
register
Control address
Address
Control
memory
(R OM)
Data
Control data register

(optional)
Microinstruction
Next-address Control Control signals

information outputs to datapath
Chapter 1 558
Terms of Use
Education, Inc.
Chapter 1 559
Chapter 8 – Memory Basics
Charles Kime & Mano

Overview
 Memory definitions
 Random Access Memory (RAM)
 Static RAM (SRAM) integrated circuits
• Cells and slices
• Cell arrays and coincident selection
 Arrays of SRAM integrated circuits
 Dynamic RAM (DRAM) integrated circuits
 DRAM Types
• Synchronous (SDRAM)
• Double-Data Rate (DDR SRAM)
• RAMBUS DRAM (RDRAM)
 Arrays of DRAM integrated circuits
Chapter 1 561
Memory Definitions
 Memory ─ A collection of storage cells together with the

necessary circuits to transfer information to and from
them.
 Memory Organization ─ the basic architectural structure of
a memory in terms of how data is accessed.
 Random Access Memory (RAM) ─ a memory organized
such that data can be transferred to or from any cell (or
collection of cells) in a time that is not dependent upon the
particular cell selected.
 Memory Address ─ A vector of bits that identifies a
particular memory element (or collection of elements).
Chapter 1 562
Memory Definitions (Continued)
 Typical data elements are:
• bit ─ a single binary digit
• byte ─ a collection of eight bits accessed together
• word ─ a collection of binary bits whose size is a
typical unit of access for the memory. It is typically a
power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4
bytes, 8 bytes, etc.)
 Memory Data ─ a bit or a collection of bits to be
stored into or accessed from memory cells.
 Memory Operations ─ operations on memory data
supported by the memory unit. Typically, read
and write operations over some data element (bit,
byte, word, etc.).
Chapter 1 563
Memory Organization
 Organized as an indexed array of words. Value of the index

for each word is the memory address.
 Often organized to fit the needs of a particular computer
architecture. Some historically significant computer
architectures and their associated memory organization:
• Digital Equipment Corporation PDP-8 – used a 12-bit address to
address 4096 12-bit words.
• IBM 360 – used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
• Intel 8080 – (8-bit predecessor to the 8086 and the current Intel
processors) used a 16-bit address to address 65,536 8-bit bytes.
Chapter 1 564
Memory Block Diagram
 A basic memory system is n Data Input Lines
shown here: n
 k address lines are decoded Memory

to address 2k words of k Address Lines
k
Unit
k
memory. 2 Words
n Bits per Word
1
 Each word is n bits. Read
 Read and Write are single

1
Write
control lines defining the

n
simplest of memory
operations. n Data Output Lines
Chapter 1 565
Memory Organization Example
 Example memory
contents: Memory Address Memory
• A memory with 3 Binary Decimal Content
address bits & 8 data 000 0 10001111
bits has: 001 1 11111111
• k = 3 and n = 8 so 23 010 2 10110001
= 8 addresses labeled 011 3 00000000
0 to 7. 100 4 10111001
• 23 = 8 words of 8-bit 1
101
10
5
6
10000110
00110011
data 111 7 11001100
Chapter 1 566
Basic Memory Operations
 Memory operations require the following:

• Data ─ data written to, or read from, memory as
required by the operation.
• Address ─ specifies the memory location to operate on.
The address lines carry this information into the
memory. Typically: n bits specify locations of 2n
words.
• An operation ─ Information sent to the memory and
interpreted as control information which specifies the
type of operation to be performed. Typical operations
are READ and WRITE. Others are READ followed by
WRITE and a variety of operations associated with
delivering blocks of data. Operation signals may also
specify timing info.
Chapter 1 567
Basic Memory Operations (continued)
 Read Memory ─ an operation that reads a data value
stored in memory:
• Place a valid address on the address lines.
• Wait for the read data to become stable.
 Write Memory ─ an operation that writes a data value to
memory:
• Place a valid address on the address lines and valid data on the
data lines.
• Toggle the memory write control line
 Sometimes the read or write enable line is defined as a
clock with precise timing information (e.g. Read Clock,
Write Strobe).
• Otherwise, it is just an interface signal.
• Sometimes memory must acknowledge that it has completed the
operation.
Chapter 1 568
Memory Operation Timing
 Most basic memories are asynchronous

• Storage in latches or storage of electrical charge
• No clock
 Controlled by control inputs and address
 Timing of signal changes and data observation is critical to the operation
 Read timing:
20 ns
Clock T1 T2 T3 T4 T1
Address Address valid
Memory
enable
Read/
Write
Data Data valid

output
65 ns
Read cycle
Chapter 1 569
Memory Operation Timing
 Write timing:
20 ns
Address Address valid
Memory
enable
Read/
Write
Data
input Data valid
75 ns
 Critical times measured with respect to edges of write pulse (1-0-1):

Write cycle
• Address must be established at least a specified time before 1-0 and held for
at least a specified time after 0-1 to avoid disturbing stored contents of other
addresses
• Data must be established at least a specified time before 0-1 and held for at
least a specified time after 0-1 to write correctly
Chapter 1 570
RAM Integrated Circuits
 Types of random access memory

• Static – information stored in latches
• Dynamic – information stored as electrical charges on
capacitors
 Charge “leaks” off
 Periodic refresh of charge required
 Dependence on Power Supply
• Volatile – loses stored information when power turned
off
• Non-volatile – retains information when power turned
off
Chapter 1 571
Static RAM  Cell
 Array of storage cells used to implement static RAM

 Storage Cell Select
• SR Latch
• Select input for
control B C
• Dual Rail Data

S Q
Inputs B and B
• Dual Rail Data B
R Q
C
Outputs C and C RAM cell
Chapter 1 572
Static RAM  Bit Slice
 Represents all circuitry that is required for 2n 1-bit

Select
words
Word
select
0
B C
• Multiple RAM cells S Q X
X
C Word
• Control Lines: B R Q
R A M cell
select
0
R A M cell
 Word select i Word

select
1
– one for each word Word Select R A M cell
select
 Re ad / Write 2n 2 1
Word
S Q X
 Bit Select select

2n 2 1
R A M cell
X
• Data Lines: R Q
RA M cell
R ead/Write
logic
 Data in D ata in
Q
 Data out D ata in
S
R ead/
Write
D ata out
Bit
select
R Q
(b) Symbol
Write logic
R ead logic D ata out
R ead/ Bit
Write select
(a) Logic diagram
Chapter 1 573
2n-Word  1-Bit RAM IC
 To build a RAM IC 4-to-16
3
Decoder 0
Word select
A A
from a RAM slice,

2 1
3 3
2 RAM cell
A A 2 3
we need:
2 2 2
A A 1 5
• Decoder  decodes 1 1 2
6 RAM cel l
A A 0 7
0 0 2
the n address lines to 16 x

RAM
1 8
2n word select lines Data Data

10
11
• A 3-state buffer  input output

12
13
• on the data output Read/

Write
14
15
permits RAM ICs to Memory

enable
RAM cell
be combined into a (a) Symbol

Read/Write
RAM with c  2n words

logic
Data input Data in

Data
Data out
output
Read/ Bit
Write select
Read/Write
Chip select
(b) Block diagram

Chapter 1 574
Cell Arrays and Coincident Selection
 Memory arrays can be very large =>

• Large decoders
• Large fanouts for the bit lines
• The decoder size and fanouts can be reduced by
approximately nby using a coincident selection in
a 2-dimensional array
• Uses two decoders, one for words and one for bits
• Word select becomes Row select
• Bit select becomes Column select
 See next slide for example
•A 3 and A2 used for Row select
•A 1 and A0 for Column select
Chapter 1 575
Cell Arrays and Coincident Selection
(continued)
Row decoder
2-to-4
Decoder 0
1
A 2
3
RAM cell RAM cell RAM cell RAM cell
0 1 2 3
A 20
2
1

Row
4 5 6 7
select

8 9 10 11

12 13 14 15
Read/Write Read/Write Read/Write Read/Write

logic logic logic logic
Data in Data in Data in Data in
Data out Data out Data out Data out
Read/ Bit Read/ Bit Read/ Bit Read/ Bit

Write select Write select Write select Write select
Data input
Read/Write
X X X X
Column select Data

output
0 1 2 3
Column 2-to-4 Decoder

decoder with enable
1 0
2 2 Enable
A A
1 0
Chip select Chapter 1 576
RAM ICs with > 1 Bit/Word
 Word length can be quite high.

 To better balance the number of words and
word length, use ICs with > 1 bit/word
 See Figure 8-8 for example
• 2 Data input bits
• 2 Data output bits
• Row select selects 4 rows
• Column select selects 2 pairs of columns
Chapter 1 577
Making Larger Memories
Data In
 Using the CS lines, we De c o de r
A1 D-In
can make larger A0
R/W
memories from smaller D3 CS D-Out
ones by tying all address, A1 D-In

data, and R/W lines in A0
R/W
parallel, and using the D2 CS D-Out
decoded higher order
A1 D-In
address bits to control A0
R/W
CS. D1 CS D-Out
 Using the 4-Word by 1- A1 D-In

Bit memory from before, A0
R/W
we construct a 16-Word A3 S 1 D0 CS D-Out
by A2 S0
Data Out
1-Bit memory.  A1
A0
R/W
Chapter 1 578
Making Wider Memories
 To construct wider Data In 3210
memories from narrow A1 D-In

A0
ones, we tie the address and R/W
CS D-Out
control lines in parallel and
keep the data lines separate. A1 D-In
 For example, to make a 4- A0
R/W
word by 4-bit memory from CS D-Out
4, 4-word by 1-bit memories A1 D-In

 A0
R/W
 Note: Both 16x1 and 4x4 CS D-Out
memories take 4-chips A1 A1 D-In

and hold 16 bits of data. A0 A0
R/W R/W
CS D-Out
CS
Data Out 3210
Chapter 1 579
Dynamic RAM (DRAM)
 Basic Principle: Storage of information on

capacitors.
 Charge and discharge of capacitor to change
stored value
 Use of transistor as “switch” to:
• Store charge
• Charge or discharge
 See next slide for circuit, hydraulic analogy,
and logical model.
Chapter 1 580
Dynamic RAM (continued)
Select
Stored 1 Stored 0
To Pump
T
B
C
DRAM cell
(b) (c)
(a)
Write 1 Write 0
Select
(d) (e)
B D Q C
Read 1 Read 0
C DRAM cell
model
(h) (f) (g)
Chapter 1 581
Dynamic RAM - Bit Slice
 C is driven by 3-state Word

select
0
Select
drivers B
D Q
C
 Sense amplifier is used C D R A M cell

model
Word
select
0
to change the small Word

D R A M cell
voltage change on C
select
1
Select D R A M cell
into H or L 2 1
 In the electronics, B, C,
D Q
2 1
C D R A M cell
and the sense amplifier model D R A M cell
R ead/Write
output are connected to logic
make destructive read

D ata in
Sense
amplifier D ata out
D ata in R ead/ Bit
into non-destructive
Write select
read
(b) Symbol
Write logic
Read logic D ata out
Bit
Read/
select
Write
(a) Logic diagram
Chapter 1 582
Dynamic RAM - Block Diagram
 Block Diagram – See Figure 8-14 in text

 Refresh Controller and Refresh Counter
 Read and Write Operations
• Application of row address
• Application of column address
• Why is the address split?
• Why is the row address applied first?
Chapter 1 583
Dynamic RAM Read Timing
20 ns
Row Column
Address
Address Address
RAS
CAS
Output
enable
Read/
Write
Data Hi-Z
Data valid
output
65 ns
Read cycle
Chapter 1 584
DRAM Types
 Types to be discussed
• Synchronous DRAM (SDRAM)
• Double Data Rate SDRAM (DDR SDRAM)
• RAMBUS® DRAM (RDRAM)
 Justification for effectiveness of these types
• DRAM often used as a part of a memory hierarchy (See details in
chapter 14)
• Reads from DRAM bring data into lower levels of the hierarchy
• Transfers from DRAM involve multiple consecutively addressed
words
• Many words are internally read within the DRAM ICs using a single
row address and captured within the memory
• This read involves a fairly long delay
Chapter 1 585
DRAM Types (continued)
 Justification for effectiveness of these types (continued)

• These words are then transferred out over the memory data bus
using a series of clocked transfers
• These transfers have a low delay, so several can be done in a short
time
• The column address is captured and used by a synchronous
counter within the DRAM to provide consecutive column
addresses for the transfers
 burst read – the resulting multiple word read from
consecutive addresses
Chapter 1 586
Synchronous DRAM
 Transfers to and from the DRAM are synchronize with a clock

 Synchronous registers appear on:
• Address input
• Data input
• Data output
 Column address counter
• for addressing internal data to be transferred on each clock cycle
• beginning with the column address counts up to column address + burst
size – 1
 Example: Memory data path width: 1 word = 4 bytes
Burst size: 8 words = 32 bytes
Memory clock frequency: 5 ns
Latency time (from application of row address until first word
available): 4 clock cycles
Read cycle time: (4 + 8) x 5 ns = 60 ns
Memory Bandwidth: 32/(60 x 10-9) = 533 Mbytes/sec
Chapter 1 587
Double Data Rate Synchronous DRAM
 Transfers data on both edges of the clock

 Provides a transfer rate of 2 data words per clock
cycle
 Example: Same as for synchronous DRAM
• Read cycle time = 60 ns
• Memory Bandwidth: (2 x 32)/(60 x 10 -9
) = 1.066
Mbytes/sec
Chapter 1 588
RAMBUS DRAM (RDRAM)
 Uses a packet-based bus for interaction between the RDRAM ICs and the
memory bus to the processor
 The bus consists of:
• A 3-bit row address bus
• A 5-bit column address bus
• A 16 or 18-bit (for error correction) data bus
 The bus is synchronous and transfers on both edges of the clock
 Packets are 4-clock cycles long giving 8 transfers per packet representing:
• A 12-bit row address packet
• A 20-bit column address packet
• A 128 or 144-bit data packet
 Multiple memory banks are used to permit concurrent memory accesses with
different row addresses
 The electronic design is sophisticated permitting very fast clock speeds
Chapter 1 589
Arrays of DRAM Integrated Circuits
 Similar to arrays of SRAM ICs, but there are

differences typically handled by an IC called a
DRAM controller:
• Separation of the address into row address and column
address and timing their application
• Providing RAS and CAS and timing their application
• Performing refresh operations at required intervals
• Providing status signals to the rest of the system (e.g.,
indicating whether or not the memory is active or is
busy performing refresh)
Chapter 1 590
Terms of Use
Education, Inc.
Chapter 1 591
Chapter 9 – Computer Design Basics
Part 1 – Datapaths
Charles Kime & Mano

Overview
 Part 1 – Datapaths
• Introduction
• Datapath Example
• Arithmetic Logic Unit (ALU)
• Shifter
• Datapath Representation and Control Word
 Part 2 – A Simple Computer
 Part 3 – Multiple Cycle Hardwired Control
Chapter 1 593
Introduction
 Computer Specification
• Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a
programmer at its lowest level
• Computer Architecture - a high-level
description of the hardware implementing the
computer derived from the ISA
• The architecture usually includes additional
specifications such as speed, cost, and
reliability.
Chapter 1 594
Introduction (continued)
 Simple computer architecture decomposed

into:
• Datapath for performing operations
• Control unit for controlling datapath operations
 A datapath is specified by:
• A set of registers
• The microoperations performed on the data
stored in the registers
• A control interface
Chapter 1 595
Datapaths
 Guiding principles for basic datapaths:

• The set of registers
 Collection of individual registers
 A set of registers with common access resources called a
register file
 A combination of the above
• Microoperation implementation
 One or more shared resources for implementing
microoperations
 Buses - shared transfer paths
 Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations
 Shifter - shared resource for implementing shift
microoperations
Chapter 1 596
Datapath Example
Load enable A select B select
 Four parallel-load Write

D data n
A address B address
registers Load
R0 2 2
 Two mux-based n n
register selectors
Load
R1
0
n 1
 Register destination n
0
2
3
MU X
decoder Load
R2
1
2
MU X
 Mux B for external

3
n n
constant input 0 1 2 3
Load R3
n n
n
 Buses A and B with external
Register file
D ecoder
D address A data B data
2 Constant in n n
address and data outputs D estination select n 1 0
MB select
 ALU and Shifter with

MU X B A ddress
Bus A n
n out
Bus B
D ata
Mux F for output select

A B n out
G select H select
4 A B 2 B
S2:0 || Cin S
 Mux D for external data input V

C
A rithmetic/logic
unit (A LU )
0 IR Shifter IL 0
G H
 Logic for generating status bits N

Z Z ero D etect
n n
0 1
V, C, N, Z MF select MU X F
F
Function unit
D ata in
n n
MD select 0 1
MU X D
n Bus D
Chapter 1 597
Datapath Example: Performing a
Microoperation
 Microoperation: R0 ← R1 + R2 Write
D data n
A address B address
 Apply 01 to A select to place Load

R0 2 2
n n
contents of R1 onto Bus A
 Apply 10 to B select to place Load
R1
0
n 1
contents of R2 onto B data and MU X
2
n
0 3
apply 0 to MB select to place 1
Load MU X
R2 2
B data on Bus B 3
 Apply 0010 to G select to perform addition G = Bus A + Bus
n n
Load R3
B n n
 Apply 0 to MF select and 0 to MD
0 1 2 3
D ecoder
n
Register file
D address A data B data

2 Constant in n n
select to place the value of G onto BUS D
D estination select n 1 0
MB select
MU X B A ddress
 Apply 00 to Destination select to enable the Load input to R0
Bus A
Bus B
n
n out
D ata
A B n out
G select H select
4 A B 2 B
 Apply 1 to Load Enable to force the Load input to R0 to 1 so that V

S2:0 || Cin
A rithmetic/logic 0
S
IR Shifter IL 0
C unit (A LU )
G H
R0 is loaded on the clock pulse (not shown) N n
n
Z Zero D etect
 The overall microoperation requires

MF select
0
MU X F
1
Function unit
F
n n D ata in
1 clock cycle 0 1
MD select
MU X D
n Bus D
Chapter 1 598
Datapath Example: Key Control Actions for
Microoperation Alternatives
 Perform a shift microoperation – Write
D data n
A address B address
apply 1 to MF select Load

R0 2 2
 Use a constant in a micro- n n
operation using Bus B – apply 1 to Load

R1
0
MB select n 1
2
MU X
n
3
 Provide an address and data for a Load
0
1
MU X
R2 2
memory or output write n n
3
microoperation – apply 0 to Load Load R3

n n
enable to prevent register loading 0 1 2 3
D ecoder
n
Register file
A data B data
 Provide an address and obtain data
D address
2 Constant in n n
D estination select n 1 0
for a memory or output read MB select
Bus A
MU X B
n A ddress
out
microoperation – apply 1 to MD A B
Bus B n
n
D ata
out
select
G select H select
4 A B 2 B
S2:0 || Cin S
V A rithmetic/logic 0 IR Shifter IL 0
 For some of the above, other C

N
unit (A LU )
G H
n
control signals become don't cares
n
Z Zero D etect
0 1
MF select MU X F Function unit
F
n n D ata in
MD select 0 1
MU X D
n Bus D
Chapter 1 599
Arithmetic Logic Unit (ALU)
 In this and the next section, we deal with detailed design of

typical ALUs and shifters
 Decompose the ALU into:
• An arithmetic circuit
• A logic circuit
• A selector to pick between the two circuits
 Arithmetic circuit design
• Decompose the arithmetic circuit into:
 An n-bit parallel adder
 A block of logic that selects four choices for the B input to the adder
 See next slide for diagram
Chapter 1 600
Arithmetic Circuit Design (continued)
 There are only four functions of B to select as Y in G = A + Y:

Cin = 0 Cin = 1
•
0 G=A G=A+1
•
B G =A+ B G =A+ B + 1
•
B G =A+ B G =A+ B + 1
•
1 G =A– 1 G=A
 What functions are implemented with carry-in to the adder = 0? =1?
C in
n
A X
n n-bit n
B parallel G X Y C in
add
B input n
Y
S0 logic
S1
C out
Chapter 1 601
Arithmetic Circuit Design (continued)
 Adding selection codes to the functions of B:

TA BLE 9-1
Function Table for A rithmetic Circuit +
Select Input G = (A +1 Y+1 Cin )
S1 S0 Y Cin =0 Cin =1
0 0 all 0s G A (transfer) G A 1 (increment)

+
0 1 B G A B (add) G A B 1
+ +
1 0 B G A B G A B 1 (subtract)
1 1 all 1s G A 1 (decrement) (transfer)
 The useful arithmetic functions are labeled in the table
 Note that all four functions of B produce at least one
useful function
Chapter 1 602
Logic Circuit
 The text gives a circuit implemented using a multiplexer

plus gates implementing: AND, OR, XOR and NOT
 Here we custom design a circuit for bit Gi by beginning with
a truth table organized as a K-map and assigning (S1, S0)
codes to AND, OR, etc.
 Gi = S0 Ai Bi + S1 Ai Bi S1S0 AND OR XOR NOT
+ S0 Ai Bi + S1 S0 Ai A B 00 01 11 10
i i
 Gate input count for
00 0 0 0 1
MUX solution > 29
 Gate input count for 01 0 1 1 1
above circuit < 20 11 1 1 0 0
 Custom design better
10 0 1 1 0
Chapter 1 603
Arithmetic Logic Unit (ALU)
 The custom circuit has interchanged the (S1,S0) codes for XOR and NOT
compared to the MUX circuit. To preserve compatibility with the text, we
use the MUX solution.
 Next, use the arithmetic circuit, the logic circuit, and a 2-way multiplexer to
form the ALU. See the next slide for the bit slice diagram.
 The input connections to the arithmetic circuit and logic circuit have been
been assigned to prepare for seamless addition of the shifter, keeping the
selection codes for the combined ALU and the shifter at 4 bits:
• Carry-in Ci and Carry-out Ci+1 go between bits
• Ai and Bi are connected to both units
• A new signal S2 performs the arithmetic/logic selection
• The select signal entering the LSB of the arithmetic circuit, Cin, is
connected to the least significant selection input for the logic circuit, S0.
Chapter 1 604
Arithmetic Logic Unit (ALU) (continued)
C0 5
Ci Ci Ci 1 1
Ai Ai
O ne stage of
Bi Bi arithmetic
circuit 2-to-1
S0 S0
0 MU X
S1 S1
Gi
1
Ai S
B i O ne stage of
C in S logic circuit
0
S1
S2
 The next most significant select signals, S0 for the arithmetic circuit and S1
for the logic circuit, are wired together, completing the two select signals
for the logic circuit.
 The remaining S1 completes the three select signals for the arithmetic
circuit.
Chapter 1 605
Combinational Shifter Parameters
 Direction: Left, Right

 Number of positions with examples:
• Single bit:
 1 position
 0 and 1 positions
• Multiple bit:
 1 to n – 1 positions
 0 to n – 1 positions
 Filling of vacant positions
• Many options depending on instruction set
• Here, will provide input lines or zero fill
Chapter 1 606
4-Bit Basic Left/Right Shifter
B 3 B 2 B 1 B 0
Serial
output L
Serial
output R
IR IL
0 1 2 M 0 1 2 M 0 1 2 M 0 1 2 M
S U S U S U S U
X X X X
2
S
 Serial Inputs:
H 3 H 2 H 1 H 0
• IR for right shift  Shift Functions:

• IL for left shift
(S1, S0) = 00 Pass B unchanged
 Serial Outputs 01 Right shift
• R for right shift (Same as MSB input)
10 Left shift
• L for left shift (Same as LSB input)
11 Unused
Chapter 1 607
Barrel Shifter
D3 D2 D1 D0
S0
S1
3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0
M M M M
U U U U
X X X X
 A rotate is a shift
Y
in which theY bits shifted outY are inserted into
3 2 Y
the positions 1 0
vacated
 The circuit rotates its contents left from 0 to 3 positions depending on S:
S = 00 position unchanged S = 10 rotate left by 2 positions
S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
 See Table 10-3 in text for details
Chapter 1 608
Barrel Shifter (continued)
 Large barrel shifters can be constructed by

using:
• Layers of multiplexers - Example 64-bit:
 Layer 1 shifts by 0, 16, 32, 48
 Layer 2 shifts by 0, 4, 8, 12
 Layer 3 shifts by 0, 1, 2, 3
 See example in section 12-2 of the text
• 2 - dimensional array circuits designed at the
electronic level
Chapter 1 609
Datapath Representation
 Have looked at detailed design of n
ALU and shifter in the datapath Write

D data
in slide 8 m
D address
m
 Here we move up one level in the 2 x n

Register file
hierarchy from that datapath m

A address B address
m
 The registers, and the multiplexer, A data B data
Constant in
decoder, and enable hardware for n
n n
accessing them become a register MB select

1
MUX B
0
file Bus A n
Address out
 The ALU, shifter, Mux F and Bus B n
Data out
status hardware become a function 4 A B

FS
unit V
 The remaining muxes and buses

Function
C
unit
N
which handle data transfers are at Z

F
the new level of the hierarchy n
n
Data in
0 1
MD select
MUX D
Chapter 1 610
Datapath Representation (continued)
 In the register file: n
• Multiplexer select inputs become D data
A address and B address m

Write
D address
• Decoder input becomes D address 2

m
x n
• Multiplexer outputs become A data m

A address
Register file
B address
m
and B data
A data B data
• Input data to the registers becomes Constant in
n n
D data n
• Load enable becomes write MB select

1
MUX B
0
 The register file now appears like a Bus A n

Address out
Bus B n
memory based on clocked flip- Data out
flops (the clock is not shown) FS

4 A B
 The function unit labeling is quite V

Function
C
straightforward except for FS N

unit
Z
F
n
n Data in
0 1
MD select
MUX D
Chapter 1 611
Definition of Function Unit Select (FS) Codes
G Select, H Select, and MF
in T of FS Codes
MF G H
FS(3:0) Select Select(3:0) Select(3:0) Micr ooperation
0000 0 0000 XX F ¬ A Boolean

0001 0 0001 XX F ¬A + 1
0010 0 0010 XX F ¬A + B
Equations:
0011 0 0011 XX F ¬A + B + 1
MFS = F3 F2
0100 0 0100 XX F ¬A + B
0101 0 0101 XX F ¬A + B + 1 GSi = Fi

0110 0 0110 XX F ¬A - 1
0111 0 0111 XX F ¬ A
HSi = Fi
1000 0 1 X 00 XX F ¬ A ÙB
1001 0 1 X 01 XX F ¬ A ÚB
1010 0 1 X 10 XX F ¬ A ÅB
1011 0 1 X 11 XX F ¬ A
1100 1 XXXX 00 F ¬ B
1101 1 XXXX 01 F ¬ sr B
1110 1 XXXX 10 F ¬ sl B
Chapter 1 612
The Control Word
 The datapath has many control inputs

 The signals driving these inputs can be defined
and organized into a control word
 To execute a microinstruction, we apply control
word values for a clock cycle. For most
microoperations, the positive edge of the clock
cycle is needed to perform the register load
 The datapath control word format and the field
definitions are shown on the next slide
Chapter 1 613
The Control Word Fields
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M M R
DA AA BA FS
B D W
 Fields Control word
• DA – D Address
• AA – A Address
• BA – B Address
• MB – Mux B
• FS – Function Select
• MD – Mux D
• RW – Register Write
 The connections to datapath are shown in the next slide
Chapter 1 614
Control Word Block Diagram
n
R W 0 Write D data
15
D A 14 D address
13 8 x n
Register file
12 9
AA 11 A address B address 8 BA
10 7
A data B data
n n
n
Constant in
1 0
MB 6 MUX B
Bus A n
Address out
Bus B n
Data out
A B
V
5
C Function
4
FS
unit
N 3
Z 2
n
n
Data in
0 1
MD 1 MUX D
Bus D
Chapter 1 615
Control Word Encoding
Encoding of Control W
D A, AA, B A MB FS MD R W
Function Code Function Code Function Code Function Code Function Code
R 0 000 Register 0 F ¬ A 0000 Function 0 No write 0
R 1 001 Constant 1 F ¬A + 1 0001 Data In 1 Write 1
R 2 010 F ¬A + B 0010
R 3 011 F ¬A + B + 1 0011
R 4 100 F ¬A + B 0100
R 5 101 F ¬A + B + 1 0101
R 6 110 F ¬A - 1 0110
R 7 111 F ¬A 0111
F ¬A Ù B 1000
F ¬A Ú B 1001
F ¬A Å B 1010
F ¬ 1011
A
F ¬B 1100
F ¬ sr B 1101
F ¬ sl B 1110
Chapter 1 616
Microoperations for the Datapath - Symbolic
Representation
Micr o-
op eratio n D A A A B A M B F S M D R W
R 1 ¬ R 2 – R 3 R 1 R 2 R 3 R e g ister F =A + B+ 1 F unction Write
R 4 ¬ s l R6 R 4 — R 6 R e g ister F = sl B F unction Write
R 7 ¬ R 7 +1 R 7 R 7 — Re gister F =A + 1 Function Write
R 1 ¬ R 0 +2 R 1 R 0 — Con s tant F =A + B Func tio n Write
Data out ¬ R 3 —— R 3 R eg i s t e r — — N o Wr it e
R 4 ¬ D ata in R 4 —— — — Data in Write
R 5¬ 0 R 5 R 0 R 0 R e g ister F =A Å B F unction Write
Chapter 1 617
Microoperations for the Datapath -
Binary Representation
m Microoperations from T a Binary C o o
Micr o-
o p eratio n D A A A B A M B F S M D R W
R 1 ¬ R 2 – R 3 001 010 011 0 010 1 0 1
R 4 ¬ s l R6 10 0 XX X 110 0 111 0 0 1
R 7 ¬ R 7+1 11 1 1 11 XXX 0 000 1 0 1
R 1 ¬ R 0+2 00 1 0 00 XXX 1 001 0 0 1
Data out ¬ R 3 XX X X XX 011 0 XXX X X 0
R 4 ¬ D ata in 10 0 XX X XXX X XXX X 1 1
R 5¬0 101 000 000 0 101 0 0 1
 Results of simulation of the above on the

next slide
Chapter 1 618
Datapath Simulation
Clock 1 2 3 4 5 6 7 8
DA 1 4 7 1 0 4 5
AA 2 0 7 0
BA 3 6 0 3 0
FS 5 14 1 2 0 10
Constant_in X 2 X
MB
A ddress_out 2 0 7 0
D ata_out 3 6 0 2 3 0
D ata_in 18 18
MD
RW
reg0 0
reg1 1 255 2
reg2 2
reg3 3
reg4 4 12 18
reg5 5 0
reg6 6
reg7 7 8
Status_bits 2 0 0 1 X
Chapter 1 619
Terms of Use
Education, Inc.
Chapter 1 620
Part 2 – A Simple Computer
Charles Kime & Mano

Overview
• Instruction Set Architecture (ISA)
• Single-Cycle Hardwired Control
 PC Function
 Instruction Decoder
 Example Instruction Execution
 Part 3 – Multiple Cycle Hardwired
Control
Chapter 1 622
Instruction Set Architecture (ISA) for Simple
Computer (SC)
 A programmable system uses a sequence of instructions to
control its operation
 An typical instruction specifies:
• Operation to be performed
• Operands to use, and
• Where to place the result, or
• Which instruction to execute next
 Instructions are stored in RAM or ROM as a program
 The addresses for instructions in a computer are provided
by a program counter (PC) that can
• Count up
• Load a new address based on an instruction and, optionally, status
information
Chapter 1 623
Instruction Set Architecture (ISA) (continued)
 The PC and associated control logic are part of the

Control Unit
 Executing an instruction - activating the necessary
sequence of operations specified by the instruction
 Execution is controlled by the control unit and
performed:
• In the datapath
• In the control unit
• In external hardware such as memory or input/output
Chapter 1 624
ISA: Storage Resources
 The storage resources are "visible" to the programmer at the lowest

software level (typically, machine or assembly language)
 Storage resources
for the SC => Program counter
(PC)
 Separate instruction and
Instruction
data memories imply memory
"Harvard architecture" 2
15
x 16
 Done to permit use of

single clock cycle per Register file
instruction implementation 8 x 16
 Due to use of "cache" in

modern computer
architectures, is a fairly Data
memory
realistic model 2
15
x 16
Chapter 1 625
ISA: Instruction Format
 A instruction consists of a bit vector

 The fields of an instruction are subvectors
representing specific functions and having specific
binary codes defined
 The format of an instruction defines the
subvectors and their function
 An ISA usually contains multiple formats
 The SC ISA contains the three formats presented
on the next slide
Chapter 1 626
ISA: Instruction Format
15 9 8 6 5 3 2 0
Destination Source reg- Source reg-

Opcode
register (DR) ister A (SA) ister B (SB)
(a) Register
15 9 8 6 5 3 2 0
Destination Source reg-

Opcode Operand (OP)
register (DR) ister A (SA)
(b) Immediate
15 9 8 6 5 3 2 0
Address (AD) Source reg- Address (AD)

Opcode (Left) (Right)
ister A (SA)
(c) Jump and Branch
 The three formats are: Register, Immediate, and Jump and Branch
 All formats contain an Opcode field in bits 9 through 15.
 The Opcode specifies the operation to be performed
 More details on each format are provided on the next three slides
Chapter 1 627
ISA: Instruction Format (continued)
15 9 8 6 5 3 2 0
Destination Source reg- Source reg-

Opcode
register (DR) ister A (SA) ister B (SB)
(a) Register
 This format supports instructions represented by:
• R1 ← R2 + R3
• R1 ← sl R2
 There are three 3-bit register fields:
• DR - specifies destination register (R1 in the examples)
• SA - specifies the A source register (R2 in the first example)
• SB - specifies the B source register (R3 in the first example and
R2 in the second example)
 Why is R2 in the second example SB instead of SA?
• The source for the shifter in our datapath to be used in
implementation is Bus B rather than Bus A
Chapter 1 628
15 9 8 6 5 3 2 0
Destination Source reg-

Opcode Operand (OP)
register (DR) ister A (SA)
(b) Immediate
 This format supports instructions described by:
• R1 ← R2 + 3
 The B Source Register field is replaced by an Operand
field OP which specifies a constant.
 The Operand:
• 3-bit constant
• Values from 0 to 7
 The constant:
• Zero-fill (on the left of) the Operand to form 16-bit constant
• 16-bit representation for values 0 through 7
Chapter 1 629
15 9 8 6 5 3 2 0
Address (AD) Source reg- Address (AD)

Opcode
(Left) ister A (SA) (Right)
 This instruction supports changes in the sequence of

(c) Jump and Branch
instruction execution by adding an extended, 6-bit, signed

2s-complement address offset to the PC value
 The 6-bit Address (AD) field replaces the DR and SB
fields
• Example: Suppose that a jump is specified by the Opcode and the
PC contains 45 (0…0101101) and Address contains – 12
(110100). Then the new PC value will be:
0…0101101 + (1…110100) = 0…0100001 (45 + (– 12) = 33)
 The SA field is retained to permit jumps and branches on
N or Z based on the contents of Source register A
Chapter 1 630
ISA: Instruction Specifications
 The specifications provide:

• The name of the instruction
• The instruction's opcode
• A shorthand name for the opcode called a
mnemonic
• A specification for the instruction format
• A register transfer description of the instruction,
and
• A listing of the status bits that are meaningfulduring
an instruction's execution (not used in the architectures
defined in this chapter)
Chapter 1 631
ISA: Instruction Specifications (continued)
TA BLE 9-8
Instruction Speciﬁcations for the Simple Computer
Mne- Status
Instruction Opcode monic Format Description Bits
Move A 0000000 MOVA RD, RA R [D R ]← R [SA ]* N, Z

Increment 0000001 INC RD, RA R [D R ]← R [SA ] + 1* N, Z
A dd 0000010 A DD RD, R A, RB R [D R ]← R [SA ] + R [SB]* N, Z
Subtract 0000101 SUB RD, R A, RB R [D R ]← R [SA ] −R [SB]* N, Z
D ecrement 0000110 D EC RD, RA R [D R ]← R [SA ] −1* N, Z
A ND 0001000 A ND RD, R A, RB R [D R ]← R [SA ] ∧R [SB]* N, Z
OR 0001001 OR RD, R A, RB R [D R ]← R [SA ] ∨R [SB]* N, Z
E xclusive OR 0001010 XOR RD, R A, RB R [D R ]← R [SA ] ⊕ R [SB]* N, Z
NOT 0001011 NOT RD, RA R [D R ]← * N, Z
Move B 0001100 MOVB RD, RB R [D R ]← R [SB]*
Shift R ight 0001101 SHR RD, RB R [D R ]← sr R [SB]*
Shift Left 0001110 SHL RD, RB R [D R ]← sl R [SB]*
Load Immediate 1001100 LDI RD, OP R [D R ]← zf O P*
A dd Immediate 1000010 A DI RD, R A, OP R [D R ]← R [SA ] + zf O P* N, Z
Load 0010000 LD RD, RA R [D R ]← M[SA ]*
Store 0100000 ST R A, RB M[SA ] ← R [SB]*
Branch on Z ero 1100000 BRZ R A, AD if (R [SA ] = 0) PC← PC + se AD, N, Z
if (R [SA ] ≠0) PC ← PC + 1
Branch on 1100001 BRN R A, AD if (R [SA ] < 0) PC← PC + se AD, N, Z
Negative if (R [SA ]≥0) PC ← PC + 1
Jump 1110000 JMP RA PC ← R [SA ]
* For all of these instructions, PC ← PC + 1 is also executed to prepare for the next cycle
Chapter 1 632
ISA:Example Instructions and Data in
Memory
Memory Repr esentation of Instruc t ions and Data
D eciimal Dec i mal

Ad d r ess Mem ory C ontents Op cod e Other F i elds Op eration
25 00001 01 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1 ¬ R2 - R3
35 01000 00 000 100 101 32 (Store ) S A:4, SB:5 M[ R4] ¬ R5
45 10000 10 010 111 011 66 (Add DR: 2 , S A : 7 , OP :3 R 2 ¬ R7 + 3
Im mediate)
55 11000 00 101 110 100 96 (Branch AD: 44, SA:6 If R6 = 0,
on Z e ro ) PC ¬ PC - 20
70 000 000000110 00000 Data = 1 92. Aft e r execution of instruction in 35,
Data = 80.
Chapter 1 633
Single-Cycle Hardwired Control
 Based on the ISA defined, design a computer architecture

to support the ISA
 The architecture is to fetch and execute each instruction in
a single clock cycle
 The datapath from Figure 10-11 will be used
 The control unit will be defined as a part of the design
 The block diagram is shown on the next slide
Chapter 1 634
IR (8:6) || IR (2:0)
V E xtend
C Branch Jump A ddress
PC
N Control
Z
P J B A ddress
LBC Instruction
memory RW D
Instruction DA R egister
AA file BA
A B
Z ero fill
IR (2:0) Constant
in
Instruction decoder
1 0
MB
MU X B
A ddress out
Bus A Bus B
D ata out
MW
D B A M F M R M P J B
A A A B S D W W L B C A B D ata in A ddress
FS
CO NTRO L
V D ata
C Function memory
unit
N
D ata out
Z
F
D ata in
0 1
MD MU X D
Bus D
DATA PATH
Chapter 1 635
The Control Unit
 The Data Memory has been attached to the Address Out

and Data Out and Data In lines of the Datapath.
 The MW input to the Data Memory is the Memory Write
signal from the Control Unit.
 For convenience, the Instruction Memory, which is not
usually a part of the Control Unit is shown within it.
 The Instruction Memory address input is provided by the
PC and its instruction output feeds the Instruction Decoder.
 Zero-filled IR(2:0) becomes Constant In
 Extended IR(8:6) || IR(2:0) and Bus A are address inputs to
the PC.
 The PC is controlled by Branch Control logic
Chapter 1 636
PC Function
 PC function is based on instruction specifications

involving jumps and branches taken from Slide 13:
Branch on Zero BRZ if (R[ S A] = 0) PC ← PC + s e A D
Branch on Negative BRN if (R[ S A] < 0) PC ← PC + s e A D
J u mp JMP PC ← R[SA ]
 In addition to the above register transfers, the PC must also
implement: PC ← PC + 1
 The first two transfers above require addition to the PC of:
Address Offset = Extended IR(8:6) || IR(2:0)
 The third transfer requires that the PC be loaded with:
Jump Address = Bus A = R[SA]
 The counting function of the PC requires addition to the
PC of 1
Chapter 1 637
PC Function (continued)
 Branch Control determines the PC transfers based on five of

its inputs defined as follows:
• N,Z – negative and zero status bits
• PL – load enable for the PC
• JB – Jump/Branch select: If JB = 1, Jump, else Branch
• BC – Branch Condition select: If BC = 1, branch for N = 1, else
branch for Z = 1.
 The above is summarize by the following table:
PC Operation PL JB BC
Count Up 0 X X
Jump 1 1 X
Branch on Negative (else Count Up) 1 0 1
Branch on Zero (else Count Up) 1 0 0
 Sufficient information is provided here to design the PC
Chapter 1 638
Instruction Decoder
 The combinational instruction decoder converts the

instruction into the signals necessary to control all parts of the
computer during the single cycle execution
 The input is the 16-bit Instruction
 The outputs are control signals:
• Register file addresses DA, AA, and BA,
• Function Unit Select FS
• Multiplexer Select Controls MB and MD,
• Register file and Data Memory Write Controls RW and MW, and
• PC Controls PL, JB, and BC
 The register file outputs are simply pass-through signals:
DA = DR, AA = SA, and BA = SB
Determination of the remaining signals is more complex.
Chapter 1 639
Instruction Decoder (continued)
 The remaining control signals do not depend on the

addresses, so must be a function of IR(13:9)
 Formulation requires examining relationships between the
outputs and the opcodes given in Slides 12 and 13.
 Observe that for other than branches and jumps, FS =
IR(12:9)
 This implies that the other control signals should depend
as much as possible on IR(15:13) (which actually were
assigned with decoding in mind!)
 To make some sense of this, we divide instructions into
types as shown in the table on the next page
Chapter 1 640
T ruth Ta ble for Instruction Decoder Logic
Instruction Bits Contr ol W o rd Bits
Instruction Function T ype 15 14 13 9 MB M D R W M W P L J B B C
Function unit operations using 0 0 0 X 0 0 1 0 0 X X
registers
Memory read 0 0 1 X 0 1 1 0 0 X X
Memory write 0 1 0 X 0 X 0 1 0 X X
Function unit operations using 1 0 0 X 1 0 1 0 0 X X
register and constant
Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0
Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1
Unconditional J ump 1 1 1 X X X 0 0 1 1 X
Chapter 1 641
 The types are based on the blocks controlled and the seven signals to be
generated; types can be divided into two groups:
• Datapath and Memory Control (First 4 types)
• PC Control (Last 3 types)
 In Datapath and Memory Control blocks controlled are considered:
• Mux B (1st and 4th types)
• Memory and Mux D (2nd and 3rd types)
• By assigning codes with no or only one 1 for these, implementation of MB,
MD, RW and MW are simplified.
 In Control Unit more of a bit setting approach was used:
• Bit 15 = Bit 14 = 1 were assigned to generate PL
• Bit 13 values were assigned to generate JB.
• Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To
force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL.
 Also, useful bit correlations between values in the two groups were
exploited in assigning the codes.
Chapter 1 642
 The end result by use of the types, careful assignment of
codes, and use of don't cares, yields very simple logic:
 This completes the Instruction
Opcode DR SA SB
design of most of the 15 14 13 12 11 10 9 8–6 5–3 2–0
essential parts of
the single-cycle
simple computer
19– 17 16– 14 13– 11 10 9–6 5 4 3 2 1 0
DA AA BA MB FS MD RW MW PL JB BC
Control word Chapter 1 643

Example Instruction Execution
Six Instructio ns for the Sin g le-Cycle Comp uter
Operation Symb ol ic
co de na m e Fo rm a t D e s c r ip ti on Fu nc ti on MB MD RW MW PL JB BC
1000 010 ADI I mme diate A dd immediate R [ DR ] ¬ R [ SA ] + zf I (2:0) 1 0 1 0 0 0 0

operand
0010 000 LD Register Load mem o ry R [ DR ] ¬ M[R [ SA ] ] 0 1 1 0 0 1 0
c ont e n t in to
reg i s t er
0100 000 ST Register Store re gister M[ R [ SA ] ] ¬ R [ SB ] 0 1 0 1 0 0 0
c onten t in
memory
0001 110 SL Register Shift left R [ DR ] ¬ sl R [ SB ] 0 0 1 0 0 1 0
0001 011 NO T R egister Comple ment R [ DR ] ¬ R [ SA ] 0 0 1 0 0 0 1

reg i s t er
1100 000 BRZ J ump/Branch If R [SA] = 0, branch If R[ SA] = 0, 1 0 0 0 1 0 0
to PC + se AD PC ¬ P C + se AD ,
If R[S A ] ¹ 0, PC ¬ PC + 1
 Decoding, control inputs and paths shown

for ADI, RD and BRZ on next 6 slides
Chapter 1 644
Decoding for ADI
Instruction
1 0 0 0 0 1 0
Opcode DR SA SB
15 14 13 12 11 10 9 8–6 5–3 2–0
19– 17 16– 14 13– 11 10 9–6 5 4 3 2 1 0
1 0010 0 1 0 0 0 0
Control word
Chapter 1 645
IR(8:6) || IR(2:0)
Extend
V
C Branch
PC
N Control
Z
Control Inputs and Paths for ADI
P J B Address
L B C
Instruction 1
0 0 0 memory RW D
DA Register
Instruction
file
Increment AA A B BA
PC Zero fill
IR(2:0) Constant
in
Instruction decoder
1 0
MB 1
MUX B
Address out
Bus A Bus B No Write

Data out 0
MW
A A A B S D W W L B C 0010 A B Data in Address
FS
1 0 1 0 0 0
0CONTROL
0010
C
+
Function
Data
memory
unit
N
Data out
Z
F
Data in
0 1
0 MD
MUX D
Bus D
DATAPATH Chapter 1 646
Decoding for LD
Instruction
0 0 1 0 0 0 0
Opcode DR SA SB
15 14 13 12 11 10 9 8–6 5–3 2–0
19– 17 16– 14 13– 11 10 9–6 5 4 3 2 1 0
0 0000 1 1 0 0 1 0
Control word
Chapter 1 647
IR(8:6) || IR(2:0)
Extend
V
C Branch
PC
N Control Control Inputs and Paths for LD
Z
P J B Address
L B C
Instruction 1
0 1 0 memory RW D
DA Register
Instruction
file
Increment AA A B BA
PC Zero fill
IR(2:0) Constant
in
Instruction decoder
1 0
MB 0
MUX B
Address out

Data out 0
MW
FS
0 1 1 0 1 0
0CONTROL
0000
V Data
Function
C memory
unit
N
Data out
Z
F
Data in
0 1
1 MD
MUX D
Bus D
Decoding for BRZ
Instruction
11 0 0 0 0 0
Opcode DR SA SB
15 14 13 12 11 10 9 8–6 5–3 2–0
19– 17 16– 14 13– 11 10 9–6 5 4 3 2 1 0
1 0000 0 0 0 1 0 0
Control word
Chapter 1 649
IR(8:6) || IR(2:0)
Extend
V
C Branch
PC
N
Z
Control
Control Inputs and Paths for BRZ
No Write
P J B Address
L B C
Instruction 0
1 0 0 memory RW D
DA Register
Instruction
file
Branch on AA A B BA
Z Zero fill
IR(2:0) Constant
in
Instruction decoder
1 0
MB 1
MUX B
Address out

Data out 0
MW
FS
1 0 0 1 0 0
0CONTROL
0000
V Data
Function
C memory
unit
N
Data out
Z
F
Data in
0 1
0 MD
MUX D
Bus D
Terms of Use

Education, Inc.
Chapter 1 651
Part 3 – Multiple-Cycle Hardwired Control
Charles Kime & Mano

Overview
 Part 3 – Multiple Cycle Hardwired Control
• Single Cycle Computer Issues
• Modifications to Datapath
• Modifications to Control
• Sequential Control Design
Chapter 1 653
Single-Cycle Computer Issues
 Shortcoming of Single Cycle Design

• Complexity of instructions executable in a single cycle
is limited
• Accessing both an instruction and data from a simple
single memory impossible
• A long worst case delay path limits clock frequency and
the rate of performing instructions
 Handling of Shortcomings
• The first two shortcomings can be handled by the
multiple-cycle computer discussed here
• The third shortcoming is dealt with by using a
technique called pipelining described in Chapter 12
Chapter 1 654
Multiple-Cycle Computer
 Converting the single-cycle computer into a

multiple-cycle computer involves:
• Modifications to the datapath/memory
• Modification to the control unit
• Design of a multiple-cycle hardwired control
 The block diagram of the single-cycle SC
architecture is given on the next slide for
use in developing the multiple-cycle SC
architecture
Chapter 1 655
E xtend
2
PS PC
D
4 RW
DR R egister 4 DA 16  16
3 R egister
16 SA address
3 file
SB logic AA BA
3 4 A B
IR 4 4 4
IL O pcode D R SA SB A X BX D X
7 3 3 3 Z ero fill
1 0 MB
MU X B
4 Control State Bus B

4
4 Bus A 0 1
MM MU X M
D ata MW A ddress
out out
4 A B
Control Logic FS D ata in A ddress
V
C Function Memory
N unit M
Z
N P I D A B MF M R MM D ata out
F
S S L X X X B S D W MW D ata in
Sequence D atapath
control control 0 1
MD
4 Bus D MU X D
CO NTRO L DATAPATH
Chapter 1 656
Datapath Modifications
 Modifications appear on the next slide

 Use a single memory for both instructions and
data
• Not essential to the multiple-cycle design, but done to
illustrate the concept
• Requires new MUX M with control signal MM to
select the instruction address from the PC or the data
address
• Requires path from Memory Data Out to the instruction
path in the control unit
Chapter 1 657
E xtend
New Instruction Path
2
PS PC
D
4 RW
DR DA 16  16
3 Register 4 R egister
16 SA address
3 file
SB logic AA BA
3 4 A B
IR 4 4 4
Inst. & Data Address
7 3 3 3 Z ero fill
Mux
1 0 MB
MU X B

4
4 Bus A 0 1
MM MU X M
D ata MW A ddress
out out
4 A B
V
C Function Memory
N unit M
Z
F
Sequence D atapath
control control 0 1
MD
4 Bus D MU X D Inst. & Data Memory
CO NTRO L DATAPATH
Chapter 1 658
Datapath Modifications (continued)
 To hold operands between cycles, need additional

registers
• Add 8 temporary storage registers to the Register File
 Register File becomes 16 x 16
 Addresses to Register File increase from 3 to 4 bits
• Register File addresses come from:
 The instruction for the Storage Resource registers (0 to 7)
 The control word for the Temporary Storage registers (8 to 15)
 The control word specifies the source for Register File addresses
• Add Register Address Logic to the Register File to select the
register address sources
• Three new control fields for register address source selection
and temporary storage addressing: DX, AX, BX
Chapter 1 659
Register Address
E xtend
2 Logic 16 x 16 Register File
PS PC
D
4 RW
DR DA 16  16
3 R egister 4 R egister
16 SA address
3 file
SB logic AA BA
3 4 A B
IR 4 4 4
Inst. & Data Address
7 3 3 3 Z ero fill
Mux
1 0 MB
MU X B

4
4 Bus A 0 1
MM MU X M
D ata MW A ddress
out out
4 A B
V
C Function Memory
N unit M
Z
F
Sequence D atapath
control control 0 1
MD
4 Bus D MU X D
CO NTRO L DATAPATH
Chapter 1 660
Control Unit Modifications
 Must hold instruction over the multiple

cycles to draw on instruction information
throughout instruction execution
• Requires an Instruction Register (IR) to hold
the instruction
 Load control signal IL
• Requires the addition of a "hold" operation to
the PC since it only counts up to obtain a new
instruction
 New encoding for the PC operations uses 2 bits
Chapter 1 661
E xtend
2
PS PC
Add "hold" operation
D
4 RW
Instruction Register DR DA 16  16
16 SA address
IR 3 file
SB logic AA BA
3 4 A B
IR 4 4 4
7 3 3 3 Z ero fill
1 0 MB
MU X B

4
4 Bus A 0 1
MM MU X M
D ata MW A ddress
out out
4 A B
V
C Function Memory
N unit M
Z
F
Sequence D atapath
control control 0 1
MD
4 Bus D MU X D
CO NTRO L DATAPATH
Chapter 1 662
Sequential Control Design
 In order to control microoperations over multiple cycles, a

Sequential Control replaces the Instruction Decoder
• Input: Opcode, Status Bits
• Output: Control Word (Modified Datapath Control part)
• Control State
• Next State: Control Word (New Sequencing Control part)
• Consists of (see next slide):
 Register to store the Control State
 Combinational Logic to generate the Control Word (both
sequencing and datapath control parts)
• The Combinational Logic is quite complex so we assume
that it is implemented by using a PLA or synthesized logic
and focus on ASM level design
Chapter 1 663
E xtend
2
PS PC
D
4 RW
DR DA 16  16
16 SA address
3 file
SB logic A A BA
3 4 A B
IR 4 4 4
Control State Register
7 3 3 3 Z ero fill
1 0 MB
MU X B

4
4 Bus A 0 1
Combinational Control MM MU X M
Logic D ata MW A ddress
out out
4 A B
V
C Function Memory
New/ Modified Control N unit M
Z
Word
F
Sequence D atapath
control control 0 1
MD
4 Bus D MU X D
CO NTRO L DATAPATH
Chapter 1 664
Control Word
27 24 23 22 21 20 17 16 13 12 9 8 7 4 3 2 1 0
I M M R M M
NS PS DX AX BX FS
L B D W M W
Sequencing Datapath
 Datapath part: fields DA, AA, and BA replaced by DX, AX, and
BX, respectively, and field MM added
• If the MSB of a field is 0, e.g., AX = 0XXX, then AA is 0 concatenated
with 3 bits obtained from the SA field in the IR
• If the MSB of a field is 1, e. g. AX = 1011, then AA = 1011
 Sequencing part:
• IL controls the loading of the IR
• PS controls the operations of the PC
• NS gives the next state of the Control State register
 NS is 4 bits, the length of the Control State register - 16 states are viewed as
adequate for this design
Chapter 1 665
Encoding for Datapath Control
DX AX BX Code MB Code FS Code MD R W MM MW Code
R [DR] R [SA] R [SB] 0 XXX Register 0 F← A 0000 FnUt No Address No 0
write Out write
R 8 R 8 R 8 1000 Constant 1 F ←A + 1 0001 Data In Write PC Write 1
R 9 R 9 R 9 1001 F ←A + B 0010
R 10 R 10 R 10 1010 Unused 0011
R 11 R 11 R 11 1011 Unused 0100
R 12 R 12 R 12 1100 F ←A + B + 1 0101
R 13 R 13 R 13 1101 F ←A – 1 0110
R 14 R 14 R 14 1110 Unused 0111
R 15 R 15 R 15 1111 F ←A B 1000
^
F ←A v B 1001
F ←A + B 1010
1011
F ←A
F ←B 1100
F ← sr B 1101
F ← sl B 1110
Unused 1111
Chapter 1 666
Encoding for Sequencing Control
NS PS IL
Ne xt State Action Code Action Code
Gives next state Hold PC 00 No load 0

of Control State Inc PC 01 Load IR 1
Register Branch 10
J ump 11
Chapter 1 667
SMDs for Sequential Control
 An instruction requires two steps:

• Instruction fetch – obtaining an instruction from
memory
• Instruction execution – the execution of a sequence of
microoperations to perform instruction processing
• Due to the use of the IR, these two steps require a
minimum of two clock cycles
 ISA: Instruction Specifications and SMD for the
instructions (that all require two clock cycles) are
given on the next four slides.
Chapter 1 668
ISA: Instruction Specifications (for reference only)
I n st ruction Speci fications for the Simple Comput er - Part 1
St a t u s
Instr u ctio n O pc ode Mnem on ic Form at D escrip tion Bits
Move A 0000000 MO V A RD ,RA R [DR] ¬ R[SA ] N, Z
Increment 0000001 INC R D , RA R[DR] ¬ R [ SA] +1 N, Z
Add 0000010 ADD R D , RA,RB R [DR] ¬ R[SA ] + R[ SB] N, Z
Subtr a ct 0000101 SUB R D , RA,RB R [DR] ¬ R[SA ] - R [ SB] N, Z
D e crement 0000110 DEC R D , RA R[DR] ¬ R[SA ] - 1 N, Z
AND 0001000 AND R D , RA,RB R [DR] ¬ R[SA ] Ù R[SB ] N ,Z
O R 0001001 OR RD ,RA,RB R[DR] ¬ R[SA ] Ú R[SB ] N ,Z
Exclusive OR 0001010 XOR R D, RA,RB R [DR] ¬ R[SA ] Å R[SB] N, Z
NO T 0001011 NO T R D , RA R[DR] ¬ R[SA ] N, Z
 SMD on Next Slide
Chapter 1 669
SMD for Two-Cycle Instructions -
Part 1
PC PC + 1
S
INF IR M[PC]
O pcode =
R [D R ] R [SA ] 0000000
R [D R ] R [SA ] + 1 0000001
R [D R ] R [SA ] + R [SB] 0000010
R [D R ] R [SA ] + R [SB] +1 0000101
R [D R ] R [SA ] 2 1 0000110
R [D R ] R [SA ] R [SB] 0001000
R [D R ] R [SA ] R [SB] 0001001
E X0
R [D R ] R [SA ] % R [SB] 0001010
R [D R ] R [SA ] 0001011
Chapter 1 670
ISA: Instruction Specifications (for reference only)
I n st ruction Speci fications for the Simple Comput er - Part 2
St a t u s
Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion Bits
Move B 0001100 MO VB RD ,RB R [DR] ¬ R[SB]
Shift Right 0001101 SHR R D , RB R[DR] ¬ sr R[SB]
Shift Left 0001110 SHL R D , RB R[DR] ¬ sl R[SB]
Load Imm e diate 1001100 LDI R D, O P R[DR] ¬ zf OP
Add Immediate 1000010 ADI R D, RA,OP R [DR] ¬ R[SA] + zf OP
Load 0010000 LD RD ,RA R [DR] ¬ M[ SA ]
Store 0100000 ST RA,RB M [SA] ¬ R[SB]
Branch on Zero 1100000 BRZ R A,AD if (R[ S A] = 0) PC ¬ PC +s e A D
Branch on Negative 1100001 BRN R A,AD if (R[ S A] < 0) PC ¬ PC +s e A D
J u mp 1110000 JMP R A P C ¬ R[SA ]
Chapter 1 671
SMD for 2-Cycle
Instructions – Part 2
 Instruction Fetch
Portion Duplicated
From Part 1
Chapter 1 672
State Table for 2-Cycle Instructions
In puts O utp uts
N e xt
State
st ate I P M M R M M
O pcode V C N Z L S D X A X B X B F S D W M W C o m m e nts
IN F X X XX X X X XXXX EX0 1 00 X XX X XX X X X X XX X X X XX X 0 1 0 I R← M [ PC ]
E X 0 0 000000 XXXX INF 0 01 0 XXX 0 X XX X X XX X 0000 0 1 X 0 M O V A R [DR ] ← R [SA]*
E X 0 0 000001 XXXX INF 0 01 0 XXX 0 X XX X X XX X 0001 0 1 X 0 I N C R [DR ] ← R [S A ] + 1*
E X 0 0 000010 XXXX INF 0 01 0 XXX 0 X XX 0 X XX 0 0010 0 1 X 0 A D D R [DR ] ← R [S A ] + R [S B ]*
E X 0 0 000101 XXXX INF 0 01 0 XXX 0 X XX 0 X XX 0 0101 0 1 X 0 SU B R [DR } ← R [S A ] + R [S B ] + 1*
E X 0 0 000110 XXXX INF 0 01 0 XXX 0 X XX X X XX X 0110 0 1 X 0 D E C R [DR ] ← R [S A ] + ( - 1) *
E X 0 0 001000 XXXX INF 0 01 0 XXX 0 X XX 0 X XX 0 1000 0 1 X 0 A N D R [DR ] ← R [SA] R [S B ]*

^
E X 0 0 001001 XXXX INF 0 01 0 XXX 0 X XX 0 X XX 0 1001 0 1 X 0 O R R [DR ] ← R [SA] v R [S B ]*
E X 0 0 001010 XXXX INF 0 01 0 XXX 0 X XX 0 X XX 0 1010 0 1 X 0 X O R R [DR ] ← R [SA] + R [S B ]*
E X 0 0 001011 XXXX INF 0 01 0 XXX 0 X XX X X XX X 1011 0 1 X 0 N O T R [DR ] ← R [S A ] *
E X 0 0 001100 XXXX INF 0 01 0 XXX XX X X 0 X XX 0 1100 0 1 X 0 M O V B R [DR ] ← R [S B ]*
E X 0 0 010000 XXXX INF 0 01 0 XXX 0 X XX X X XX X X X XX 1 1 0 0 L D R [DR ] ← M [R [SA]]*
E X 0 0 100000 XXXX INF 0 01 X XX X 0 X XX 0 X XX 0 X X XX X 0 0 1 S T M [ R [SA]] ← R [S B ]*
E X 0 1 001100 XXXX INF 0 01 0 XXX XX X X X X XX 1 1100 0 1 0 0 LDI R [DR ] ← zf OP *
E X 0 1 000010 XXXX INF 0 01 0 XXX 0 X XX X X XX 1 0010 0 1 0 0 ADI R [DR ] ← R [S A ] + z f OP *
E X 0 1 100000 X XX1 IN F 0 10 X XX X 0 X XX X X XX X 0000 X 0 0 0 B R Z PC ← PC + se A D
E X 0 1 100000 X XX0 IN F 0 01 X XX X 0 X XX X X XX X 0000 X 0 0 0 B R Z PC ← PC + 1
E X 0 1 100001 X X1 X INF 0 10 X XX X 0 X XX X X XX X 0000 X 0 0 0 B R N PC ← PC + se A D
E X 0 1 100001 X X0 X INF 0 01 X XX X 0 X XX X X XX X 0000 X 0 0 0 B R N PC ← PC + 1
E X 0 1 110000 XXXX INF 0 11 X XX X 0 X XX X X XX X 0000 X 0 0 0 J M P PC ← R [S A ]
* F o r thi s state a n d i n put combinati o n, PC ¬ PC + 1 als o oc cur s .
Chapter 1 673
SMD for Right Shift and Left Shift Multiple
From INF
R8 R [SA ]
PC PC 1 1
Z · ((O pcode = 0001101) + (O pcode = 0001110))
E X0 E X1
Z · ((O pcode = 0001101)
+ (O pcode = 0001110))
0 ))
Z · ((O pcode = 0001101) PC PC 1 1 0 0 0111 R9 zf O P
e =
co d
+ (O pcode = 0001110)) (O p
0 1) +
= 0 0011
e
co d
· ( (O p
Z
E X2 E X3
O pcode = 0001101 R 8 sr R 8
O pcode = 0001110 R 8 sl R 8
Z · ((O pcode = 0001101)
+ (O pcode = 0001110)) R9 R92 1
Z · ((O pcode = 0001101) + (O pcode = 0001110))
E X4
R [D R ] R 8,
(O pcode = 0001101) + (O pcode = 0001110) PC PC 1 1
To INF
Chapter 1 674
State Table For Right and Left Shift Multiple
TA BLE 9-15
State Table for Illustration of Instructions Having Three or Mo re Cycles
Inputs Outputs
Next
State Comments
state I M
Opcode VCNZ L PS DX AX BX MB FS MD RW MM W
E X0 0010001 XXXX E X1 0 00 1000 0XXX XXXX X 0000 1 1 X 0 LR I R8 ← M[R[SA ]], → E X1

E X1 0010001 XXXX INF 0 01 0XXX 1000 XXXX X 0000 1 1 X 0 LR I R[D R ] ← M[R8], → INF*
E X0 0001101 XXX 0 E X1 0 00 1000 0XXX XXXX X 0000 0 1 X 0 SR M R8 ← R[SA ], : → E X1

E X0 0001101 XXX 1 INF 0 01 1000 0XXX XXXX X 0000 0 1 X 0 SR M R8 ← R[SA ], Z : → INF*
E X1 0001101 XXX 0 E X2 0 00 1001 XXXX XXXX 1 1100 0 1 X 0 SR M R9 ← zf OP, : → E X2
E X1 0001101 XXX 1 INF 0 01 1001 XXXX XXXX 1 1100 0 1 X 0 SR M R9 ← zf OP, Z : → INF*
E X2 0001101 XXXX E X3 0 00 1000 XXXX 1000 0 1101 0 1 X 0 SR M R8 ← sr R8, → E X3
E X3 0001101 XXX 0 E X2 0 00 1001 1001 XXXX X 0110 0 1 X 0 SR M R9 ← R9 −1, : → E X2
E X3 0001101 XXX 1 E X4 0 00 1001 1001 XXXX X 0110 0 1 X 0 SR M R9 ← R9 −1, Z : → E X4
E X4 0001101 XXXX INF 0 01 0XXX 1000 XXXX X 0000 0 1 X 0 SR M R[D R ] ← R8, → INF*
E X0 0001110 XXX 0 E X1 0 00 1000 0XXX XXXX X 0000 0 1 X 0 SLM R8 ← R[SA ], : → E X1
E X0 0001110 XXX 1 INF 0 01 1000 0XXX XXXX X 0000 0 1 X 0 SLM R8 ← R[SA ], Z : → INF*
E X1 0001110 XXX 0 E X2 0 00 1001 XXXX XXXX 1 1100 0 1 X 0 SLM R9 ← zf OP, : → E X2
E X1 0001110 XXX 1 INF 0 01 1001 XXXX XXXX 1 1100 0 1 X 0 SLM R9 ← zf OP, Z : → INF*
E X2 0001110 XXXX E X3 0 00 1000 XXXX 1000 0 1110 0 1 X 0 SLM R8 ← sl R8, → E X3
E X3 0001110 XXX 0 E X2 0 00 1001 1001 XXXX X 0110 0 1 X 0 SLM R9 ← R9 −1, : → E X2
E X3 0001110 XXX 1 E X4 0 00 1001 1001 XXXX X 0110 0 1 X 0 SLM R9 ← R9 −1, Z : → E X4
E X4 0001110 XXXX INF 0 01 0XXX 1000 XXXX X 0000 0 1 X 0
*For this state and input combination , PC ← PC + 1 also occurs.
Chapter 1 675
Terms of Use
Education, Inc.
Chapter 1 676

Digital Logic Design - Revision

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NUMBER SYSTEMS – Representation

 Positive radix, positional number systems

(Integer Portion) + (Fraction Portion)

General Decimal Binary

 210 (1024) is Kilo, denoted "K"

 220 (1,048,576) is Mega, denoted "M"

 230 (1,073, 741,824)is Giga, denoted "G"

 240 (1,099,511,627,776 ) is Tera, denoted “T"

 Single Bit Addition with Carry

Given two binary digits (X,Y), a carry in (Z) we get the

 Extending this to two multiple bit

 Extending this to two multiple bit examples:

The binary multiplication table is simple:

 Useful for Base Conversion

 To convert to decimal, use decimal arithmetic

Name Radix Digits

 The six letters (in addition to the 10

 Good idea to memorize!

2) Convert the Fraction Part

3) Join the two results with a radix point

 To Convert the Integral Part:

 Convert 0.6875 to Base 2:

 Join the results together with the

 Note that in this conversion, the fractional part

To convert back, sum the digits times their

 Convert octal to binary.

 Why do these conversions work? Chapter 1 22

 You can use arithmetic in other bases if

 Given n binary digits (called bits), a binary code

for the seven Orange 001

colors of the Yellow 010

rainbow Green 011

not used Violet 111

 Given M elements to be represented by a

 Given n digits in radix r, there are rn

few are useful:

Decimal 8,4,2,1 Excess3 8,4, - 2, - 1 Gray

0 0000 0011 0000 0000

1 0001 0100 0111 0100

2 0010 0101 0110 0101

3 0011 0110 0101 0111

4 0100 0111 0100 0110

5 0101 1000 1011 0010

6 0110 1001 1010 0011

7 0111 1010 1001 0001

8 1000 1011 1000 1001

9 1001 1 100 1111 1000

 The BCD code is the 8,4,2,1 code.

Decimal Excess 3 8, 4, –2, –1

 Do NOT mix up conversion of a decimal

represented by two digits!

carry = 1 0011 leaving 3 + cy

0001 | 0011 Final answer (two digits)

 Add 2905BCD to 1897BCD showing

0001 1000 1001 0111

+ 0010 1001 0000 0101

ASCII has some interesting properties:

 Digits 0 to 9 span Hexadecimal values 3016 to 3916 .

punched paper tape was used to store messages.

 Redundancy (e.g. extra information), in the

 A simple form of redundancy is parity, an extra

 Fill in the even and odd parity bits:

Decimal 8,4,2,1 Gray