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M. Rizwan MCSM-17-56
M. Bilal MCSM-17- 11
Nadir Abbas MCSM-17-36
M. Ans Khalid MCSM-17-60
M.Rizwan
Introduction of Latch and Flip flop
Combination Logical Circuit
Combination circuit is a type of digital logic which is
implement by boolean circuit where the output is a
pure function of the present input.
Sequential logic circuit
Sequential logic is a type of logic circuit whose output
depends not only on the present value of its input
signals but on the sequence of past inputs.
Sequence circuit is the extent of combination circuit.
Difference between combination circuit and
sequential circuit
R
Q’
Logical Diagram
RS Latch work only positive edge tagger.
SR Latch Using Nand Gate
Operation
When S=1 and R=0 then output is Q=0 and Q’=1.
Nand Gate Truth Table
X Y R
0 0 1
0 1 1
1 0 1
1 1 0
Operation
Q(t+1)= o.
Operation
When input S=0 and R=1 and Q =0 then output
Q(t+1)= o.
Operation
When input S=1 and R=0 and Q =0 then output
Q(t+1)= 1.
Operation
When input S=1 and R=1 and Q =0 then output is
determinate.
Operation
When input S=0 and R=0 and Q =1 then output is
Q(t+1)=1.
Operation
When input S=0 and R=1 and Q =1 then output is
Q(t+1)=0.
When input S=1 and R=o and Q =1 then output is
Q(t+1)=1.
When input S=1 and R=1 and Q =1 then output is
Q(t+1)=indeterminate.
Equation of SR Flip Flop
SR
Q oo o1 11 10
1
0
1 1 1
Q(t+1)=S+QR
RS Flip Flop With NOR Gate
Nadir Abbas
D Flip Flop
D Flip Flop
D Flip Flop is the modification of the clocked SR flip flop.
In D Flip Flop Inverter is used for second input.
In D flip flop input and output has same value.
Symbolic Diagram
Note
D Flip Flop is used only to delay the
input value.
D Flip Flop using NAND gate
Q(t) D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1
Truth table of D Flip Flop
also 0.
Operation
When Q(t)=0 and input Q=1 then output Q(t+1) is
also 1.
Operation
When Q(t)=1 and input Q=0 then output Q(t+1) is
also 0.
When Q(t)=1 and input Q=1 then output
Q(t+1) is also 1.
Equation Of D Flip Fop
D 0 1
S 1
0
1 1
Q(t+1)=D
D Flip Flop with NOR and Nor gate
M.Ans Khalid
Jk Flip Flop and Jk Master Slave Flip Flop.
JK Flip Flop
Jk is a refinement of SR Flip Flop to solve the problem
of indeterminate state when both input is ‘1’ .
In JK Flip Flop J and K input work as S and R input.
JK flip flop using NAND gate
Q(t+1)=1.
Operation
When input J=1 and K=1 and Q=0 then output
Q(t+1)=1.
Operation
When input J=0 and K=0 and Q=1 then output
Q(t+1)=1.
Operation
When input J=0 and K=1 and Q=1 then output
Q(t+1)=0.
When input J=1 and K=0 and Q=1 then output
Q(t+1)=1.
Operation
When input J=1 and K=1 and Q=1 then output
Q(t+1)=0.
Equation Of JK Flip Flop
JK 00 01 11 10
Q0 1 1
1 1
1
Q(t+1)=JQ’+ QK’
JK flip flop with NOR Gate
T Flip Flop Using NAND gate
It’s a single input version of JK flip flop.
T stand for toggle.
T Flip Flop has one input and and two output.
A
A
(a) Diagram
T Flip Flop