Scribd Logo
Upload

Welcome to Scribd!

  • Uvm Ral

    Uploaded by

    SubbuNaidu
    20 views35 pages
    The document discusses the UVM register model which provides a way to track register content on a design under test and conveniently access registers and memory. It covers an overview of the register model, how the model is generated, using an adapter to integrate with a verification IP, backdoor access to registers, and stimulus abstraction using built-in sequences to read and write registers.

    Original Description:

    Original Title

    UVM_RAL

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document discusses the UVM register model which provides a way to track register content on a design under test and conveniently access registers and memory. It covers an overview of the register model, how the model is generated, using an adapter to integrate with a verification IP, backdoor access to registers, and stimulus abstraction using built-in sequences to read and write registers.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    20 views35 pages

    Uvm Ral

    Uploaded by

    SubbuNaidu
    The document discusses the UVM register model which provides a way to track register content on a design under test and conveniently access registers and memory. It covers an overview of the register model, how the model is generated, using an adapter to integrate with a verification IP, backdoor access to registers, and stimulus abstraction using built-in sequences to read and write registers.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 35

    UVM RAL

    content

    • Introduction
    • Register Model overview
    • Register model Generation
    • Adapter
    • Integrating
    • Backdoor Access
    • Stimulus Abstraction
    • Built-in sequences
    Introduction
    Introduction

    The UVM register model provides a way of tracking the register content of a DUT and a convenience
    layer for accessing register and memory locations within the DUT.
    Register Model overview
    Example: jelly bean taster
    Register Model Generation
    Adapter
    Adapter
    Developing the adapter requires knowledge of the target
    bus protocol and how the different fields in the VIP
    sequence_item relate to that protocol.
    Integration
    Integration
    Backdoor Access
    Stimulus Abstraction
    Read write

    Update

    You might also like