Module:3

Processing Unit – Control Path

L3:Instructions set architectures, CISC

and RISC architecture

Dr. Gayathri Sivakumar

Assistant Professor Sr. Grade
SENSE
VIT, Chennai
Instruction Set Architecture
Instruction Set Architecture (ISA)
• Serves as an interface between software and hardware
• Provides a mechanism by which the software (program instructions) tells the
hardware (Processor) what should be done.
Instruction Set
Instruction set architectures are measured according to:
• Main memory space occupied by a program.
• Instruction complexity.
• Instruction length (in bits).
• Total number of instruction in the instruction set.
 Instruction set design
• One of the most interesting, and most analyzed, aspects of computer design is instruction set
design.
• The instruction set defines the functions performed by the CPU. The instruction set is the
programmer's means of controlling the CPU.
• Thus programmer requirements must be considered in designing the instruction set.
• Most important and fundamental design issues:
Classification of ISA
• The number of address fields in the instruction format depends on the internal
organization of CPU
• Instruction sets are differentiated by the following:
• Number of bits per instruction.
• Accumulator-based, stack-based or register-based.
• Number of explicit operands per instruction.
• Operand location.
• Types of operations.
• Type and size of operands.
• The three most common CPU organizations

1. Single accumulator organization

2. General register organization
3. Stack organization
Single accumulator organization One address machine

• accumulator holds an operand for the instruction

• instruction leaves the result in the accumulator
• PDP-8, Mark I computer

ADD X /* AC  AC + M[X] */

Pros Cons
1. Very low hardware requirements 1. Accumulator becomes the bottleneck
2. Easy to design and understand 2. Little ability for parallelism or pipelining
3. High memory traffic
 General register organization
• Multiple registers used as accumulator
• PDP-11, IBM system/360

ADD R1, R2, R3 /* R1  R2 + R3 */

ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */

Pros Cons
1. Some data can be accessed without loading 1. Operands are not equivalent
first 2. Variable number of clocks per
2. Instruction format easy to encode instruction
3. Good code density 3. May limit number of registers
 Stack organization
• push down list with a Last In First Out (LIFO) access
mechanism
• all operations by the CPU are done on the contents of a
stack; result stored in stack
• Burroughs B5000 and HP 3000
PUSH X /* TOS  M[X] */
ADD Cons
1. Stack becomes the bottleneck
Pros
2. Little ability for parallelism or pipelining
1. Good code density (implicit top of stack)
3. Data is not always at the top of stack
2. Low hardware requirements
when need, so additional instructions like
3. Easy to write a simpler compiler for stack
TOP and SWAP are needed
architectures
4. Difficult to write an optimizing compiler
for stack architectures
Assembly code of C = A + B; in all 3 architectures
CISC and RISC Architecture
Introduction
• The computer designers intend to reduce this gap and include large instruction set, more
addressing mode and various High Level Language (HLL) statements implemented in
hardware.
• As a result the instruction set becomes complex. Such complex instruction sets are
intended to-
• Ease the task of the compiler writer.
• Improve execution efficiency, because complex sequences of operations can be
implemented in microcode.
• Provide support for even more complex and sophisticated HLLs.
• To reduce the gap between HLL and the instruction set of computer architecture, the
system becomes more and more complex and the resulted system is termed as Complex
Instruction Set Computer (CISC).
 Cont…

• A number of studies have been done over the years to determine the characteristics
and patterns of execution of machine instructions generated from HLL programs.
• The instruction execution characteristics involves the following aspects of
computation:
• Operation Performed: These determine the functions to be performed by the
processor and its interaction with memory.
• Operand Used: The types of operands and the frequency of their use
determine the memory organization for storing them and the addressing modes
for accessing them.
• Execution sequencing: This determines the control and pipeline organization.
 Cont…
• A variety of studies have analyzed the behavior of high level language program. The
below Table includes key results, measuring the appearance of various statement
types during execution which is carried out by different researchers.
• These results are instructive to the machine instruction set designers, indicating
which type of statements occur most often and therefore should be supported in an
―optimal‖ fashion.
• From these studies one can observe that though a complex and sophisticated
instruction set is available in a machine architecture, common programmer may not
use those instructions frequently.
Classification of ISA
Based on CPU design and instruction set, the computer architecture can
be classified into two categories:
1. Complex Instruction Set Computer (CISC)
2. Reduce Instruction Set Computers (RISC)
CISC Architecture
• A large number of instruction types used – typically from 100 to 250
instructions.
• A large number of addressing modes used- typically from 5 to 15 different
modes.
• Some instructions that perform specialized tasks are used infrequently.
• Variable-length instruction formats.
• Small number of general-purpose registers (GPRs) – typically 8-24 GPRs.
• Clock per instruction (CPI) lies between 2 and 15.
• Mostly micro-programmed control units.
• Most instructions manipulate operands in memory.
 Cont…

The two architectures, CISC and RISC, can be compared based on

1- instruction set
2-studying the available addressing modes
3-the integer and floating point units

VAX 11/780 Intel’s Pentium

1. Number of instructions: 303
2. Instruction size: 2 – 8 bytes
3. Instruction format: not fixed
4. Addressing modes: 22
5. Number of general purpose
registers: 16
1. Number of instructions: 235
2. Instruction size: 1 – 8 bytes
3. Instruction format: not fixed
4. Addressing modes: 11
5. Number of general purpose
registers: 8
 Demerits of CISC

• CPU complexity: micro-programmed control unit design becomes complex

since the instruction set is large.
• System size and cost: Due to complexity of the CPU, a lot of hardware
circuitry is used in the system. Thus, the hardware cost of the system and the
power consumption have increased.
• Clock per instruction (CPI): number of clock periods needed for each
instruction execution is large and hence the overall execution time is
reduced. In other words, the CPI consists of some number of clock pulses.
• Reliability: As heavy hardware is prone to frequent failures, the reliability of
the system degrades.
• Maintainability: Since there are a large number of huge circuits,
troubleshooting and detecting a fault is tough task.
RISC Architecture
• RISC concept – an attempt to reduce the execution cycle by simplifying the
instruction set
• Relatively few number of instruction types—typically less than100
instructions
• Relatively few addressing modes—typically less than or equal to 5
• Fixed-length, easily decoded instruction formats
• Large number of general-purpose registers (GPRs)—typically 32-192 GPRs
• Clock per instruction (CPI) lies between 1 and 2
• Memory access limited to load and store instructions
• All operations are executed within registers of the CPU
 Cont…

• Mostly hardwired control units.

• RISC architecture is simple and efficient
• New RISC computers may have some instruction that are quite complex

Sun SPARC PowerPC

1. Number of instructions: 52
2. Instruction size: 4 bytes
3. Instruction format: fixed
4. Addressing modes: 2
5. Number of general purpose
registers: up to 520
1. Number of instructions: 206
2. Instruction size: 4 bytes
3. Instruction format: not fixed (but
small differences)
4. Addressing modes: 2
5. Number of general purpose
registers: 32
Implications
• A number of groups have looked at these results and have concluded that the attempt
to make the instruction set architecture close to HLL is not the most effective design
strategy.
• Generalizing from the work of a number of researchers three element emerge in the
computer architecture.
• First, use a large number of registers or use a compiler to optimize register usage.
This is intended to optimize operand referencing.
• Second, careful attention needs to be paid to the design of instruction pipelines.
Because of the high proportion of conditional branch and procedure call instructions, a
straight forward instruction pipeline will be inefficient. This manifests itself as a high
proportion of instructions that are prefetched but never executed.
• Third, a simplified (reduced) instruction set is indicated. It is observed that there is no
point to design a complex instruction set which will lead to a complex architecture.
Due to the fact, a most interesting and important processor architecture evolves which
is termed as Reduced Instruction Set Computer (RISC) architecture.
Design elements-RISC

• Although RISC system have been defined and designed in a variety of

ways by different groups, the key element shared by most design are
these:
• A large number of general purpose registers, or the use of compiler
technology to optimize register usage.
• A limited and simple instruction set.
• An emphasis on optimizing the instruction pipeline
• An analysis of the RSIC architecture begins into focus many of the
important issues in computer organization and architecture.
Characteristics of Reduced Instruction Set Architecture
Although a variety of
different approaches to
reduce Instruction set
architecture have been
taken, certain
characteristics are
common to all of them:

• One instruction per

cycle.
• Register–to–register
operations.
• Simple addressing
modes.
• Simple instruction
formats.
One machine instruction per machine cycle : Cont..
• A machine cycle is defined to be the time it takes to fetch two operands from registers, perform an
ALU operation, and store the result in a register.
With simple, one-cycle instructions there is little or no need of microcode, the machine instructions
can be hardwired. Hardware implementation of control unit executes faster than the
microprogrammed control, because it is not necessary to access a microprogram control store
during instruction execution.
Register –to– register operations
• With register–to–register operation, a simple LOAD and STORE operation is required to access the
memory, because most of the operation are register–to-register. Generally we do not have memory–
to–memory and mixed register/memory operation.
Simple Addressing Modes
• Almost all RISC instructions use simple register addressing. For memory access only, we may
include some other addressing, such as displacement and PC-relative. Once the data are fetched
inside the CPU, all instruction can be performed with simple register addressing.
Simple Instruction Format
• Generally in most of the RISC machine, only one or few formats are used. Instruction length is
fixed and aligned on word boundaries. Field locations, especially the opcode, are fixed.
With fixed fields, opcode decoding and register operand accessing can occur simultaneously.
Simplified formats simplify the control unit
Demerits of RISC

• Difficult to program at assembly level

• No solution for floating point numbers
• Lacks some sophisticated instructions found in CISC processors
• Several RISC instructions may be needed to replace one CISC
instruction, which results in longer programs
• Performance is intimately tied to compiler optimisation
• More error-prone and less flexible hardwired control units
Comparison: CISC and RISC
• RISC is good in environments requiring
— small size.
— low power consumption.
— low heat dissipation.
• On modern-day general-purpose machines, RISC and CISC have
converged to an extent.
• For example, Intel’s Pentium series, the VAX 9000 and Motorola
88100 are built with mixed features taken from both the RISC and
CISC camps.
• Modern RISCs (ARM, Sun SPARC, HP PA-RISC) more complex than
forebears.
• Modern CISCs incorporate many features learned from RISC
Cont…
CISC issues and RISC solutions
Cont…
Reference

• William Stallings, 8th Edition, Computer Organization and Architecture, Designing

for Performance, Pearson, 2010, New Jersey
• B.Govindarajalu, 2nd Edition, Computer Architecture and Organization, Design
Principles and Applications, Tata-McGraw-Hill, 2010, New Delhi
• [HUCK83] Huck, T; "Comparative analysis of computer architectures", Stanford
University Technical Report No.83-243.
• [KNUTH71] Knuth D; "An Empirical Study of FORTRAN programs ", Software
practice and Experience, Vol. 1,1971. No.83-243
• [PATT82] Patterson, D and Sequin, C; "A VLSI RISC ", Computer, September
1982.
• [TANE78] Tanenbaum, A; "Implication of Structured Programming for machine
architecture ", Communication of the ACM, March 1978.