LMK05028 EVM Quick Start Guide

With TICS Pro Installation and LMK05028 GUI Workflow

PRELIMINARY
2017-11-17

1
Contents
• LMK05028 EVM Overview
– Default EVM Configuration
• EVM Quick Start
– EVM Test Setup Example
• TICS Pro GUI Installation
• LMK05028 GUI Workflow
– Request a LMK05028 config file (.tcs) before using TICS Pro
– GUI Overview
– GUI Detailed Flow
• Communication Set-up
• Configure Device
• Program Device
• Appendix
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LMK05028 EVM Overview • IN[0:3]_P/N SMA ports are DC-coupled to DUT
• TCXO_IN SMA port is AC-coupled to DUT
• OUT[0:6]_P/N SMA ports are AC-coupled to DUT
• OUT7_P/N is DC-coupled to the DUT
Ref Des Ref Des
# Pre-Prod EVM Final EVM Component Description
0 U5 U5 LMK05028 (DUT)
1 J4 J4 Mini-USB Port
00
2 D8, D9 D8, D9 Status LEDs – GPIO 5, 6
3 D12, D13 D12, D13 Status LEDs – STATUS 0,1
4 JP27 JP4 Power LED – TCXO (Y2)
5 JP28 JP5 I2C/SPI Jumpers MCU (U8) to DUT
6 D16 D16 Power LED – LMK61E2 OSC (U7)
7 TP3 TP3 DUT VDD supply
8 TP6 TP6 U3 LDO1 supply (3.3V) to DUT VDD pins
U3 LDO2 supply to DUT VDDO pins
9 TP7 TP7
(1.8/2.5/3.3 V, selectable via JP7)
10 TP5 TP5 U4 LDO3 (3.3V) supply to onboard OSCs
11 D6 D6 Power LED – 10 MHz TCXO (Y2)
12 D10 D10 Status LED – MCU USB I/F
13 D5 D5 Power LED – 48.0048 MHz XO (Y1)
14 S3 S3 DUT PDN/Reset switch
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EVM Default Jumper Settings
Before powering EVM, verify the following. See Appendix for visual of jumper placements.

– JP1, JP2, JP3, JP7: Short pins 1-2 to use onboard LDOs 1,2 (U3) to power the DUT.
• DUT VDD = 3.3V, VDDO = 1.8V. Assumes board input (VIN1) powered by 5V ext. supply.

– JP4 (*JP27), JP25: Short pins 1-2 to use LDO3 (U4) to power onboard TCXO and XO.

– JP6 (*JP29): Short pins 2-3 to disable power to onboard LMK61E2 osc (unused by default).

– JP24: Short pins 2-3 for LMK05028 to start-up in EEPROM+I2C Mode.

– JP5 (*JP28): Short pins 1-2, 3-4, 11-12, and 13-14 to route I2C and GPIOs from MCU to DUT.
• I2C is the default selected protocol for EVM and GUI.

*Indicates Jumper label for Pre-production EVMs

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Default EVM Configuration with Frequency Plan
IN[0:3] LMK05028 (U5)
• The default configuration TCXO (Y2) 25 MHz S-E to DPLLs 1,2 DPLLs 1,2
10 MHz S-E 3-loop mode
shown here was pre- to DPLLs 1,2 DPLL BW = 10Hz
programmed to the device (on bottom) TCXO BW = 600Hz
EEPROM.

OUT[0:3] OUT[4:7]
• Before programming a new 122.88 MHz 156.25 MHz
AC-LVPECL AC-LVPECL
configuration, it is from PLL2 from PLL1
recommended to verify the
default configuration is XO (Y1)
working as intended. 48.0048 MHz S-E
to DPLLs 1,2
(on bottom)

• A new device configuration GPIO 5,6 LEDs (on)

DPLL 1,2 Holdover active VIN1 (J1.1)
can be re-programmed 5V ext. supply
using TICS Pro GUI tool. STAT 0,1 LEDs (on) and GND 5
DPLL 1,2 Loss of Lock
EVM Quick Start
To evaluate the Default EVM configuration:

1. Verify the default jumper settings.

2. Connect a 5V supply to VIN1 (J1.1 and GND) with current limit to 1 A.

3. Verify LEDs D12/D13 are off (DPLLs Locked), D8/D9 are off (DPLLs not in holdover).

4. Connect the DPLL clock input(s) to the any INx_P/N SMA ports.
• With no clock input, the clock outputs will free-run from the onboard OSC.

5. Verify LEDs D12/D13 are off (DPLLs Locked), D8/D9 are off (DPLLs not in holdover).

6. Observe any active output clocks on OUT0-7 SMA ports

• A balun is recommended for interfacing DIFF clock outputs to the single-ended input of RF test equipment, such as phase noise
analyzers (SSA), for best results.
– Suggested SSA: Keysight E5052B, Rohde & Schwarz FSWP/FSUP
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EVM Test Setup Example
• For precise frequency measurements and evaluation of PLL lock, it is recommended for the
signal generator and signal measurement equipment to be locked to a common 10 MHz Ext Ref.
• Terminate unused active output with 50 ohm loads or disable output to minimize output noise coupling.
10 MHz Ext Ref Out

Ext
O-scope
Ref In

Sig Gen
Ext
Ref In
Freq Counter

Power Supply
Balun

+5V

Win PC w/ TICS Pro

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TICS Pro GUI Installation Guide
Windows 7+ (one-time step)
1. Download & Install TICS Pro GUI software v1.6.7 (beta)
– https://
sps08.itg.ti.com/sites/spsgroup/Customer/Shared%20Documents/LMK05028%20PG2%20EVM-GUI%20Collateral%20fo
r%20Field/TICS_Pro_Installer.zip

2. (web) Download & Install MATLAB Runtime v9.0 (2015b, 64-bit)

– https://www.mathworks.com/supportfiles/downloads/R2015b/deployment_files/R2015b/installers/win64/MCR_R2015b_w
in64_installer.exe
– This is required to run the compiled Matlab script bundled with the device profile.

3. Download the device profile LMK05x28-ENGINEERING.zip (pre-release)

– https://
sps08.itg.ti.com/sites/spsgroup/Customer/Shared%20Documents/LMK05028%20PG2%20EVM-GUI%20Collateral%20fo
r%20Field/LMK05x28-ENGINEERING.zip
– No need to un-zip file.
– Customers: Please contact TI Field Apps or appscts@list.ti.com to gain access to this pre-release s/w.

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4. Launch TICS Pro, and Import device profile:
– Select Device > Import User Device, then select LMK05x28-ENGINEERING.zip from Step 3.
LMK05028 GUI Workflow
• The following workflow will walk-through the steps to configure the DUT on the
EVM using TICS Pro.

• The default device EVM configuration (already pre-programed to the

LMK05028) is used as an example for this workflow.

• This workflow should be used to generate and program a new device

configuration.

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Request a LMK05028 configuration file (.tcs)
before getting started with TICS Pro
• If needed, email appscts@list.ti.com to request an Excel form to specify the device configuration, and
return the completed form. TI will reply with a custom .tcs file to Load in TICS Pro for evaluation.

Example

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LMK05028 GUI Workflow Overview
Detailed steps in the following slides
1. Select Device > User Devices > 3A
3A 22 11 44
LMK05x28-ENGINEERING
2. Set-up Communication (I2C/SPI)
3. Configure Device in Main:Start Page 3B
3B
A. Load Existing: File > Load > Open .tcs file, or
B. Start New: In Main: Start Page,
i. Do Steps 1 to 5:
– XO, TCXO, Clock Inputs & Outputs
– Clock Input & Output Assignments
– DPLL Settings
ii. Do Step 6: Run Script
iii. Do Remaining Steps:
– Clock Input Validation
– DPLL Lock Detect
– Zero Delay Mode
– DCO Mode controls
– STATUS outputs (in User Controls)
4. Program Device
A. Click Write All Registers
B. Click Soft-reset Chip
C. Verify proper operation; else, Go back to 3B.
D. Click Program EEPROM
A. On next POR cycle, device should auto-start. 11
Set-up Communication
1. Click USB Communications > Interface
2. In Communication Setup:
1. Tick USB2ANY in Interface
2. Choose Protocol: I2C or SPI_CLKLOW
3. Follow Change Device Mode & Protocol dialog:
1. Set EVM Jumpers accordingly for I2C or SPI.
2. Click Yes to confirm change, or No to cancel.
4. Press Close to apply Mode/Protocol changes.
3. Follow dialogs:
1. Scan I2C Bus (I2C only) – No to skip
2. Write All Registers – No to skip

• Default I2C device address:

– 0x00: Initial PG2.1 silicon
– 0x60: Later PG2.1 silicon with GPIO[2:1] pins = 00b upon
POR
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NOTE: JP5 is labeled JP28 on Pre-production EVMs

Step 1: XO and TCXO Inputs
• Enter XO and TCXO frequencies.
These were set to 48.0048e6 and 10e6
to match the onboard oscillators.

• XO Mode allows the user to configure

input buffer for DIFF/SE or CMOS.
– DIFF/SE is recommended, even for
single-ended XO input signal.

• Interface Type can be selected when XO Mode is DIFF/SE.

– AC-DIFF(ext. term) is the used since the EVM has onboard termination & AC-coupling to XO_P
input pin.

• TCXO Doubler and MDIV are typically set as shown.

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Step 2: Clock Inputs
• Enter Frequencies for any Clock Inputs
to be assigned to a DPLL.
– All frequency text inputs accept math
expressions. E.g. mixed numbers, fractions,
scientific notation, or combination of these to
maintain precision (avoid rounding errors).

• Set DPLL Assignments: Unused, DPLL1, DPLL2, or DPLL 1,2

– If Unused is selected, Clock input will be skipped in the frequency planning computatons.

• Interface Type can be selected for the input coupling and termination required.
– On the EVM, SMA input ports are DC-coupled to the IN[0:3]_P/N pins of DUT.

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Step 3: DPLL Input Clock Selection
• For each DPLL, configure the Input Select Modes.
– For either Auto or Manual Fallback modes, configure Input Select Priority as well.
• Input Select Mode:
– Auto non-revertive – Selects the highest priority
valid clock. If a higher priority clock goes valid,
it does not switch until the currently selected
clock goes invalid.
– Auto-revertive – Always selects the highest priority
valid clock. If a higher priority clock goes valid,
it will immediately switch to that clock.
– Manual Fallback – Selects the clock chosen by the
manual select mode (SW register or HW pin control)
when valid. If it goes invalid, the next highest priority
valid clock is selected per the priority table.
– Manual Holdover – Selects the clock chosen by the
manual select mode (SW register or HW pin control)
when valid. If it goes invalid, then it enters holdover
mode regardless of other clock inputs.
• If Priority is Ignore, the input cannot be selected
by Auto or Manual Fallback modes.
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Step 4: Clock Outputs
• Assign Frequency, Channel Mux,
and Interface Type to Clock Outputs.

• Output frequency constraints:

– OUT[4:7] bank requires at least
one clock from PLL1.
– OUT[0:3] bank requires at least
one clock from PLL2 (if PLL2 used).
– This is enforced by the GUI

• As outputs are assigned, the PLL VCO frequencies will be computed & displayed (in Step 5)
and achieved output frequencies will be displayed.
– If output frequencies cannot be supported by VCO, the corresponding frequencies will reset to 0.
• In this case, try assigning the outputs to the other PLL domain, or eliminate one or more frequencies until a
valid VCO frequency is found.
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Step 5: DPLL/DCO Configuration (1 of 3)
• For each DPLL, configure DPLL Mode, Market
Segment, Loop BW for REF and TCXO loops.
– These determine the “DPLL optimization goals”.
– See table below for help to configure these settings.

Market
DPLL Mode Suggested LBW (per Application) DPLL Optimization Goals
Segment
• 1~10 Hz (SyncE EEC Opt. 1 • Jitter/wander filtering, Holdover
3 loop
• 0.1 Hz (SyncE EEC Opt. 2) SyncE/SONET • Hitless switching enabled
2 loop REF • 10~100 Hz (Jitter cleaning only with XO holdover) • REF TDC~400 kHz

3 loop • 1~20 Hz • Best close-in phase noise

• Jitter/wander filtering, Holdover
2 loop REF or Wireless/BTS
• 10~300 Hz • Hitless switching enabled
2 loop TCXO • REF TDC maximized
• OTN/OTU: 100~300 Hz • Jitter attenuation
2 loop REF • Broadcast/Genlock: 1~10 Hz OTN/JitterAttn • Hitless switching disabled
• Jitter cleaning: 10~100 Hz • REF TDC~1 MHz
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Step 5: DPLL/DCO Configuration (2 of 3)
• REF (DPLL) Loop BW*
– 2 loop: 10~300 Hz
– 3 loop: 0.01~20 Hz
• Optimal DPLL LBW depends on relative phase noise
between REF and XO (for 2 loop) or TCXO (for 3 loop)

• TCXO Loop BW*

– 2 loop: 100~400 Hz
– 3 loop: (200 x REF LBW)~2000 Hz
• Min. TCXO LBW is restricted to 200x REF LBW by the GUI for stability
• Optimal TCXO LBW depends on relative phase noise between TCXO and XO

• OPTIONAL: VCOx Freq and/or PLLx P1 (VCO primary post-divider) controls can be directly entered to force / override the values
computed during Step 4.
– Possible reasons for this:
• Avoid VCO frequency when an integer multiple of XO frequency (fractional APLL mode is required for DPLL operation)
• This could the user to force another valid frequency plan option that was not computed
– NOTE: If PLLx P1 is changed, click in the VCO* Freq text input and press “Enter” key to apply the change.

*Suggested ranges for REF & TCXO LBW. Other possibilities are available. 18
Step 6: Run Script
• Run script and allow a moment for the Matlab
script to compute DPLL settings & write registers
– A shell will display the script activity.
– If desired, close the shell to abort the script.

• IMPORTANT: In Start Page, if one or more controls labeled in

red text is changed, the script must be run again to affect changes.

• After script is done, it is recommended to click Write All Registers

then Soft-Reset Chip to ensure EVM and GUI are synced.
– Subsequent changes should be written dynamically.
– Soft-reset may be needed if the DPLL or APLL configuration has changed, or DPLL loop saturated.

• Steps 7 and higher do not require the script to be run when changes are made.
– The registers associated with these steps require Steps 1-6 to have been done and not be changed after running the script.
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Step 7: Tuning Word History
• History Count sets the time window (THISTCNT) to
allow updates to the tuning word history that reflects
the average frequency while locked.
– The history, if valid, sets the holdover frequency.
– History is valid as soon as the DPLL is locked for longer
than THISTCNT.

• History Delay sets the time window (THISTDLY) to

prevent updates to tuning word history just prior
clock input LOS event.
– This is used to avoid corrupting history data which may
occur while the clock input is failing.

Holdover Flowchart

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Step 8: Clock Input Validation (1 of 2)
• A DPLL input can only be selected if considered “ valid” per criterion set by the input detectors.
• Clock input detector thresholds can be set and enabled per input. If not enabled, its flag is ignored.
– Amplitude Detector (not shown; enabled by default)
– Frequency Detector
– Missing / Late Clock Window Detector
– Early Clock Window Detector (aka Runt pulse monitor)
• Validation Timer sets the minimum time for all enabled detectors to be clear of flags before an input
is set valid and its loss-of-signal status is cleared (LOS=0).
– The validation timer starts counting once all enabled detector flags are cleared.
– When any enabled detector sets a flag, the validation timer will be reset and LOS will be set (LOS=1).

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Step 8: Clock Input Validation (2 of 2)
• Amplitude Detect will clear its flag when the input swing is above the programmable MIN swing setting.
• Frequency Detect will clear its flag when the input frequency is within the Valid ppm setting. It will set its flag when
beyond the Invalid ppm setting.
– Avg can be set to adjust the measurement accuracy of the input frequency at the expense of measurement time, TMEAS-FDET.
– A higher Avg setting may be needed to avoid false flags when the input has large wander.
– Input frequency is measured relative to the selected “0ppm” comparison clock. This is the XO input unless the TCXO input is used.

• Missing Clk Window will clear its flag when the input clock edge arrives before its nominal clock period + T LATE.
– Set Late Clks so that TLATE is slightly higher than the longest expected input clock period.
– If the input clock edge arrives later than (Input period + TLATE), then the missing clock flag will be set (invalid).

• Early Clk Window will clear its flag when the input clock edge arrives after its nominal clock period – T EARLY.
– Set Early Cnt so that TEARLY is slightly lower than the shortest expected input clock period.
– If the input clock period arrives sooner than (Input period – TEARLY), then the early clock flag will be set (invalid).

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Step 9: Frequency Lock Detect
• DPLL Frequency Lock Detect will clear its flag (LOL=0) when the DPLL frequency is
within the Lock ppm setting. It will set its flag (LOL=1) when it exceeds the Unlock ppm
setting.
– Lock Avg and Unlock Avg can be set to adjust the Lock and Unlock measurement accuracy of the DPLL’s
frequency at the expense of measurement time, TMEAS-LOCKDET and TMEAS-UNLOCKDET.
– Lock Avg is typically set higher to increase accuracy.
– Unlock Avg is typically set lower to minimize latency of flagging a LOL condition.

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Step 10: Zero Delay Mode (ZDM)
• When enabled, ZDM cancels the phase difference between the selected DPLL
output clock and the DPLL clock input edge.

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Step 11: DCO Freq. Control
• In Step 5, if 2 loop:TCXO+APLL mode was selected
and DCO Step Size (ppb) value was specified,
Run Script should compute the FDEV register
corresponding to desired ppb step size.
– FDEV register can also be directly changed

• When DCO mode is Enabled, clicking Incr. or Decr.

buttons adjust the DPLL’s output clocks by the
ppm step size corresponding to FDEV value.
– Incr/Decr can done via Register or GPIO pin control.
– If GPIO control is selected, the following bits should be
pre-configured in User Controls :
• GPIO[3:6]_FDEV_EN = 1 (in STATUS group)
• DPLL[1:2]_IGNORE_GPIO_PIN = 0 (in DPLLx CTRL group)
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STATUS Displays & Controls in User Controls
• Click Read Status Regs to update the
Status register displays (in red boxes)
– INT LIVE[0:2] (read only) display
various status bits for XO, TCXO, APLL,
DPLL, or DPLL Input detector flags.
– REF VALID (read only) display
which inputs are valid based on input
detector flags: 0 = Invalid, 1 = Valid
– REFSEL STAT (read only) display
which DPLL input is currently selected or
if the DPLL is in holdover state

• Configure the Status output pin controls

(in blue boxes):
– STAT SEL controls select the status output
signal to the status pins: STAT 0/1, GPIO 5/6
– OUTPUT TYPE controls select the output type
• CMOS or Open-drain
– STAT POL controls select the output polarity
• 0 = Active high, 1 = Active low 26
STATUS Controls in User Controls (cont’d)
• INT MASK allows the specified interrupt source to be masked, so that it will not
cause the interrupt flag to be raised

• If an interrupt flag is raised, manually

uncheck (clear) the flag bit before
reading the status registers again;
otherwise, the flag bit will stay set
even if the interrupt live was not set.

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Advanced: APLLs Page
• APLL pages allow manual adjustment of loop filter settings (if needed)
– Default Loop filter & Charge pump settings are optimized for 48~54 MHz low-jitter XO.
– These should be re-optimized if using an XO with lower frequency and/or higher jitter.

• PLL Mode Control has debug

options:
– Powerdown APLL: PLL1_PDN=1
– Free-run APLL: PLLx_MODE=1
(decouples APLL from DPLL loop)

• DO NOT change APLL Frac-N Div

or XO Doubler settings
– These are computed by Run Script
– APLL/DPLL can un-lock if changed
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Advanced: Outputs Page (1 of 2)
OUT DIV = MSB * LSB
• Outputs page allows manual changes
to VCO post-div and output dividers,
and configuration of output slew rate
(Fast or Nom only) and SYNC features.

– PLL Post-Div and Output Div

values should be set via the
Frequency Planner during Step 5
on the Start Page.

– OUT0 & OUT7 have cascaded

dividers to support low-freq outputs
down to 1 Hz (1 PPS).
• OUT DIV = MSB * LSB

– NOTE: If channel divider or

powerdown bits are manually
changed here, they do not
get reflected on the Start Page.
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Advanced: Outputs Page (2 of 2)
• Output Sync can be enabled to phase-align multiple output channels sourced from the
same PLL post-divider P1 (PRI) or P2 (SEC) after a SYNC event is triggered.

– Example 1: To enable sync on OUT0 &

OUT1 from PLL2 P1, set these bits:
• CH0_SYNCEN=1
• CH1_SYNCEN=1
• PLL2_PRI_CH03_SYNC_BNK=1
• Toggle SYNC_SW to trigger SYNC

– Example 2: To enable sync on OUT4/5 &

OUT6 from PLL1 P1, set these bits:
• CH45_SYNCEN=1
• CH6_SYNCEN=1
• PLL1_PRI_CH47_SYNC_BNK=1
• Toggle SYNC_SW to trigger SYNC 30
Programming the EEPROM
• After the user has confirmed the device configuration is correct on the EVM and
ensured all register are written to the device, the user can click Program
EEPROM so that the chip can auto-start with this configuration on the next
power-on/reset cycle.

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Appendix

32
Default Power Jumper Settings
Onboard LDO Power for XO and LMK61E2 Power
DUT and OSCs XO power on

LMK61E2 power off

TCXO Power

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Device Mode and MCU-DUT Jumper Settings
EEPROM + I2C Mode (Default) EEPROM + SPI Mode
Short SDA,SCL Short SCK,SIMO,SOMI,SCS

Pre-prod EVM
Short pin 2-3
Short pin 2-3
on JP24
on JP24

Final EVM
Float pin 2
on JP24

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Typical Output Waveform (156.25 MHz Output)

35