Assembly Language Programming

15EEE314
Microcontroller and Applications
 Addition
• Addition of two numbers 0110 1100
• Requirement Operand 1 1011 0010
– Memory locations to store two operands Operand 2 1001 0110
– Memory location to store sum and carry
1 0100 1000
• PIC16F877A
– Default Bank selected: BANK0 CARRY SUM
– User Accessible Locations: 0x20 to 0x7F
• Assign
– 0x20  SUM
– 0x21  CARRY

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 Addition – Immediate Addressing
• Move Operand1  Work register Operand1: 1011 0010
– Work register loaded with first operand 0xB2
• Add Operand2 with the content of Work Register Operand2: 1001 0110
– Operand1 + Operand2  Destination 0x96
• Work Register is the destination (Immediate addressing)
– SUM is present in Work Register CLRF 0x20
• CARRY is present as C in STATUS Register CLRF 0x21
MOVLW 0xB2
• Push the content of SUM and CARRY to Data Memory
ADDLW 0x96
MOVWF 0x20
BTFSC STATUS,0
INCF 0x21,1

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 Addition – Immediate Addressing
#include<p16f877a.inc> Header file containing  Register Mapping
ORG 0x00
GOTO start Unconditional Branch
start ORG 0x05 Set Program Origin
CLRF 0x20
CLRF 0x21
Assembler Directive: Directives are assembler
MOVLW 0xB2 commands that appear in the source code but are not
ADDLW 0x96 translated directly into opcodes. They are used to
MOVWF 0x20 control the assembler: its input, output, and data
BTFSC STATUS,0 allocation.
INCF 0x21,1
loop GOTO loop
END Indicates the end of the program's source code
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 Addition – Immediate Addressing
#include<p16f877a.inc>
ORG 0x00
GOTO start
start ORG 0x05 1 Margin
CLRF 0x20
CLRF 0x21
1 MOVLW 0xB2 2 Label Indent
ADDLW 0x96
MOVWF 0x20
BTFSC STATUS,0
INCF 0x21,1
3 Program Area
loop GOTO loop
END

2 3

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 Program Memory
#include<p16f877a.inc> ADDRESS CONTENT

ORG 0x00 0x00 GOTO start Reset Vector

GOTO start 0x01
start ORG 0x05 0x02

CLRF 0x20 0x03

CLRF 0x21 0x04

0x05 (start) CLRF 0x20 Interrupt Vector
MOVLW 0xB2
ADDLW 0x96 0x06 CLRF 0x21
MOVWF 0x20 0x07 MOVLW 0xB2
BTFSC STATUS,0 0x08 ADDLW 0x96
INCF 0x21,1 0x09 MOVWF 0x20
loop GOTO loop 0x0A BTFSC STATUS,0
END 0x0B INCF 0x21,1
0x0C (loop) GOTO loop

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 Addition – Direct Addressing
• Operands are supplied in the Data Memory
• Labels can be used to identify specific memory locations
• Assign
– 0x20  OP1 (operand 1)
– 0x21  OP2 (operand 2)
– 0x22  SUM
– 0x23  CARRY
• Since sequential memory locations are required, CBLOCK directive can be used
– To complete the label assignment ENDC directive (End an Automatic Constant Block) is used
• For non-sequential memory locations EQU directive can be used

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 Addition – Direct Addressing
#include<p16f877a.inc>
CLRF SUM
CBLOCK 0x20
CLRF CARRY
OP1
MOVF OP1,0
OP2
ADDWF OP2,0
SUM
MOVWF SUM
CARRY
BTFSC STATUS,0
ENDC
INCF CARRY,1
ORG 0x00
loop GOTO loop
GOTO start
END
start ORG 0x05

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 Subtraction
Binary 2’s Complement 0x05 - 0x03 0101 0x03 - 0x05 0011
0x05 0101 1011 = +0x02 1101 = -0x02 1011
0x03 0011 1101 Actual Result 1 0010 Carry 0 1110 2’s C

Carry Actual Result 0010

0xA4 - 0x62 0x62 - 0xA4

= +0x42 = -0x42

Binary 2’s Complement 1010 0100 0110 0010

0xA4 1010 0100 0101 1100 1001 1110 0101 1100
0x62 0110 0010 1001 1110 Actual Result 1 1100 0010 Carry 0 1011 1110 2’s C
Carry
Actual Result 1100 0010
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 Subtraction
#include<p16f877a.inc> Comp COMF Diff,1; 1’s complement
CBLOCK 0x20
INCF Diff,1; 2’s complement
num1
INCF Borr,1; ack borrow
num2
Diff RETURN
Borr loop GOTO loop; infinite loop
ENDC END
ORG 0x00
MOVF num2,0
SUBWF num1, 0; W= num1- W
MOVWF Diff
BTFSS STATUS,C
CALL Comp
GOTO loop
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Accessing Successive Memory Locations – Array 1
• Clear 8 successive locations starting from 0x20 - Indirect addressing mode

MOVLW 0x20
MOVWF FSR
MOVLW 0x08
MOVWF count
L1 CLRF INDF
INCF FSR,1
DECFSZ count,1
GOTO L1
Lp GOTO Lp
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Accessing Successive Memory Locations – Array 2
• Clear 8 successive locations starting from 0x20 - Indirect addressing mode

MOVLW 0X08
MOVWF VALUE INCF COUNT,1
MOVF COUNT,0
MOVLW 0X20
XORWF VALUE,0
MOVWF FSR BTFSS STATUS,Z
MOVLW 0X00
GOTO L1
MOVWF COUNT
LOOP GOTO LOOP
L1 CLRF INDF
INCF FSR,1

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 Count Down Loop – 8 Bit
• Continuously count down from 4 till 0

Org 0x00
L2 MOVLW 0x04
MOVWF 0x30
L1 DECFSZ 0x30,1
GOTO L1
GOTO L2

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 Count Down Loop – 16 Bit
CBLOCK 0x25 L1 DECFSZ N_low,1
N_low GOTO L1
N_high MOVF N_high,0
ENDC BTFSC STATUS,Z
ORG 0x00 GOTO Lp
MOVLW 0x01 DECF N_high,1
MOVWF N_high MOVLW 0xFF
MOVLW 0x0A GOTO L2
L2 MOVWF N_low Lp GOTO Lp

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 Multiplication – 8 Bit
CBLOCK 0x20 MOVWF Multiplicant
Count MOVF Multiplier,0
Multiplier =3 Multiplier
Multiplicant = 4 BTFSC STATUS,Z
Multiplicant GOTO LP
Product_msb MOVF Multiplicant,0
Count = 3
Product_lsb BTFSC STATUS,Z
ENDC GOTO LP
4 is added 3 times
ORG 0x00 Loop ADDWF Product_lsb,1
CLRF Product_msb BTFSC STATUS,C
CLRF Product_lsb INCF Product_msb,1
MOVLW 0x03 DECFSZ Count,1
MOVWF Count GOTO Loop
MOVWF Multiplier LP GOTO LP
MOVLW 0x04
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 Division
Dividend = 5 , Divisor = 2, Q =0 , Rem = 0

Dividend= dividend – divisor

Dividend = 5-2 =3 ; C=1 indicating no borrow
Check C flag for borrow, if no borrow then increment quotient and repeat; Q=1
Dividend= 3-2 =1 ; C=1  no borrow so increment quotient Q=2
Dividend= 1-2 = FF ; 2’s complement addition, C=0  borrow present
 Division is over
 Dividend = FF
 Remainder = dividend + divisor
 Rem= FF + 2 = 1
 5/2 Q=2, Rem =1
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 Division
#include<p16f877a.inc> GOTO LP
CBLOCK 0x20 Loop SUBWF dividend,1 ; div = div-divisor
dividend BTFSC STATUS,C ; check no borrow
divisor
INCF quotient,1
quotient
BTFSS STATUS,C ; borrow exist
remainder
ENDC GOTO out
ORG 0x00 GOTO Loop
MOVLW 0x05 Out CLRW
MOVWF dividend MOVF dividend,0
MOVLW 0x02 ADDWF divisor,0
MOVWF divisor MOVWF remainder
CLRF remainder
LP GOTO LP
CLRF quotient
END
MOVF divisor,0
BTFSC STATUS,Z
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 Watch Dog Timer (WDT)
• Safety mechanism to recover from software/hardware faults.
• It is a timer , that runs in the background using a dedicated clock for reliability. For
each cycle, the timer register increments.
• If the timer overflows i.e exceeds the maximum count , it is considered as a fault and
microcontroller resets as to recover.
• The user program has to take care of WDT.
• The programmer should know when the WDT will overflow( after how many
instructions) and CLRWDT instruction should be used. So that WDT is cleared and
reinitialized to 0.
• WDT as a feature could be enabled or disabled.
• In PIC16f877a WDT uses an internal RC oscillator for reliable operation.
• WDT is independent of the Crystal oscillator
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 Watch Dog Timer (WDT)
• If the program has infinite loops - the controller will be executing the infinite
loop, but the WDT will still continue to increment and overflow, resulting in a
reset.
• Such cases you can disable WDT , as the infinite loop is intentionally put by the
programmer.

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 SLEEP
• Dedicated instruction for SLEEP mode.
• Power saving.
• Microcontrollers goes to sleep mode suspending all the activities.
• The external crystal oscillator is not used, saving power.
• Few peripherals could be working, based on internal RC oscillator.
• Wake up from SLEEP could be initialized through an external interrupt.
• WDT can wake up the device from SLEEP mode. ( not as a reset, instead as wake
up)
• Some peripherals can also wake the device.
• Eg. UART- serial communication module.
• If the peripheral receives a bit from another device, it wakes up PIC.
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 STATUS- register

TO - time out bit (bar) – logic is inverted

= 1 after power up , CLRWDT instruction, or SLEEP instruction
=0 indicates that a WDT time out has occurred.
After power up i.e the microcontroller has turned on this bit is set as 1,
CLRWDT and SLEEP instruction also sets this bit.
PD – power down bit (bar) – logic is inverted
= 1 after power up, CLRWDT instruction
=0 when SLEEP is executed

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Time Delay in Software

• A bit in selected location (A) is cleared after the delay

• A number N_Dly is loaded into a scratchpad register B
• The number is decremented continuously until it becomes 0
• Once the B  0, the selected bit (in A) is set to 1
• The bit in A location remains at 0 for the definite period of
time of execution of the routine

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 Time Delay in Software
A EQU 0x30
B EQU 0x31
Note: During the execution of routine, µc is tied up and cannot
N_Dly EQU 0x20 execute any other activity
ORG 0x00 Resources are wasted but can be justified if µc does not have
any other task to perform
BCF A,7
MOVLW N_Dly
Z=0 Z=1
MOVWF B
L1 DECFSZ B,1 1 ins cycle 2 ins cycle
GOTO L1 2 ins cycle
BSF A,7
LP GOTO LP
END
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 Time Delay in Software - Calculation
Time delay for 7th bit of A remains 0
A EQU 0x30
B EQU 0x31 Number of Instruction cycles = 3 + ((N_Dly – 1)*3) + 2
N_Dly EQU 0x20
ORG 0x00
BCF A,7 1 ins cycle
MOVLW N_Dly 1 ins cycle
MOVWF B 1 ins cycle
L1 DECFSZ B,1 1 ins cycle 2 ins cycle
GOTO L1 2 ins cycle
BSF A,7
LP GOTO LP
END
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 Time Delay in Software - Calculation
Time delay for 7th bit of A remains 0
N_Dly = 0x20 = (32)d
1. Number of Instruction cycles for loop (exactly)
= [(N_Dly-1)(1+2)] +2 = (31*3)+2 = 95
Number of Instruction cycles for outside loop = 3
Total Number of Instruction cycles = Number of Instruction cycles for loop +
Number of Instruction cycles for outside loop = 95+3 = 98

1 IC= 1 instruction cycle = 4 clock cycles

  If Oscillator Frequency ,Fosc = 4MHz

Frequency of IC = ,

  Delay time = No of Instruction cycles * = 98* = 98 25

 Time Delay in Software - Calculation
Time delay for 7th bit of A remains 0
N_Dly = 0x20 = (32)d
2. Number of Instruction cycles for loop (approximate)
= [(N_Dly)(3)] = (32*3) = 96
Number of Instruction cycles for outside loop = 3
  Delay time = No of Instruction cycles * = 99* = 99

Difference between the exact time delay and approximate time delay is just 1µs
So for rapid calculation, the later method is used

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 Time Delay in Software with NOP
A EQU 0x30
B EQU 0x31 Number of instruction cycles for 7th bit in A to remain 0
N_Dly EQU 0x20 = 5*N_Dly + 4
ORG 0x00 Inside Outside
+
BCF A,7 Loop Loop
MOVLW N_Dly
MOVWF B Z=1
Z=0
NOP
L1 NOP 1 ins cycle 1 ins cycle
NOP
1 ins cycle 1 ins cycle
DECFSZ B,1
1 ins cycle 2 ins cycle
2 ins cycle
GOTO L1
BSF A,7
LP GOTO LP
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END
Time Delay in Software – Longer Delay
• Delay by decrementing 16-bit number to 0
• Nested loops
• Inner loop : decrement M to zero
• Outer loop : every time NL goes through 0
• decrement NH
• Delay = NH  (256  3+3) instruction cycles ~
approximately

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 Time Delay in Software – Longer Delay
N_Dly_H EQU 0x30 L2 MOVWF N_l
N_Dly_L EQU 0x31 L1 DECFSZ N_l,1
CBLOCK 0x20 GOTO L1
A, N_l, N_h DECFSZ N_H,1
ENDC GOTO L2
ORG 0x00 BSF A,7
BCF A,7 LP GOTO LP
MOVLW N_Dly_H END
MOVWF N_h  
Number of instruction cycles = NH  ((NL  3)+4) ~
MOVLW N_Dly_L approximately
Delay time = No of Instruction cycles *
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Time Delay in Software – Slightly Longer Delay
N_Dly_H EQU 0x30 MOVWF N_l
N_Dly_L EQU 0x31 L1 DECFSZ N_l,1
CBLOCK 0x20 GOTO L1
A, N_l, N_h DECFSZ N_H,1
ENDC GOTO L1
ORG 0x00 BSF A,7
BCF A,7 LP GOTO LP
MOVLW N_Dly_H END
MOVWF N_h  
Number of instruction cycles = NH  ((256  3)+3) ~
MOVLW N_Dly_L approximately
Delay time = No of Instruction cycles *
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 Subroutines
• Specific task to be executed repeatedly at different stages of program.
• Similar to the concept of functions in C

Process:
1. Halt main program, provide returning
2. Transfer control to subroutine
3. Execute subroutine
4. Return to main program execution

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Subroutines

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 Interrupt
• Several peripherals capable for generating interrupts.
• PIC has a single interrupt line.
– Interrupt lines from different peripherals and external interrupts are connected to a
single line.
• Each interrupt has  associated interrupt flag
• Global Interrupt Enable (GIE) master control for interrupts.

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 Interrupt
External Interrupt

Interrupt line IRQ

Processor IRQ IRQ IRQ IRQ

P1 P2 P3 P4

P – peripheral interrupts ( internal interrupts)

IRQ- interrupt request
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Interrupt Process

Similar to subroutine call, when an interrupt is

Encountered

1. Main program halted

2. PC loaded to STACK
3. PC loaded with interrupt vector ( 0x04)
4. Execute ISR
5. Load PC with address from stack
6. Return to main program

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Interrupt Mask

PIR- peripheral interrupt Register

PIE- peripheral interrupt enable
T0IF= timer0 interrupt flag
T0IE= timer0 interrupt enable

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 Interrupt Instructions
• Returning from Interrupt
– RETFIE
• Return from ISR, with GIE=1
• Widely used
– RETURN
• Normal return from ISR

Note: On detecting an interrupt, the first step in ISR is to disable

GIE (GIE=0) so that during ISR execution , other interrupts are
not detected. Similarly, the last step in ISR will be GIE=1 to detect
further interrupts.

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IRQ and Response

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 Interrupt priority
• All the interrupts have same priority in PIC-except RESET.
• RESET is non-maskable.
• Priority is assigned while writing ISR.
– Which interrupt flag is to be checked first

function ISR( )
{
GIE=0;
Assuming peripheral A and peripheral B
If( intA_flag==1)
generated interrupt at the same time.
{ do …. }
if ( intB_flag==1)
In the ISR peripheral A is given high priority.
{ do…. }
GIE=1;
} EEE, Amrita School of Engineering 39
 Interrupt status saving
• Interrupt may come anytime
• It is advised to save the contents of Work register and STATUS register (as the
operations in ISR may alter the contents of W and STATUS)
• Saving the values are done as first steps in ISR, so that these values could be
loaded back once the ISR is completed
• The saved values could be used and main routine can continue execution
• Interrupt status saving should be done by programmer

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