BONAM VENKATA CHALAMAYYA INSTITUTE OF

TECHNOLOGY AND SCIENCE :: BATLAPALEM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

REALIZATION OF MULTIPLIER USING DELAY

EFFICIENT CYCLIC REDUNDANT ADDER

Under the Esteemed Guidance of

Mr.K.Srinivas, M.Tech.,MIETE
Associate Professor
Presented by:
N.S.S.Satya Lakshmi(14H41A0444)
A.Gouri Bhavani(14H41A0420)
M.Viswanadh Gowd(15H45A0409)
B.V.V.D.Saikumar(15H45A0404)
 ABSTRACT

 In this project, cyclic redundant adder which is fastest among all the
existing adders with the least delay of 1.091ns is discussed.

 The proposed cyclic redundant adder makes use of recursive doubling

technique which makes the computation of the adder fast by reducing
the delay.

 A multiplier is designed based on quarter square algorithm and

implemented using cyclic redundant adder.
 CONTENTS
 INTRODUCTION
 EXISTING SYSTEM
 PROPOSED SYSTEM
 PROJECT DESIGN FLOW
 GENERAL MULTIPLICATION
 EXISTING ADDER ARCHITECTURE
 CYCLIC REDUNDANT ADDER
 QUARTER SQUARE MULTIPLIER
 ARCHITECTURE
 RESULTS
 COMPARISION
 SOFTWARE TOOLS
 ADVANTAGES,DISADVANTAGE & APPLICATIONS
 CONCLUSION
 FUTURE SCOPE
 REFERENCES
 INTRODUCTION

To perform multiplication, adders are used. Adders are one of

the most crucial and irreplaceable circuits of any digital
system. For any digital circuit the parameters like delay, area
and power should be considered . To reduce the delay, the
proposed system uses cyclic redundant adder.
 EXISTING SYSTEM

 Adders are used in any digital system from a multiplier design to a

complex filter design for DSP applications.

 Generally the following adder is discussed in our system:

•Ripple carry adder - disadvantage is area and power

consumption is more in this adder. Execution time is also more
and circuit is complex.
 PROPOSED SYSTEM

 The proposed cyclic redundant adder is based on the simple

principle of a full adder circuit.
 In cyclic redundant adder, the carry is computed in parallel
manner, which makes the computation of the adder fast by
reducing the delay.
 In this system, we are using recursive doubling technique.
 The cyclic redundant adder is the fastest with the least time
delay of 1.09 ns.
PROJECT DESIGN FLOW
Existing techniques

Modelling of Cyclic Redundant Adder

VHDL code
Developed

simulation

Analysis of Results

Comparision with other methods

Conclusion
 GENERAL MULTIPLICATION

Multiplier is multiplied with multiplicand, produces product. For that, first

production of partial products takes place.
After generating partial products either directly or using smaller multipliers.
To obtain final product an adder is used.
Partial products have fewer bits than final product, and must be aligned before
added .
In order to modify that wrong we have to go for any algorithm.
 GENERAL MULTIPLICATION
ALGORITHM
X= Xn-1 Xn-2 …………………X0 Multiplicand
Y=Yn-1 Yn-2…………………….Y0 Multiplier

Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0

Yn-1X1 Yn-2X1 Yn-3X1 …… Y1X1 Y0X1
Yn-1X2 Yn-2X2 Yn-3X2 …… Y1X2 Y0X2
… … … …
…. …. …. …. …. PARTIAL PRODUCTS GENERATION
Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2

Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 …… Y1Xn-1 Y0Xn-1

-----------------------------------------------------------------------------------------------------------------------------------------
P2n-1 P2n-2 P2n-3 P2 P1 P0

ACCUMILATION
 EXISTING
ADDER ARCHITECTURE

RIPPLE CARRY ADDER:

A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary
numbers.
It can be constructed with full adders connected in cascaded , with the carry output
from each full adder connected to the carry input of the next full adder in the chain.
The interconnection of four full adder circuits to provide a 4-bit ripple carry adder.
In the ripple carry adder, the output is known after the carry generated by
the previous stage is produced.
 The sum of the most significant bit is only available after the carry
signal has rippled through the adder from the least significant stage to the
most significant stage.
As a result, the final sum and carry bits will be valid after a considerable
delay.
 CYCLIC REDUNDANT ADDER

Here the carry is computed in a parallel manner to reduce the delay.

This adder optimizes the parallel carry computation using the parallel prefix
circuit, which uses recursive doubling technique.
 RECURSIVE DOUBLING TECHNIQUE

If the current state is kill or generate, then the state in the next stage will also
be kill or generate respectively. If the current state is propagate then the
corresponding state in the next stage is given as ,
Next state = state of (current cell number –x)
The recursive doubling technique has to be done (r-1) times, (where r is the
number of bits),in the worst case when all states are propagate at initial stage.
The procedure can be terminated when all the states of the current stage are
generate or kill. The worst case recursive doubling technique is as follows
QUARTER SQUARE MULTIPLIER USING CYCLIC
REDUNDANT ADDER

(A+B)2 - (A-B)2 = 4AB

ARCHITECTURE
RESULTS OF MULTIPLIER USING RIPPLE CARRY ADDER
RESULTS OF MULTIPLIER USING CYCLIC REDUNDANT ADDER
 COMPARISION

DELAY

Existing adder Ripple carry 11.237 ns

adder
Proposed adder Cyclic 10.601 ns
redundant adder
 SOFTWARE TOOLS

The main tools used in the implementation of this project are:

 ISE from Xilinx 14.7

 Xilinx Isim tool for simulation

Xilinx XST for synthesis

 ADVANTAGES
The proposed system reduces the delay in computation of carry.

Efficiency of the proposed system is more.

DISADVANTAGE
In the proposed system, there is a Little bit increase in area.

APPLICATIONS
It is used in:
Multiplexer
FFT filter
DSP processors
 CONCLUSION

The structural model of the proposed cyclic redundant adder is

designed using VHDL and implemented on Xilinx ISE 14.7.

The proposed adder is found to be the fastest among all the existing
adders like ripple carry adder.
 FUTURE SCOPE

This system in future can be designed by reducing the

parameter power of about 30%.
 REFERENCES

Springer ,B.K.Kaushik et al.(Eds): Realization of multiplier using delay efficient cyclic

redundant adder.

Barak at m,saad, W,shokair, m, elkordy, M.: Implementation of efficient portable low delay
adder using FPGA. In:28th International conference on micro electronics ICM

 Suganya , R,meganathan,d: high performance VLSI adders.in:3rd international conference on

signal processing, communication and networking ICSCN.

https://doi.org/10.1007/978-981-10-74707_4

https://www.Springer.com/series/7899

Switching theory and logical circuits by Anand kumar.

VLSI Design-black book by Dr.K.V.K.K.Prasad,Kattula Shyamala.

THANK YOU

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