Professional Documents
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Computer System
Overview
BY: ZALINA AYOB
Operating System
Process I/O
or Modules
Main System
Memory Bus
Processor
Referred to as
the Central
Processing Unit
(CPU)
Main Memory
• Volatile
– Contents of the memory is lost
when the computer is shut
down
• Referred to as real memory or
primary memory
I/O Modules
storage (e.g.
hard drive)
Moves data
between the
computer and communication
external s equipment
environments
such as:
terminals
System Bus
–Provides for
communication among
processors, main memory,
and I/O modules
CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR
I/O AR
Data
Execution
unit Data
I/O BR
Data
Data
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
processor reads
(fetches) processor executes
instructions from each instruction
memory
Two steps
Fetch Stage Execute Stage
• Processor interprets
Fetched instruction is the instruction and
loaded into Instruction performs required
Register (IR)
action:
– Processor-memory
– Processor-I/O
– Data processing
– Control
Fetch Stage Execute Stage
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6
1 4 1 4 1 4
Interrupt Interrupt
2b Handler Handler
5 5
Figure 1.5a
WRITE WRITE WRITE
END END
3a
3 3
3b
Flow of Control
(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait
Without Interrupts Figure 1.5 Program Flow of Control Without and With Interrupts
User I/O User I/O User I/O
Program Program Program Program Program Program
1 4 1 4 1 4
Figure 1.5b
2 2
Interrupt Interrupt
2b Handler Handler
END END
3a
3 3
3b
1 4 1 4 1 4
Figure 1.5c
2a
END
2 2
Interrupt Interrupt
2b Handler Handler
END END
3a
3 3
3b
(a) No interrupts
WRITE
i
Interrupt
occurs here i+1
Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START initiate interrupt
instruction instruction
Interrupts
handler
Enabled
HALT
1 1
4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
1 1
4 4
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction
Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt
Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y + L Return Routine T Y + L Return Routine T–M
Stack Stack
Pointer Pointer
Processor Processor
T–M T
N User's N User's
N+1 N+1
Program Program
Main Main
Memory Memory
An interrupt occurs
while another
Two approaches:
interrupt is being
processed
• e.g. receiving data • disable interrupts
from a while an interrupt is
communications line being processed
and printing results at • use a priority scheme
the same time
Interrupt
User Program Handler X
Interrupt
Handler Y
Interrupt
User Program Handler X
Interrupt
Handler Y
Disk
interrupt service routine
Greater capacity
Faster = smaller cost
access time per bit
= greater Greater
cost per bit capacity =
slower access
speed
The Memory Hierarchy
T2
Average access time
T1
0 1
Fraction of accesses involving only Level 1 (Hit ratio)
Also referred to
as auxiliary
memory
• external
• nonvolatile
• used to store
program and data
files
Cache Memory
• Invisible to the OS
• Interacts with other memory management hardware
• Processor must access memory at least once per
instruction cycle
• Processor execution is limited by memory cycle time
• Exploit the principle of locality with a small, fast memory
Block Transfer
Word Transfer
Fastest Fast
Less Slow
fast
C-1
Block Length
(K Words)
(a) Cache
Block M – 1
2n - 1
Word
Length
(b) Main memory
RA - read address
Receive address
RA from CPU
Load main
Deliver RA word
memory block
to CPU
into cache slot
DONE
Cache number of
cache block size
Design levels
Main
categorie
s are:
write mapping
policy function
replacemen
t algorithm
Cache and Block Size
Cache Block
Size Size
Processor
issues an I/O The processor
command to executes the
a module and data transfer
then goes on and then
to do some resumes its
other useful former
work processing
System Bus
Main I/O
Memory I/O Adapter
Subsystem
I/O
Adapter
I/O
Adapter
32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB
L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D
12 MB
L3 Cache