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Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal
Hardware behavior
Register transfer
Logic
Circuit
a=b=0→1 69 1.55
a = 1, b = 0 → 1 62 1.67
a = 0 → 1, b = 1 50 1.72
a=b=1→0 35 1.82
a = 1, b = 1 → 0 76 1.39
a = 1 → 0, b = 1 57 1.94
Copyright Agrawal, 2007 Lectures 5-8: Power Analysis 6
Spice Characterization (Cont.)
a=b=0 5.05
a = 0, b = 1 13.1
a = 1, b = 0 5.10
a=b=1 28.5
c (CMOS)
c (zero delay)
Logic simulation
c (unit delay)
X rise=5, fall=5
c (multiple delay)
Unknown (X)
c (minmax delay) min =2, max =5
0 5 Time units
Copyright Agrawal, 2007 Lectures 5-8: Power Analysis 9
Event-Driven Simulation Example
Scheduled Activity
events list
a =1 e =1 t=0 c=0 d, e
c =1→0 2 1
g =1 2 d = 1, e = 0 f, g
Time stack
2 3
2
d=0 4 g=0
5
4 f =0 6 f=1 g
b =1
7
8 g=1
g
0 4 8
Time, t
4
5
6
7
N
Delay at node k = 0.69 Σ Cj × Rjk
j=1
Example:
Pcap = Σ Ck V 2 f
all nodes k
Where:
Ck is the total node capacitance being switched, as
determined by the simulator.
V is the supply voltage.
f is the clock frequency, i.e., the number of vectors applied
per unit time
1/fck
N(t)
T = ───
t
N(t)
T = lim ───
t→∞ t
Transition probabilities:
T 01 = p 0 Prob{signal is 1 | signal was 0} = p 0 p1
T 10 = p 1 Prob{signal is 0 | signal was 1} = p 1 p 0
T = T 01 + T 10 = 2 p 0 p 1 = 2 p 1 (1 – p 1)
0.25
f = p1(1 – p1)
0.2
0.1
0.0
0 0.25 0.5 0.75 1.0
p1
1/fck
p1 = 0.5 T = 4/6
p1 = 0.5 T = 1/6
1/fck
p01 = p10 = 2/3
p00 = p11 = 1/3 p1 = 0.5
p 01 + p 00 = 1
p 11 + p 10 = 1
p0=1–p1
p 01
p 1 = ───────
p 10 + p 01
= 2 p 10 p 01 / (p 10 + p 01)
= 2 p 1 p 10 = 2 p 0 p 01
x1
x1 + x2 – x1x2
x2
x1 1 - x1
y = 1 - (1 - x1x2) x2
= 1 – x2 + x1x2x2
X1 X2 Y
= 1 – x2 + x1x2
0 0 1
= 0.75 (correct value)
0 1 0
1 0 1
1 1 1
y = (x1 + x2 – x1x2) x2
X1 X2 Y = x1x2 + x2x2 – x1x2x2
0 0 0 = x1x2 + x2 – x1x2
0 1 1 = x2
1 0 0 = 0.5 (correct value)
1 1 1
X2
X1 X2 Y
Shannon expansion about the
0 0 1
reconverging input, X2:
0 1 0
1 0 1
Y = X2 Y(X2 = 1) + X2’ Y(X2 = 0)
1 1 1
= X2 (X1) + X2’ (1)
X2
1
..
x1, T1
.. Boolean y, T(Y) = ?
. n
function
xn, Tn
n
T(y) = Σ T(Xi) Prob(Boolean diff(Y, Xi) = 1)
i=1
Transition density
Signal probability
A E A E
B F G
G B
C
D C
D F
Chain Tree
Signal
name Prob(sig.= 1) Prob(0→1) Prob(sig.=1) Prob(0→1)
A E A E
B F G
G B
C
D C
D F
A=11
B=10
E=10
C=11
F=10
D=01
G=00
Time units
0 1 2 3
A=11
B=10
Therefore, just counting the gate
E=10 transitions, we find that the chain
C=11
consumes 100(4 – 3)/3 = 33%
higher peak power than the tree.
D=10
F=10
G=10
Time units
0 1 2 3
Copyright Agrawal, 2007 Lectures 5-8: Power Analysis 56