Mission

Research
Corporation

Nonvolatile, High Density, High

Performance Phase Change Memory
Guy Wicker1, Scott Tyson2, Tyler Lowrey1, Stephen Hudgens1, Robert Pugh3, Ken Hunt3

1
Ovonyx, Inc., 1675 W. Maple Rd, Troy, MI 48084
2
Mission Research Corp., 5001 Indian School Rd NE, Albuquerque, NM 87110
3
Air Force Research Laboratory, 3550 Aberdeen SE, Kirtland AFB, NM 87117

ABSTRACT
ABSTRACT
A resistor-based approach has been developed as a basis for a new nonvolatile
memory that is potentially denser, faster, and easier to make than Dynamic RAM.
It relies on phase transitions induced by nanosecond-scale heating and cooling of
small volumes of chalcogenide films within the memory cell. Initial target markets
include FLASH memory, embedded memory, and DRAM.
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BACKGROUND
BACKGROUND
Mission
Research
Corporation

As early as the 1950s, the semiconducting properties of a range of crystalline and amorphous
chalcogenide alloys were investigated. In the early 1960s, new reversible phase change materials
and electrically and optically programmable devices were reported, and these devices were proposed
for use in digital computers as non-volatile memory. 650 MByte PD and CD-RW disks and 5.2
GByte DVD-RAM optical memory disks using a laser-induced structural phase change in a
chalcogenide alloy are now in production. A number of recent developments have made it possible
to use phase-change semiconductor memory devices as practical high-performance memory
elements.
• Alloys developed for use in optical disk applications have been shown to be well suited for use
in semiconductor memory applications
• A more detailed understanding of the device behavior has developed that permits the
engineering of practical memory devices
• Lithographic scaling and processing improvements have reduced the programming requirements
of new cell designs, which can now be driven by minimum geometry MOS transistors
It is now believed that chalcogenide technology can provide a lower cost and higher performance
memory than EEPROM and DRAM. Furthermore, embedded memory applications can readily be
achieved due to the simple, planar structure of the storage element.

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 THEORY
THEORY OF
OF OPERATION
OPERATION
Mission
Research
Corporation

The phase conversion is accomplished by heating and cooling the material. When melted it
loses all crystalline structure, and rapid cooling below glass transition temperature causes the
material to be locked into its amorphous phase. This phase is very stable near room
temperature, but the rate of nucleation and growth of crystallites increases exponentially as the
melting temperature is approached. To switch the memory element back to its conductive
state, the material is heated to a temperature between the glass transition temperature and the
melting temperature, causing nucleation and crystal growth to rapidly occur over a period of
several nanoseconds.
The crystal nucleation and growth rate depends on the chalcogenide alloy composition and can
vary by more than 20 orders of magnitude among various materials. Changes in the electrical
properties of these alloys are far more dramatic, with variations in the electrical conductivity
by up to 6 orders of magnitude between phases.

Conductivity (ohm-cm)-1

Activation Energy (eV)

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THEORY
THEORY OF
OF OPERATION
OPERATION (Cont)
(Cont)
Mission
Research
Corporation

To create an electronic memory from these VA VA

materials, an array of access transistors must each R R
C D e v ic e C D e v ic e
be capable of providing sufficient power to a
memory element to melt a portion of the C n
chalcogenide alloy. Thermal isolation of the VA VA
memory element itself from the heat-sinking R C R C
D e v ic e D e v ic e
substrate and metallization is a crucial aspect of
the memory element design. C n+ 1

R ow n R ow n+1
Three modes of operation –
• Read - the electric field is limited by applying a low voltage. A small current will
pass if the material is in the amorphous state; in the crystalline phase, the applied
voltage and the resistance of the contact will limit the current through the device.
• Set - the voltage must be high enough to ensure that the alloy will switch into a low
impedance state. An intermediate current level will heat the material but not melt it.
• Reset - the voltage must be high enough to ensure that the alloy will switch into a low
impedance state with sufficient current to heat a portion of the material above its
melting temperature. When the current is removed, the small volume of material that
has melted will rapidly quench into the amorphous state.
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DEVICE
DEVICE PERFORMANCE
PERFORMANCE AND
AND SCALING
SCALING
Mission
Research
Corporation

The scaling limitation of a memory device based on a phase change alloy is the minimum
amount of material that can reliably undergo a phase transition. The results of finite
element simulation show that the power needed to operate the memory goes down
dramatically as the device size is decreased. The quenching time is roughly proportional
to the device size as well. Memory elements exhibit a dramatic reduction in reset power as
size is reduced as well.It seems that for the near future, the scaling limits of the addressing
circuitry and the lateral isolation of the individual elements of the memory array will be
the dominant concern.
1 .1E E- 0 - 77
S u rro u n d in g H e a te d R e g io n

1900
T h e rm al D ia m e te r

1500
(a n g stro m s)

120
In s u la tio n

100
1 .1E E- 0 - 88

0
Q u e n c h tim e ( s )

800

0
60

40
er 0
0

m
P o ly
1 .1E E- 0 - 99 200 G
BPS
100 S iO
S iN
11 .EE -- 11 00

11. EE - -1 11 1
1 . E1 - E0 6- 6 1 1. EE - -0 55 1 1. EE - 0- 44 1 1. E E- 0- 33
P o w e r to re s e t in 5 n s (W )
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DEVICE
DEVICE CONFIGURATION
CONFIGURATION
Mission
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Corporation

S iO 2

C h a lc o g e n id e
S iO 2 v ia
T h in
C o n ta c t
S iO 2

Si

One structure currently being investigated is shown above. The bottom electrode contacts
the chalcogenide alloy material, forming a ring-shaped contact area. The chalcogenide
alloy is deposited in the highly conductive crystalline phase. The region where phase
transition occurs is limited to the chalcogenide material immediately adjacent to the lower
electrode. This reduction in the volume of material being melted reduces the power
requirement sufficiently to allow a minimum-feature-size MOS transistor to easily control
the device.

Detailed modeling of the electrical, thermal, and phase-transition behavior of these device
structures has suggested numerous alternative structures that will have improved reliability
and that will integrate well into a standard CMOS logic or memory process.
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NEAR
NEAR TERM
TERM DEVELOPMENT
DEVELOPMENT FOR
FOR SPACE
SPACE
Mission
Research
Corporation

Although many memory technologies (i.e., SRAM, DRAM, FeRAM, EEPROM, Flash,
ROM, HDD, and MRAM) are capable of supporting a variety of terrestrial applications
due to the ready availability of power grid and the easy replacement of worn-out or failed
components, each of these technologies possesses serious inadequacies for implementation
in space-based or missile systems. Reasons include susceptibility to extreme shock,
radiation, or thermal environments; high levels of power consumption; high cost; low
integration levels; and low cycling limitations. In contrast, the technology described here
offers an approach that potentially overcomes each of the limitations of these other
technologies.
As a result, the Air Force Research Laboratory has initiated a development effort to
demonstrate the feasibility of the technology. The chalcogenide memory element will be
integrated into the process flow of a space-hardened, submicron fabrication technology
capable of supporting an initial circuit integration level of 16Mb. Test structures will be
fabricated and characterized, and the thermal models will be further refined. The effort is
scheduled to begin during last quarter of 1999.

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Summary
Summary
Mission
Research
Corporation

Chalcogenide-alloy, phase-change memories can provide competitive alternatives to

established semiconductor memory products. Additionally, chalcogenide-based memories
offer nonvolatile operation, DRAM speeds, no practical cycling limitations, higher
integration density, and lower manufacturing cost than any established technology.
Inherent radiation hardness of the basic material makes this technology an ideal candidate
for space electronics applications.

These memory elements are fundamentally different from other semiconductor memories;
information storage is achieved through changes in electrical resistivity rather than
through manipulation of exceedingly small amounts of charge.

Efforts to date have focused on reducing the power needed to switch the memory element
to allow operation by a single, minimum-feature-size MOS transistor, thereby allowing
maximum memory density integration. Extensive modeling supports the achievement of
this goal. New devices are currently being fabricated to demonstrate the feasibility of
integrating planar resistive elements with MOS transistors. Device modeling suggests that
these devices will meet the goal of low power switching and simple lithographic-
dependent scalability.
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