+

Chapter 5
Internal Memory
+
Memory Cell Operation
Semiconductor Memory Types

Table 5.1 Semiconductor Memory Types

+
Dynamic RAM (DRAM)

 RAM technology is divided into two technologies:

 Dynamic RAM (DRAM)
 Static RAM (SRAM)

 DRAM

 Made with cells that store data as charge on capacitors

 Presence or absence of charge in a capacitor is interpreted as a binary 1 or

0

 Requires periodic charge refreshing to maintain data storage

 The term dynamic refers totendency of the stored charge to leak away,
even with power continuously applied
+
Dynamic
RAM
Structure

Figure 5.2a
Typical Memory Cell Structures
+
Static RAM
(SRAM)
 Digital device that uses the same logic
elements used in the processor

 Binary values are stored using

traditional flip-flop logic gate
configurations

 Will hold its data as long as power is

supplied to it
+
Static
RAM
Structure

Figure 5.2b
Typical Memory Cell Structures
 SRAM versusDRAM
SRAM
 Both volatile
 Power must be continuously supplied to the memory to
preserve the bit values

 Dynamic cell
Simpler to build, smaller
DRAM


 More dense (smaller cells = more cells per unit area)

 Less expensive
 Requires the supporting refresh circuitry
 Tend to be favored for large memory requirements
+  Used for main memory

 Static
 Faster
 Used for cache memory (both on and off chip)
+
Read Only Memory (ROM)
 Contains a permanent pattern of data that cannot be changed or
added to

 No power source is required to maintain the bit values in memory

 Data or program is permanently in main memory and never needs to

be loaded from a secondary storage device

 Data is actually wired into the chip as part of the fabrication process
 Disadvantages of this:
 No room for error, if one bit is wrong the whole batch of ROMs must be
thrown out
 Data insertion step includes a relatively large fixed cost
+
Programmable ROM (PROM)

 Less expensive alternative

 Nonvolatile and may be written into only once

 Writing process is performed electrically and may be performed by

supplier or customer at a time later than the original chip fabrication

 Special equipment is required for the writing process

 Provides flexibility and convenience

 Attractive for high volume production runs

 Read-Mostly Memory

EEPRO Flash
EPROM
M Memory
Electrically erasable
programmable read-only Intermediate between
Erasable programmable read-
memory EPROM and EEPROM in
only memory
both cost and functionality

Can be written into at any time

without erasing prior contents
Uses an electrical erasing
Erasure process can be
technology, does not provide
performed repeatedly
Combines the advantage of byte-level erasure
non-volatility with the
flexibility of being updatable in
place
Microchip is organized so that
More expensive than PROM
a section of memory cells are
but it has the advantage of the
More expensive than EPROM erased in a single action or
multiple update capability
“flash”
Typical 16 Mb DRAM (4M x 4)
Chip Packaging
 Figure 5.5

256-KByte
Memory
Organization

+
1MByte Module Organization
Interleaved Memory Composed of a collection of
DRAM chips

Grouped together to form a memory

bank

Each bank is independently able to

service a memory read or write
request

K banks can service K requests

simultaneously, increasing memory
read or write rates by a factor of K

If consecutive words of memory

are stored in different banks, the
transfer of a block of memory is
speeded up
+
Error Correction
 Hard Failure
 Permanent physical defect
 Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1
or switch erratically between 0 and 1
 Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
 Wear

 Soft Error
 Random, non-destructive event that alters the contents of one or more memory cells
 No permanent damage to memory
 Can be caused by:
 Power supply problems
 Alpha particles
Error Correcting Code Function
+
BATAS KELOMPOK
+
Hamming
Error
Correcting
Code
Sistem yang dikembangkan
dari error detection code
dengan menggunakan parity
bit

Diperkenalkan oleh Richard Diagram venn Hamming code

Hamming ((BELL LAB) dalam 4 bit WORDS
 Posisi
(decimal)
7 6 5 4 3 2 1

Posisi (bit) 0111 0110 0101 0100 0011 0010 0001

Data bit D4 D3 D2 D1
Check Bit C3 C2 C1

Banyak check bit (K) yang diperlukan :

2k – 1 >= M (banyak bit data) + K

Jika K = 3 Jika K = 2
2 3– 1 > 4 + 2 22 – 1 < 4 + 2
 Banyak check bit (K) yang diperlukan :
C1 = D1 XOR D2 XOR D4 (POSISI 3, 5, 7)
C2 = D1 XOR D3 XOR D4 (POSISI 3, 6, 7)
C3 = D2 XOR D3 XOR D4 (POSISI 5, 6, 7)

Posisi7 :
CONTOH
(decimal)
6 5 4 3 2 1

Posisi (bit) 0111 0110 0101 0100 0011 0010 0001

Diambil Data 4 BIT
1011
Data bit 1 0 1 1
Check Bit 0 0 1
 C1 = D1 XOR D2 XOR D4 (POSISI 3, 5, 7)
C2 = D1 XOR D3 XOR D4 (POSISI 3, 6, 7)
C3 = D2 XOR D3 XOR D4 (POSISI 5, 6, 7)

Posisi
(decimal)
7 6 5 4 3 2 1

Posisi (bit) 0111 0110 0101 0100 0011 0010 0001

Data bit 1 0 1 0
Check Bit 0 1 0
+
Layout of Data Bits and Check Bits
Check Bit Calculation
+
Hamming SEC-DED Code
 Organisasi DRAM SDRAM

 Salah satu masalah bottleneck (perbedaan kecepatan transfer

rate ) yang paling besar yaitu antara processor- internal memory
DDR-DRAM
 Pada DRAM lama, chip is constrained both by its internal
architecture and by its interface to the processor’s memory bus

 Telah banyak peningkatan dan pengembangan pada arsutektur

DRAM dan telah banyak alternatifnya yang dikembangkan.
RDRAM

Table 5.3 Performance Comparison of Some DRAM Alternatives

Synchronous DRAM (SDRAM)

Merupakan memori Dynamic RAM yang banyak digunakan

Transfer data dengan processor terjadi secara synchronous terhadap sinyal

clock sehingga memungkinkan kecepatan transfer tinggi dengan processor
dan system bus sehingga mengurangi bottleneck dan mempercepat kerja
processor tanpa adanya penundaan (wait state).

Pada synchrous akses, transfer data SDRAM terjadi dengan control dari
sistem clock.
• Processor akan memberikan perintah
• DRAM akan merespon setelah beberapa set clock system tertentu
• Sementara itu, processor dapat menjalankan tugas dan instruksi lainnya selama
terjadi pemprosesan pada SDRAM
 Table 5.3
Perbandingan DRAM
dengan Alternatifnya

Table 5.3 Performance Comparison of Some DRAM Alternatives

SD
RA
M
+
SDRAM Pin Assignments

Table 5.4 SDRAM Pin Assignments

+
SDRAM Read Timing
 RDRAM Developed by Rambus

Bus memberikan informasi

kontrol alamat menggunakkan
protokol berorientasi blok
asynchronous Adopted by Intel for its Pentium
• Mendapat permintaan memori melalui bus and Itanium processors
kecepatan tinggi
• Permintaan berisi alamat yang diinginkan,
jenis operasi, dan jumlah byte dalam
operasi

Bus dapat menangani hingga 320

RDRAM merupakan pesaing
chip RDRAM dan diberi nilai 1,6
utama SDRAM
GBps

Chip adalah paket vertikal dengan

semua pin di satu sisi
Pertukaran data dengan processor
lebih dari 28 kabel yang panjangnya
tidak lebih dari 12cm
+
RDRAM Structure
+
Double Data Rate SDRAM
(DDR SDRAM)
 SDRAM hanya bisa mengirim data sekali per siklus bus clock

 Double-data-rate SDRAM dapat mengirim data dua kali per siklus

clock, sekali pada rising edge clock pulse dan sekali pada falling edge

 Dikembangkan oleh JEDEC Solid State Technology Association

(Electronic Industries Alliance’s semiconductor-engineering-
standardization body)
+
DDR SDRAM
Read
Timing
+
Cache DRAM (CDRAM)

 Dikembangkan oleh Mitsubishi

 Mengintegrasikan cache SRAM kecil ke generic DRAM chip

 SRAM pada CDRAM dapat digunakkan dalam dua cara :

 Ini bisa digunakkan sebagai cache yang terdiri dari sejumlah baris 64-
bit

 Mode cache dari CDRAM efektif untuk akses acak ke memori

 Bisa juga digunakkan sebagai penyangga untuk mendukung akses

serial blok data
+ Summary Internal
Memory

 Semiconductor main memory

 Hamming code
 Organization
 DRAM and SRAM  Advanced DRAM organization
 Types of ROM  Synchronous DRAM
 Chip logic  Rambus DRAM
 Chip packaging  DDR SDRAM
 Module organization  Cache DRAM
 Interleaved memory
 Error correction
 Hard failure
 Soft error