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MICROPROCESSORS
&
MICROCONTROLLER

EC-602
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LESSON PLAN
Module-2
8051 architecture:
8051 micro controller hardware, input/output pins, ports, external
memory, counters and timers, instruction set, addressing modes,
serial data i/o, interrupts.

Assembly language Programming:

Moving data:
External data moves, code memory read only data moves, PUSH
and POP opcodes, data exchanges.
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LESSON PLAN
Module-2
Assembly language Programming:
Logical operations:
Byte-level, bit-level, rotate and swap operations.
Arithmetic operations:
Flags, incrementing and decrementing, addition, subtraction,
multiplication and division, decimal
arithmetic.
Jump and call instructions:
Jump and call program range, jumps, calls and subroutines, interrupts
and returns.
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THE 8051
MICROCONTROLLER
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 What is a microcontroller ?
Basically a device which integrates a number of components of a
microprocessor system on to a single chip, only need to supplied
power and clocking.

 Microcontroller combines on the same chip

1) The CPU core
2) I/O Ports
3) Memory
4) Timer
DIFFERENCE BETWEEN MP & MC

6
7
 BLOCK DIAGRAM
External Interrupts

Interrupt 4k 128 bytes Timer 1

Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

P0 P2 P1 P3 TXD RXD
Addr/Data
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8051 BASIC COMPONENT

4K bytes internal ROM
128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface

CPU RAM ROM

A single chip
I/O Serial Microcontroller
Timer COM
Port Port
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8051 FEATURS
Only 1 On chip oscillator (external crystal)
6 interrupt sources (2 external , 3 internal, Reset)
64K external code (program) memory(only read) PSEN
64K external data memory(can be read and write) by RD,WR
Code memory is selectable by EA (internal or external)
We may have External memory as data and code
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ARCHITECTURE
OF
8051

PIN DIAGRAM
 P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 )P0.1(AD1)
P1.3 4 37 P0.2(AD2
P1.4 5 36 )P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 8051 31 EA
(TXD)P3.1 11 30 ALE
(INT0)P3.2 12 MC 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 )P2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 )P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

13
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PIN DISCRIPTION
One of the most useful features of the 8051 is that it contains four I/O ports
(P0 - P3)

 Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）

 8-bit R/W - General Purpose I/O
 Or acts as a multiplexed low byte address and data bus for external memory design

 Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）

 Only 8-bit R/W - General Purpose I/O

 Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）

 8-bit R/W - General Purpose I/O
 Or high byte of the address bus for external memory design

 Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）

 General Purpose I/O
 if not using any of the internal peripherals (timers) or external interrupts.

Each port can be used as input or output (bi-direction)

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PORT 3 ALTERNATE FUNCTIONS

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PIN DISCRIPTION
Vcc （ pin 40 ）： Vcc provides supply voltage to the chip. The
voltage source is +5V.
GND （ pin 20 ）： Ground.
XTAL1 and XTAL2 （ pins 19,18 ）： These 2 pins provide
external
clock by using a quartz crystal oscillator.
C2
XTAL2
30pF Using a quartz crystal oscillator
C1 We can observe the frequency
XTAL1 on the XTAL2 pin.
30pF

GND
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PIN DISCRIPTION
Vcc （ pin 40 ）： Vcc provides supply voltage to the chip. The
voltage source is +5V.
GND （ pin 20 ）： Ground.
XTAL1 and XTAL2 （ pins 19,18 ）： These 2 pins provide
external
clock by using a quartz crystal oscillator.
C2
XTAL2
30pF Using a quartz crystal oscillator
C1 We can observe the frequency
XTAL1 on the XTAL2 pin.
30pF

GND
 PIN DISCRIPTION
RST （ pin 9 ）： Reset
 input pin and active high （ normally low ） .
The high pulse must be high at least 2 machine cycles.
 power-on reset.
Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.
Reset values of some 8051 registers power-on reset circuit
Register Reset Value
PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero
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EA （ pin 31 ）： Enable external access

 The EA pin is connected to GND to indicate the code is stored
externally.
 PSEN ＆ ALE are used for external ROM.

If EA is low, then the program memory is external.

If EA is high, then addresses from 0000 to 0FFF will refer to

on-chip memory and addresses 1000 up to FFFF refer to
external memory.
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PSEN （ pin 29 ）： Program store enable

 This is an output pin and is connected to the OE pin of the
ROM.

ALE （ pin 30 ）： Address latch enable

 It is an output pin and is active high.
 8051 port 0 provides both address and data.
 The ALE pin is used for de-multiplexing the address and data
by connecting to the G pin of the 74LS373 latch.
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8051 MEMORY
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ACCESS TO EXTERNAL MEMORY

PORT 0 acts as a multiplexed address/data bus. Sending the low
byte of the program counter (PCL) as an address.

PORT 2 sends the program counter high byte (PCH) directly to

the external memory.

The signal ALE operates as in the 8051 to allow an external latch

to store the PCL byte while the multiplexed bus is made ready to
receive the code byte from the external memory.

PORT 0 then switches function and becomes the data bus

receiving the byte from memory.
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ADDRESS MULTIPLEXING FOR EXTERNAL MEMORY

Figure: Accessing external code memory

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ADDRESS MULTIPLEXING FOR EXTERNAL CODE MEMORY

WR
RD
PSEN OE
ALE 74LS373 CS
G
P0.0 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 ROM
TIMMING DIAGRAM
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ACCESSING EXTERNAL DATA MEMORY

Interface to 1K RAM
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ACCESSING EXTERNAL DATA MEMORY

WR WR
RD RD
PSEN
ALE G 74LS373 CS
P0.0 D
A0
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15
RAM

Interfaceing to RAM
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TIMING FOR MOVX INSTRUCTION

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ARCHITECTURE
OF
8051
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ARCHITECTURE OF 8051
 Accumulator : It is an 8 – bit register used for
arithmetic and logical operation to
accumulate the result.
Several function like rotate, swap etc
apply on the accumulator

 B register: It is use with A register for multiplication and

division for other instruction it is treated a
scratch pad register.
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ARCHITECTURE OF 8051
 ALU : The ALU can perform arithmetic and logical
operation on 8-bit data. Like add, sub, mul, div
or AND or OR ,compliment, etc.

 Program counter (PC) : It is a 16 –bit register. It is

used to hold the address of an instruction
(program) stored in the memory.

 Program status word ( PSW ): Many instruction affect

the status flags in order to address these flags
conveniently they can be grouped to from PSW
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ARCHITECTURE OF 8051
 DPTR: DATA POINTER
 The data pointer is 16 bit register
 It is used to hold the address of data in the memory.
 It can be accessed separately as lower 8 bit (DPL) and
higher 8 bit (DPH)
 The DPTR does not have a single internal address
instead DPH and DPL are each assigned a separate
address.
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ARCHITECTURE OF 8051
 STACK AND STACK POINTER
 The stack is the reserved area of the memory in the
RAM where temporary information may be stored.
 An 8 – bit stack pointer is used to hold the address of
most recent stack entry. Generally it is called top of the
stack.
 It work on LIFO or FILO principle.
 By default location of stack pointer is 07h
we can change the default location by MOV SP,# XX h
( RAM location 30h – 7Fh)
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ARCHITECTURE OF 8051
STACK IN THE 8051

7FH
 The register used to access the
Scratch pad RAM
stack is called SP (stack pointer)
register. 30H

2FH
Bit-Addressable RAM
 The stack pointer in the 8051 is
20H
only 8 bits wide, which means that 1FH Register Bank 3
it can take value 00 to FFH. 18H
17H
Register Bank 2
10H
 When 8051 powered up, the SP 0FH (Stack) Register Bank 1
register contains value 07. 08H
07H
Register Bank 0
00H
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PROGRAM STATUS WORD (PSW)

Register set select Status bits
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PROGRAM STATUS WORD (PSW)

8051 FLAG BITS
 PSW (Program status word) register
 It is an 8-bit register
 It is a bit addressable register
CY AC FO RS1 RS0 OV - P

CY- Carry flag PSW.7

AC- Auxiliary carry PSW.6
FO – Available to the user for general purpose
RS0-RS1- Register Bank selector (PSW.3, PSW.4)
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PROGRAM STATUS WORD (PSW)

8051 FLAG BITS
OV- overflow Flag PSW.2
P- Parity Flag PSW.0

RS1 RS0 Register Bank Address

0 0 Bank 0 00h-07h
0 1 Bank 1 08h- 0fh
1 0 Bank2 10h-17h
1 1 Bank3 18h-1Fh
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PROGRAM STATUS WORD (PSW)

8051 FLAG BITS
 CY This flag is set whenever there is carry from D7 bit.
This flag bit is affected after addition or subtraction. It
can also set 1 or 0 directly by instruction such as
“SETB C” and “ CLR C”
 AC If there is carry from D3 to D4 during an ADD or
SUB operation, this bit is set; otherwise it is cleared
( used in BCD arithmetic)
• P The Parity Flag reflects the number of 1s in the A
( accumulator) . If A contains odd number of 1s, then
P=1 and A contains even number of 1s, then P=0
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PROGRAM STATUS WORD (PSW)

8051 FLAG BITS

OV this flag is set whenever the result of singed

number operation is too large, causing the high-order
bit to overflow into the sign bit
( It is used only in signed operation)
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ARCHITECTURE
OF
8051

MEMORY ORGANIZATION
 8051 MEMORY
FFFF FFFF FFFF

up to 60 KB SF = Special Function
of external
ROM/
EPROM
up to 64
KB of 00F8 up to 64 KB
external 1000 of external
EPROM/ 21 SF registers RAM
ROM or and 0080
0FFF 007F
128 KB internal
4 KB of RAM
internal
ROM/
EPROM
0000 0000 0000
0000

PROGRAM OR CODE MEMORY (ROM) DATA MEMORY (RAM)

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ON-CHIP MEMORY INTERNAL RAM

 The 8051 has 256 bytes of RAM on-chip.
 The lower 128 bytes are intended for internal data
storage.
 The upper 128 bytes are the Special Function
Registers (SFR).

 The lowest 32 bytes of the on-chip RAM form 4 banks

of 8 registers each.

 Only one of these banks can be active at any time.

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ON-CHIP MEMORY INTERNAL RAM

 Bank is chosen by setting 2 bits in PSW

 Default bank (at power up) is bank 0 (locations 00–07).

 The 8 registers in any active bank are referred to as R0

through R7

Given that each register has a specific address, it can be

accessed directly using that address even if its bank is not
the active one.
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ON-CHIP MEMORY INTERNAL RAM

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ON-CHIP MEMORY INTERNAL RAM

7F
General purpose RAM
80 bytes
30
2F 7F 7E 7D 7C 7B 7A 79
78

Bit addressable
RAM 16 bytes ( 80
0F 0E 0D 0C 0B 0A 09 08 bits)

2 07 06 05 04 02 00
0 03 01
1F Bank 4 Reg. BANK
3 8 bytes each
Bank Total 32 bytes
0 2
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ON-CHIP MEMORY INTERNAL RAM

7FH

Scratch pad RAM

30H

2FH

Bit-Addressable RAM
20H
1FH
18H Register Bank 3
17H
10H Register Bank 2
0FH
08H Register Bank 1
07H
00H Register Bank 0
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ON-CHIP MEMORY INTERNAL RAM

 The next 16 bytes – locations 20H to 2FH – form a
block that can be addressed as either bytes or
individual bits.
 The bytes have addresses 20H to 2FH.
 The bits have addresses 00H to 7FH.
 Specific instructions are used for accessing
the bits.

 Locations 30H to 7FH are general purpose RAM.

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REGISTERS (PART OF RAM)

1F

Bank 3
Four Register Banks
Each bank has R0-R7
18 Selectable by psw.2,3
17

Bank 2

10
0F

Bank 1

08
07 R7
06 R6
05 R5
04 R4 Bank 0
03 R3
02 R2
01 R1
00 R0
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BIT ADDRESSABLE MEMORY (PART OF RAM)

2F 7F 78
2E
20h – 2Fh (16 locations X 8-bits = 128 bits)
2D
Bit addressing:
2C MOV C, 1Ah
2B
2A
29
28
27
26
25
24
23
22
21
20
1A
DATA MEMORY (RAM)
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SPECIAL FUNCTION REGISTERS

DATA registers

CONTROL registers
Timers
Serial ports
Interrupt system Addresses 80h – FFh
Analog to Digital converter
Digital to Analog converter Direct Addressing used to
access SPRs
Etc.
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THE SFR (SPECIAL FUNCTION REGISTER)

 The upper 128 bytes of the on-chip RAM are used to

house special function registers.
 In reality, only about 25 of these bytes are actually
used. The others are reserved for future versions of
the 8051.
 Some of these registers are bit-addressable as well as
byte-addressable. The address of bit 0 of the register
will be the same as the address of the register.
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THE SFR (SPECIAL FUNCTION REGISTER)

ACC and B registers – 8 bit each
DPTR : [DPH:DPL] – 16 bit combined
PC (Program Counter) – 16 bits
SP (Stack Pointer) – 8 bit
PSW (Program Status Word)
Port Latches
Serial Data Buffer
Timer Registers
Control Registers
THE SFR (SPECIAL FUNCTION REGISTER)
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ARCHITECTURE
OF
8051

ADDRESSING MODES
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ADDRESSING MODES

The way in which the instruction is specified.

• Immediate
• Register
• Direct
• Register Indirect
• Indexed
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IMMEDIATE ADDRESSING MODE

Immediate Data is specified in the instruction itself
Eg:
MOV A, #30
MOV R6, #65H
MOV DPTR, #2343H
MOV P1, #65H
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REGISTER ADDRESSING MODE

Either source or destination is one of CPU register
MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV R5,DPL
MOV R,DPH

Note that MOV R4,R7 is incorrect

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DIRECT ADDRESSING MODE

Specify data by its 8-bit address
Usually for 30h-7Fh of RAM
MOV A, 70H ; copy contents of RAM at 70H to A

MOV R0, 40H ; copy contents of [40H] to R0

MOV 56H, A ; put contents of A at 56H
MOV 20H, 30H ; [20H] [30H]
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REGISTER INDIRECT ADDRESSING MODE

INTERNAL RAM
In this mode, register is used as a pointer to the data.

MOV A, @Ri ; move content of RAM loc.

Where address is held by Ri into A ( i=0 or 1 )

MOV @R1, B ; [R1] B

In other word, the content of register R0 or R1 is sources or target in

MOV, ADD and SUBB instructions.
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REGISTER INDIRECT ADDRESSING MODE

EXTERNAL RAM (16-BIT ADDRESS)
For External RAM, address is given by R1, R0 & DPTR.
“X” is present in the instruction to indicate External RAM

MOVX A, @ DPTR ; A gets the content of External RAM whose

address is given by DPTR.

MOVX @DPTR, A ; The value of A goes to the External RAM

whose address is given by DPTR.
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REGISTER INDIRECT ADDRESSING
MODE
EXTERNAL RAM(8-BIT ADDRESS)
For External RAM, address is given by R1, R0 & DPTR.

“X” is present in the instruction to indicate External RAM

If R0 & R1 is used to give an address, then only the first 256

locations of External RAM is available from 0000H – 00FFH

MOVX A, @ R0 ; A gets the content of External RAM whose

address is given by R0.

MOVX @R1, A ; The value of A goes to the External RAM

whose address is given by R1.
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INDEXED ADDRESSING MODE AND ON-CHIP

ROM ACCESS
This mode is widely used in accessing data elements of
look-up table entries located in the program (code) space
ROM at the 8051

MOVC A, @A+DPTR; A= content of address A +DPTR from ROM

MOVC A, @A+PC; A= content of address A +PC from ROM

Note:
Because the STATIC data elements are stored in the program (code )
space ROM of the 8051, it uses the instruction MOVC instead of MOV. The
“C” means code.
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ARCHITECTURE
OF
8051

INSTRUCTION SETS
 ARITHMETIC
INSTRUCTION
OF
8051
 SUBTRACT
SUBB A, byte subtract with borrow

Example:

SUBB A, #0x4F ;A  A – 4F – C

Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.

Example:

Clr c
SUBB A, #4F ;A  A – 4F
 MULTIPLY
When multiplying two 8-bit numbers, the size of the maximum
product is 16-bits

FF x FF = FE01
(255 x 255 = 65025)

MUL AB ; BA  A * B

Note : B gets the High byte

A gets the Low byte

69
 DIVISION

• Integer Division

DIV AB ; divide A by B

A  Quotient(A/B)
B  Remainder(A/B)

OV - used to indicate a divide by zero condition.

C – set to zero
 INCREMENT AND DECREMENT
INC A increment A
INC byte increment byte in memory

INC DPTR increment data pointer

DEC A decrement accumulator

DEC byte decrement byte

• The increment and decrement instructions do NOT affect the C

flag.
• Notice we can only INCREMENT the data pointer, not decrement.
 Mnemonic Description
DATA MOV @Ri, direct [@Ri] = [direct]

TRANSFER MOV @Ri, #data [@Ri] = immediate data

MOV DPTR, #data 16 [DPTR] = immediate data

INSTRUCTION MOVC A,@A+DPTR A = Code byte from [@A+DPTR]

OF MOVC A,@A+PC A = Code byte from [@A+PC]

8051 MOVX A,@Ri A = Data byte from external ram [@Ri]

MOVX A,@DPTR A = Data byte from external ram [@DPTR]

MOVX @Ri, A External[@Ri] = A

MOVX @DPTR,A External[@DPTR] = A

PUSH direct Push into stack

POP direct Pop from stack

XCH A,Rn A = [Rn], [Rn] = A

XCH A, direct A = [direct], [direct] = A

XCH A, @Ri A = [@Rn], [@Rn] = A

XCHD A,@Ri Exchange low order digits

 LOGICAL
INSTRUCTION
OF
8051
 ROTATE
• Rotate instructions operate only on a

RL a
Mov a,#0xF0 ; a 11110000
RR a ; a 11100001

RR a
Mov a,#0xF0 ; a 11110000
RR a ; a 01111000
74
 ROTATE THROUGH CARRY
C
RRC a

mov a, #0A9h ; a  A9
add a, #14h ; a  BD (10111101), C0
rrc a ; a  01011110, C1

C
RLC a

mov a, #3ch ; a  3ch(00111100)

setb c ; c  1
rlc a ; a  01111001, C1
75
 SWAP

SWAP a

mov a, #72h ; a  72h

swap a ; a  27h

76
 BIT CLR
Mnemonic

C Clear C
Description

INSTRUCTION CLR

SETB C
bit Clear direct bit

Set C

OF SETB bit Set direct bit

CPL C Complement c
8051 CPL bit Complement direct bit

ANL C,bit AND bit with C

ANL C,/bit AND NOT bit with C

ORL C,bit OR bit with C

ORL C,/bit OR NOT bit with C

MOV C,bit MOV bit to C

MOV bit,C MOV C to bit

JC rel Jump if C set

JNC rel Jump if C not set

JB bit,rel Jump if specified bit set

JNB bit,rel Jump if specified bit not set

if specified bit set then clear it and

JBC bit,rel
jump
 JUMP ACALL addr11
Mnemonic Description

Absolute subroutine call

INSTRUCTION LCALL addr16 Long subroutine call

RET Return from subroutine

OF RETI Return from interrupt

8051 AJMP addr11

LJMP addr16
Absolute jump

Long jump

SJMP rel Short jump

JMP @A+DPTR Jump indirect

JZ rel Jump if A=0

JNZ rel Jump if A NOT=0

CJNE A,direct,rel

CJNE A,#data,rel
Compare and Jump if Not Equal
CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ Rn,rel
Decrement and Jump if Not
Zero
DJNZ direct,rel

NOP No Operation
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