DSP C5000

Chapter 3
Addressing Modes

Copyright © 2003 Texas Instruments. All rights reserved.

 Objectives
 Present the main addressing modes and
allocation of sections
 Present the main addressing modes of
the C54 family
 Present the main addressing modes of
the C55 family
 Explain how to use these addressing
modes
 Do exercises to practice using the
different addressing modes

SIEE, Slide 2 Copyrig

 Outline

Generalities on addressing modes

C54x

C55x

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 Addressing Modes: What are the Problems?
 Specify operands per instruction:
 A single instruction can access several
operands at a time thanks to the many
internal data busses,
 But how do we specify many addresses using
a small number of bits?
 Repeated processing on an array of data:
 Many DSP operations are repeated on an
array of data stored at contiguous addresses
in data memory.
 There are cases where it is useful to be able
to modify the addresses as part of the
instruction (increment or decrement).
SIEE, Slide 4 Copyrig
 Main Addressing Modes of C5000 Family
 Immediate addressing
 Absolute addressing
 Direct addressing
 Indirect addressing by register
 Support for circular indirect addressing
 Definition
 Access to Memory Mapped Registers
MMRs

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 Allocating Sections

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 Example
System Diagram
Algorithm DROM RAM

y = x1 + x0 + x2 init[3] x[3]

EPROM C5000 RAM

(code) CPU y

Procedure
 Allocate sections (code, constants, vars)
 Setup addressing modes
 Add the values (x1 + x0 + x2)
 Store the result (y)

How do we allocate the proper sections?

SIEE, Slide 7 Copyrig
 Writing relocatable code
 The programmer should not have to give the
exact addresses:
 where to read the code in program memory,
 where to read the data in data memory.
 The assembler allows to use symbolic addresses.
 The assembler and the linker work with COFF
files:
 COFF = Common Object File Format.
 In COFF files, specialized sections are used for code,
variables or constants.
 The programmer specifies in a command file for the
linker where the different sections should be
allocated in the memory of the system.

SIEE, Slide 8 Copyrig

 Definition of Sections
 Different sections for code, vars, constants.
 The sections can be initialized or not.
 An initialized section is filled with code or
constant values.
 An uninitialized section reserves memory
space for a variable.
 The sections can have default names or
names given by the programmer.

SIEE, Slide 9 Copyrig

 Definition and names of Sections
 The programmer uses special directives to
identify the sections.
Initialized sections
Unitialized
sections,
Code or
code Variables reserve space
constants
for data

Named
sections, name .sect .usect
given by user

Unnamed
sections, .text .data .bss
default name

SIEE, Slide 10 Copyrig

 Example of sections
.sect ”init" Initialized named section: Initialization
tbl .int 1,2,3 of constants. Definition of address tbl

x .usect "vars",3 Uninitialized named section: x[3], y[1],

y .usect "result",1 Definition of address x and y.
.sect “code” Initialized named section: code

System Diagram

How are these sections DROM RAM

placed into the memory tbl[3] x[3]
areas shown?
EPROM 54x RAM
code CPU y

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 C54x Addressing Modes

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 Format of Data and Instructions, Internal
Busses of the C54x Family
 In the C54x DSP, the data and program
memories are organized in 16-bit words.
Data busses have a 16-bit width.
 Data and instructions are generally of size
N=16 bits.
 Some instructions may take several 16-bit
words.
 Some data operands may be double
precision and occupy 2 words.
 Internal busses: 2 data read, 1 data write
SIEE, Slide 13 Copyrig
 Terms from the User’s Guide
Term What it means
Smem 16-bit single data memory
operand 16-bit dual data memory operand used in dual-operand instructions
Xmem
and some single-operand instructions. Read through D bus.
Ymem 16-bit dual data-memory operand used in dual-operand instructions.
Read through C bus.
lk 16-bit long
constant 16-bit immediate data memory address (0 - 65,535)
dmad
pmad 16-bit immediate program memory address (0 - 65,535)
This includes extended program memory devices
src Source accumulator (A or B)
dst Destination accumulator (A or B)
PA 16-bit port (I/O) immediate address (0 - 65,535)

SIEE, Slide 14 Copyrig

 Immediate Addressing Mode #
 Instruction contains the value of the
operand. Value is preceded by #.
 Example: ADD #4,A
 Add the value 4 to the content of
accumulator A.
 Useful for initializations.
 Long (16 bits) or short values:
 For long values: instruction uses 2 words.

SIEE, Slide 15 Copyrig

 Immediate Addressing Mode #
 16 bit value Example:
 2 words, 2 cycles STM #1234h,AR2
 Initialization of ARi for Load AR2 with the value
example 1234h.

 Short value
 3, 5, 8, 9 bits constant Example:
 1 word, 1 cycle LD #6, DP
 To initialize short Load DP with the value 6.
length registers or bit
fields:
 DP, ASM …
 Not always available
SIEE, Slide 16 Copyrig
 Example: MMR (Memory Mapped Registers)
and Immediate Addressing
.sect ”init"  STM (STore to Memory-mapped
tbl .int 1,2,3 register) stores an immediate
value to the specified MMR or
x .usect "vars",3 Scratch address.
y .usect "result",1
.sect “code”
start: STM #tbl,AR1  #tbl is the 16-bit address of the
STM #x,AR2
first element of the array tbl.

0000
h  MMR = Memory Mapped Registers
MMRs

0060
h Scratch  Scratch memory
007F

SIEE, Slide 17 Copyrig

 Direct Addressing Mode @
 Direct addressing = random access from
a specified base address.
 The instruction contains an offset relative
to the base address.
 The base address can be the beginning of
a data memory page or the stack
pointer.
 The data memory is virtually divided in 512
pages of 128 words (512x128 = 216).
 Data Page DP relative direct address
 CPL bit (ComPiler Mode bit) = 0 in ST1
 Stack Pointer SP relative direct address
 CPL bit = 1 in ST1
SIEE, Slide 18 Copyrig
 Data memory pages
Addresses in Dec Hex Data memory
0 0000
Page 0 128 words

128 0080
Page 1 128 words

256 0100
Page 2 128 words
512 Pages

Page 511 128 words

65 535 FFFF

SIEE, Slide 19 Copyrig

 Direct Addressing Mode @
 For DP relative mode:
 The 16 bit address is split into 9 MSB and
7 LSB.
 The 7 LSB of the operand address are given
in the instruction,
 The 9 MSB are in the DP register.
 For SP relative mode
 The 7 bits given in the instruction are
used as an offset from the SP to obtain
the address.
 In both cases, only 7 bits are used in
the instruction for the operand
address.
SIEE, Slide 20 Copyrig
 Direct Addressing Mode @
DP relative, CPL = 0
15 - 8 7 6-0
Instruction Opcode I=0 dma

DP register 9-bit DP

Address 9-bit DP 7-bit dma

SP relative, CPL = 1
SP Register 16-bit Stack Pointer

+ 7-bit dma

Address 16-bit Data Memory Address

SIEE, Slide 21 Copyrig

 Direct Addressing Mode @, example
Addresses in Dec Hex Data memory
0 0000
Page 0 128 words
DP = 2, page 2
128 0080
Page 1 128 words
Offset in the
instruction = 1
256 0100 0
1 Address = 0101
128 words
Page 2 in hexadecimal
127

Page 3 to 510

Page 511 128 words

65 535 FFFF

SIEE, Slide 22 Copyrig

 Example
.sect ”init"
tbl .int 1,2,3

x .usect "vars",3
y .usect "result",1
.sect “code”
start: STM #tbl,AR1
STM #x,AR2

LD #x,DP  This instruction loads the upper

9 bits of address x into DP (in ST0)
LD @x+1,A  CPL = 0
ADD @x,A
ADD @x+2,A  To be sure that x and x+1 are in the
same page: use Blocking.

SIEE, Slide 23 Copyrig

 Direct Addressing Mode @, DP relative
 When DP is initialized, it allows single-
word single-cycle instructions with easy
to understand symbols for addresses.
 Defines 512 pages (selected by the 9 bits
of DP) of 128 words (selected by the 7
bits in instruction) in data memory.
 CPL is reset by:
 RSBX CPL ; CPL = 0 on reset
 Blocking of data in the same page
 In the linker command file:
 .bss : > RAM BLOCK = 128
 In the assembler file
 .bss x, 2, 1 ; specify all variables in one page
SIEE, Slide 24 Copyrig
 Direct Addressing Mode @, SP relative
 Used by the C compiler
 Useful for stack based operations
 Controlled by the CPL bit. Set by:
 SSBX CPL

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 Indirect Addressing Mode *ARi
 Compatible with pointers in C.
 8 ARi Auxiliary Registers to store the
addresses of the operands. They are used
as pointers.
 2 ARAU = Auxiliary Registers
Arithmetic Units to realize operations on
the addresses stored in the ARi.
 1 operand (Smem) or 2 operands
(Xmem, Ymem) can be specified by
indirect addressing in 1 instruction.
 Very efficient for DSP operations.

SIEE, Slide 26 Copyrig

 Indirect addressing mode *ARi
 AR0 can be used as an index.
 Support for circular addressing
 details in next slides
 Bit Reversed BR addressing for FFT
 ARi can be modified during the
instruction
 The possible modifications or operations on
ARi depend on the number of operands
specified by indirect addressing in the
instruction.
 Pointers (ARi) must be initialized before
use.
SIEE, Slide 27 Copyrig
 Circular buffer and addressing on C54x

Data Memory ARi BK

Start_address =
xxxxxxxxxxx00000 xxxxxxxxxxx00010 N=30=1 1 1 1 0

ARi

End_address =
xxxxxxxxxxx11111

SIEE, Slide 28 Copyrig

 Circular addressing with C54x
 Circular indirect addressing mode: %
 *ARi-%, *ARi+%, *ARi-0%, *ARi+0%,
*ARi(lk)%
 In dual operand mode Xmem, Ymem:
 *ARi+0% only valid mode
 To perform a decrement, store a negative value
in AR0.
 BK register:
 Stores the size N of the circular buffer.
 Must be initialized before use.
 There may be several circular buffers at
different addresses at the same time but
with the same length.
SIEE, Slide 29 Copyrig
 Limitations on Start Addresses of Circular
Buffers
 If N is written on nb bits in binary, the
start address must have its nb LSB at 0:
 Examples:
 for N=32, 6 LSB of start address =0
 for N=30, 5 LSB of start address =0
 To access a circular buffer:
 Initialize BK with N (nb bits)
 Choose 1 ARi as a pointer
 The effective start address of the buffer is the
value in ARi with its nb LSB at 0.
 The end address = start addess +N-1.

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 Indirect Addressing: ARi Specifications and
Options for Modification
 For a single operand Smem:
 16 possible options for Smem,
 4 bits for the option + 3 bits for the ARi.
 The address is specified by 4 + 3 = 7 bits.
 For 2 operands Xmem, Ymem:
 Only 4 ARi can be used: AR2 to AR5.
 Only 4 possible options for the operations
on the ARi.
 Each address needs 2 + 2 = 4 bits, so 2x4=8
bits are necessary for the 2 addresses.

SIEE, Slide 31 Copyrig

 Indirect Addressing Options for ARi
modifications, Single operand Smem
Option Syntax Action Affected by:
No Modification *ARn no modification to ARn
Increment / *ARn+ post increment by 1
Decrement *ARn- post decrement by 1
Indexed *ARn+0 post increment by AR0 AR0
*ARn-0 post decrement by AR0
Circular *ARn+% post increment by 1 - circular BK
*ARn-% post decrement by 1 - circular
*ARn+0% post increment by AR0 - circular BK, AR0
*ARn-0% post decrement by AR0 - circular
Bit-Reversed *ARn+0B post inc. ARn by AR0 with reverse carry AR0
*ARn-0B post dec. ARn by AR0 with reverse carry (=FFT size/2)

Pre-modify *ARn (lk) *(ARn+LK), ARn unchanged

*+ARn (lk) *(ARn+LK), ARn changed
*+ARn (lk)% *(ARn+LK), ARn changed - circular BK
*+ARn pre-increment by 1, during write only
Absolute *(lk) 16-bit lk is used as an absolute address
See Absolute Addressing

SIEE, Slide 32 Copyrig

 Indirect Addressing Options for ARi
for Double Operand Xmem and Ymem

Option Syntax Action Affected by:

No Modification *ARn no modification to ARn
Increment / *ARn+ post increment by 1
Decrement *ARn- post decrement by 1
Circular *ARn+0% post increment by AR0 - circular BK, AR0

SIEE, Slide 33 Copyrig

 Indirect Addressing Mode *ARi
 There are latencies to consider:
 no latency STM, MVDK
 1 cycle MVDM, MVKD, MVDD
 2 cycles STLM, ST, etc
 ARi are read/modified in access phase, so the
debugger will appear to show ARs changing early.
 CMPT must = 0 (bit5, ST1)
 is 0 on reset
 is forced to 0 with RSBX CMPT
 CMPT (Compatibility Mode Bit) = 1 allows
‘C2x/’C2xx/C5x styled ARP operation for ARs.
But this mode is discouraged.

SIEE, Slide 34 Copyrig

 Example
.sect ”init"
tbl .int 1,2,3

x .usect "vars",3
y .usect "result",1
.sect “code”
start: STM #tbl,AR1
STM #x,AR2  Initialization of AR1 and AR2.

LD *AR1+,A
 Copy the values from table in DROM
STL A,*AR2+ ;... to RAM (via A). Indirect addressing
allows sequential access to data.
LD #x,DP System Diagram
LD @x+1,A
ADD @x,A DROM RAM
ADD @x+2,A
tbl[3] x[3]

EPROM 54x RAM

code CPU y
SIEE, Slide 35 Copyrig
 Absolute Addressing Mode *()
 Allows us to specify a complete operand
address in an instruction. *(Address)
 The address can be in data, program or
IO memory. 16 bits.
 2 words, 2 cycles.
Data Memory
Addr Data
. .
.data . .
x: .word 1000h x: 01FF 1000
y: .word 0500h y: 0200 0500
. .
.text . .
LD *(x),A Acc A 0 0 0 0 0 0 1 0 0 0
ADD *(y),A 0 0 0 0 0 0 1 5 0 0

SIEE, Slide 36 Copyrig

 Example
.sect ”init"
tbl .int 1,2,3 System Diagram
X .usect "vars",3 DROM RAM
Y .usect "result",1
.sect “code”
tbl[3] x[3]
Start: STM #tbl,AR1
STM #x,AR2 EPROM 54x RAM
code CPU y
LD *AR1+,A
STL A,*AR2+ ;...
LD #x,DP

LD @x+1,A
ADD @x,A
ADD @x+2,A

STL A,*(y)  Save accumulator A at address y

SIEE, Slide 37 Copyrig

 MMR Memory Mapped Registers Addressing
 MMRs are in page 0 of data memory.
 They can be accessed by some specific MMR
instructions allowing simple access to page 0.
 In these cases DP, SP and CPL are ignored
LDM, STLM MMR  Acc
STM #  MMR
PSHM, POPM MMR  Stack
MVDM, MVMD MMR  Dmem
MVMM AR, SP  AR, SP

0000h
MMRs Tip: use the .mmregs directive
to allow MMR names to be
interpreted as addresses
0060h
Scratch
007Fh

SIEE, Slide 38 Copyrig

 MMR Memory Mapped Registers
Addr. Addr.
Name (Hex) Description Name (Hex) Description
IMR 0000 Interrupt Mask Register AR0 0010 Address Register 0
IFR 0001 Interrupt Flag Register AR1 0011 Address Register 1
----- 2-5 Reserved AR2 0012 Address Register 2
ST0 0006 Status 0 Register AR3 0013 Address Register 3
ST1 0007 Status 1 Register AR4 0014 Address Register 4
AL 0008 A accumulator low (A[15:00]) AR5 0015 Address Register 5
AH 0009 A accumulator high (A[31:16]) AR6 0016 Address Register 6
AG 000A A accumulator guard (A[39:32]) AR7 0017 Address Register 7
BL 000B B accumulator low (B[15:00]) SP 0018 Stack Pointer Register
BH 000C B accumulator high (B[31:16]) BK 0019 Circular Size Register
BG 000D B accumulator guard (B[39:32]) BRC 001A Block Repeat Counter
T 000E Temporary Register RSA 001B Block Repeat Start Address
TRN 000F Transition Register REA 001C Block Repeat End Address
PMST 001D PMST Register
------- 01E-01F Reserved

Note: XPC and Peripheral MMR locations are device dependent

SIEE, Slide 39 Copyrig
 MMR Memory Mapped Registers Addressing
 When accessing MMRs, latencies need
to be considered.
 STM (STore to Memory-mapped
register):
 Stores an immediate value to the specified
MMR or Scratch memory address.
 Writes the values during the access phase
of the pipeline to avoid latencies.

SIEE, Slide 40 Copyrig

 Exercise on Addressing Modes of C54x
Given: DP=0 DP=4 DP=6
Address/Data (HEX) 60 20 200 100 300 100
CPL=0 61 120 201 60 301 30
CMPT=0 62 202 40 302 60
Addr Mode Program A B DP AR0 AR1 AR2
LD #0,DP
STM #2,AR0
STM #200h,AR1
STM #300h,AR2 120
LD @61h,A
ADD *AR1+,A
SUB @60h,A,B 260
ADD *AR1+,B,A
LD #6,DP
ADD @1,A 390
ADD *AR2+,A
SUB *AR2+,A
SUB #32,A 380
ADD *AR1-0,A,B
SUB *AR2-0,B,A
STL A,62h

SIEE, Slide 41 Copyrig

 Exercise on Addressing Modes of C54x
Given: DP=0 DP=4 DP=6
Address/Data (HEX) 60 20 200 100 300 100
CPL=0 61 120 201 60 301 30
CMPT=0 62 202 40 302 60
Addr Mode Program A B DP AR0 AR1 AR2
IMMED LD #0,DP 0
MMR STM #2,AR0 2
MMR STM #200h,AR1 200
MMR STM #300h,AR2 300
DIRECT LD @61h,A 120
INDIRECT ADD *AR1+,A 220 201
DIRECT SUB @60h,A,B 200
INDIRECT ADD *AR1+,B,A 260 202
IMMED LD #6,DP 6
DIRECT ADD @1,A 290
INDIRECT ADD *AR2+,A 390 301
INDIRECT SUB *AR2+,A 360 302
IMMED SUB #32,A 340
INDIRECT ADD *AR1-0,A,B 380 200
INDIRECT SUB *AR2-0,B,A 320 300
DIRECT STL A,62h

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 C55x Addressing Modes

SIEE, Slide 43 Copyrig

 Format of Data and Instructions, Internal
Busses for the C55x Family
 Unified program-data memory map:
byte-aligned for program and word-
aligned for data.
 Has a variable length instruction set (8-
16-24-32-40-48 bits).
 Program address bus: 24 bits, 16 Mbytes
 4 instructions bytes are fetched at a time
 6 bytes are decoded at a time
 Internal data busses: 3 data read, 2 data
write
 Data addresses: 8 Mwords of 16 bits
segmented into 64K pages, 23-bit address.
A 24-bit address is automatically generated
by the hardware by adding a LSB = 0.
SIEE, Slide 44 Copyrig
 C55x Addressing Modes
 Direct
 Indirect
 Absolute
 MMR
 Loading constants in registers (e.g.
immediate)
Algorithm System Diagram
y = x0 + x1 + x2 ROM RAM 55xx
tbl[3] x[3] CPU
This algorithm will again be used I P
as an example for the different y = x0 + x1 + RAM
addressing modes. x2
D A
y

SIEE, Slide 45 Copyrig

 Loading Constants in Registers #
 Used for initialization of registers.
 Used to be called immediate addressing
 Addressing registers:
 16-bits long: ARi, DP, CDP (Coefficient
Data Pointer)
 23-bits long: XARi, XDP, XCDP
 The 7 MSB of Xreg specify the 64K page.
 The ARAU auxiliary Register
Arithmetic Unit is 16 bits wide: update
of ARi and CDP are done modulo 64K.
 Initialization example: AMOV
#adr,XAR3
SIEE, Slide 46 Copyrig
 Example
x .usect “vars”,4
y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code” 23-bit XARn
X 16-bit ARn
indir: AMOV #x,XAR0
AMOV #tbl,XAR6
= 23-bit address

ROM RAM 55xx

tbl[3] x[3] CPU
I P
y = x0 + x1 + RAM
x2
D A
y

SIEE, Slide 47 Copyrig

 Direct Addressing Mode @
 Gives the instruction a positive 7bit
offset from DP (non-aligned).
 In the case where the bit CPL=0 in ST1.
 Calculation in the ARAU modulo 64K
23-bit XDP
X 16-bit DP

+ 7-bit @x

= 23-bit address

SIEE, Slide 48 Copyrig

 Example
x .usect “vars”,4
y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code”

ROM RAM 55xx

tbl[3] x[3] CPU
ADD: MOV @(x+0),AC0
ADD @(x+1),AC0 I P
y = x0 + x1 + RAM
ADD @(x+2),AC0 x2
D A
y

How is XDP initialized?

SIEE, Slide 49 Copyrig
 Example
x .usect “vars”,4
y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code”

A in AMOV means in AD-phase.

The MDP has to be reloaded

every time we cross a 64K page.

dir: AMOV #x,XDP  Constant value contained

in instruction opcode
ADD: MOV @(x+0-x),AC0  (-x) used in instruction to tell
ADD @(x+1-x),AC0 the assembler HOW to create the
ADD @(x+2-x),AC0 7-bit offset from non-aligned XDP

SIEE, Slide 50 Copyrig

 Directive .dp for Direct Addressing
 Instead of using (-x) to help the assembler
calculate the proper 7-bit offset,
 We can use the directive .dp to set the base address
for the assembler calculation of the 7-bit offset.
 .dp base_address

.dp x The @addr in the instruction is

interpreted as a 23-bit address.
dir: AMOV #x,XDP
The .dp provides a compile-time base
ADD: MOV @(x+0),AC0 address.
ADD @(x+1),AC0 The assembler determines the 7-bit
ADD @(x+2),AC0 offset by: (@addr-.dp_value)&7F

SIEE, Slide 51 Copyrig

 Indirect Addressing Mode *ARi
 Similar to the case of the C54x, but:
 23-bit addresses,
 Extended registers XARi on 23 bits specify
the complete address,
 ARAU calculates on 16 bits (modulo 64K),
 8 ARi 16-bit pointers used in the
instructions.
23-bit XARn
X 16-bit ARn

= 23-bit address

SIEE, Slide 52 Copyrig

 Indirect Addressing Options for Pointer ARi
Modifications
*ARn No Modify
*ARn(T0/1) No Modify w/offset
*ARn(#k16) No Modify w/offset
*ARn +/- Post Modify (+/-)
*(ARn +/- T0/1) Post Modify (+/- by T0/1)
*+/- ARn (+/-) Pre Modify
*+ ARn(#k16) (+ #k16) Pre Modify
*(ARn +/- T0B) Bit reversed using T0
*CDP No Modify
*CDP(#k16) No Modify w/offset
*CDP +/- Post Modify (+/-)
*+CDP(#k16) (+ #k16) Pre Modify

 Assumes ST2_55ARMS=0 and ST1_55C54CM=0.

 The reset condition is C54CM=1.
SIEE, Slide 53 Copyrig
 Address Register Mode Select Bit ARMS
 ARMS bit = bit 15 of ST2_55
 ARMS=0 at reset DSP mode
 For ARMS=1, CONTROL mode
 T1 cannot be used as offset
 No bit reversed addressing
 New mode:
 *ARi(short(#k3)) or *SP(short(#k3))
 Useful for the C compiler
 The C compiler sets ARMS = 1.

SIEE, Slide 54 Copyrig

 Modifying TAs Registers
 TAx registers = T0-3, AR0-7.
 Special instructions:
 AADD, ASUB, AMOV
 Can be used to modify TAs registers
during the address (AD) phase of the
pipeline, while instructions without A
operates during the execution (X) phase.
 They only work on the TAx registers.
Examples:

AADD #const,AR1
ASUB AR1,T0
AMOV #k23,XAR2

SIEE, Slide 55 Copyrig

 Example
x .usect “vars”,4
y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code”

.dp x
indir: AMOV #x,XAR0
AMOV #tbl,XAR6

COPY: MOV +
*AR6+, +
AR0+
MOV *AR6+,*AR0+
MOV *AR6 ,*AR0
ROM RAM 55xx
dir: AMOV #x,XDP CPU
tbl[4] x[4]
ADD: MOV @(x+0),AC0 I P
y = x0 + x1 + RAM
ADD @(x+1),AC0 D A
ADD @(x+2),AC0 x1 y

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 Circular Buffer Addressing Mode

Buffer Start Address = Xeven[22:16] BSAxx[15:0]

Offset into Buffer = + ARn/CDP

Calculated Address = Xeven[22:16] BSAxx + ARn/CDP

Buffer Length = BKzz[15:0]

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 Circular Buffer Addressing Mode
Buffer
Block size
Offset Xeven Start
Register
Address
AR0
XAR0[22:16] BSA01
AR1
BK03
AR2
XAR2[22:16] BSA01
AR3
AR4
XAR4[22:16] BSA01
AR5
BK03
AR6
XAR6[22:16] BSA01
AR7
CPD XCDP[22:16] BSAC BKC
The even XARn (i.e. 0,2,4,6) determines the 64K Page
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 Selecting Circular or Linear Addressing
Mode
 Use the LSB of Status word ST2_55
15 9 8 7 6 5 4 3 2 1 0
C A A A A A A A A
D R R R R R R R R
other bits or rsvd P 7 6 5 4 3 2 1 0
ST2_55 L L L L L L L L L
C C C C C C C C C

0 = linear mode 1 = circular mode

(default)
 Set or reset status bits:
BSET AR5LC ;AR5 in circular mode
BCLR AR3LC ;AR3 in linear mode

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 Circular Buffer Exercise
Use AR4 as a circular pointer to x{5}: x
A
ARR44 7 0
1 1
.sect “data”
x .int 7,1,9,6,2 ;init data 9 2
.sect “code” 6 3
__________________
AMOV #x,XAR4 ;init XAR
__________________
MOV #x,BSA45 ;init start addr 2 4
__________________
MOV #5,BK47 ;init length
__________________
MOV #0,AR4 ;init AR4 to top
__________________
BSET AR4LC ;set AR4 to circ

MOV #3,T0 ;index

MOV *(AR4+T0),AC0 ;AC0 =_7__, AR4 =_3__
MOV *+AR4(#4h),AC1 ;AC1 =_9__, AR4 =_2__
MOV *AR4(T0),AC2 ;AC2 =_7__, AR4 =_2__
Results are
cumulative

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 Comparison of C54x and C55x circular
addressing modes
 3 BK registers in C55X instead of 1 in
C54x: allows for several simultaneous
circular buffers with different size.
 In C54x, circular addressing mode is
specified in indirect addressing type %
in the instructions.
 In C55x, the mode in set in status
register ST2_55 for each register (linear
or circular). No memory alignment
constraint.

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 Absolute Addressing *(#)
 *(#) = 23 bit address
 Fast: no initialization,
 But long instruction because it contains
the 23 bit address.
 If the address is in the 64K work page, it
is possible to specify a 16-bit only
address:
 abs16*(#label)

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 Example
X .usect “vars”,4
Y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code”

.dp x
indir: AMOV #x,XAR0
AMOV #tbl,XAR6

COPY: MOV *AR6+,*AR0+

MOV *AR6+,*AR0+
MOV *AR6 ,*AR0
dir: AMOV #x,XDP
ROM RAM 55xx
ADD: MOV @(x+0),AC0 tbl[4] x[4] CPU
ADD @(x+1),AC0
ADD @(x+2),AC0 I P
y = x0 + x1 + RAM
x2
D A
STORE: MOV AC0,*(#y) y

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 MMR Addressing Using mmap()
 MMRs are located between 0 and 5F.
 Scratch memory is located between 60
and 7F.
 mmap() forces bits 22:7 to zero.
 Useful to access MMR and scratch memory
without initialization of addressing
registers.
 Useful only for direct addressing.
; write #1234h to ST0_55
AMOV #0,XDP ; write #1234h to ST0_55
MOV #1234h, @(ST0_55 - 0) MOV #1234h, mmap(@ST0_55)

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 Access Peripheral Registers
 The I/O space is internal.
 The PDP (Peripheral Data Pointer)
register is used to access ports using
direct addressing.
 It is a 9bit register. Its value is
concatenated with the 7 bits in the
instruction to obtain a full 16-bit
peripheral address.
 The port() modifier selects the
peripheral map

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 Access Peripheral Registers
I/O - Peripheral
Memory Map
0000h
DMA
abs: MOV port(#addr),T1
McBSP
dir: MOV #addr,PDP EHPI
MOV T1,port(@addr)
EMIF
indir: AMOV #addr,AR4 Timers
MOV port(*AR4),T1 Power Dwn
Instr Cache
GPIO
FFFFh

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 Directives for Addressing Modes
 3 Mode bits affect addressing:
 ARMS: Address Register Mode Select
 C54CM: C54 Compatibility Mode
 C54CM=1 on reset, native C55x coding
requires C54CM=0.
 CPL: ComPiLer Mode
 3 directives help the assembler to check
the syntax and responds with ERROR
in case of inconsistency:
 .arms_on or .arms_off
 .c54cm_on or .c54cm_off
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 .cpl_on or .cpl_off Copyrig
 Modifying Status Bits

BSET/BCLR bit_name
BCLR ARMS ;clear ARMS
BSET CPL ;set CPL
BCLR C54CM ;clear C54CM

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 Addressing Exercise
 The initial state of 02_0105h 21h XAR1 02_0106h
each instruction is x = 02_0106h 30h
shown here... 02_0107h 40h XDP 02_0106h
 Below, write down 02_0108h 50h
the state after each instr T0 2 .dp x
02_0206h 60h
AR1 AC0 T1 02_0106h ST1M40
MOV @(x+1),AC0
MOV @(x+80h),AC0
MOV T0,*AR1+
MOV *(#x),AC0
MOV #4,@(x+128)
MOV *(AR1+T0),T1
BSET M40
MOV @(x+2),AC0
MOV *AR1(T0),AC0
MOV *AR1(#100h),T1
MOV @(x+129),AR1
MOV *+AR1(#-1),AC0

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 Addressing Exercise – Solution
 The initial state of 02_0105h 21h XAR1 02_0106h
each instruction is x = 02_0106h 30h
shown here... 02_0107h 40h XDP 02_0106h
 Below, write down 02_0108h 50h
the state after each instr T0 2 .dp x
02_0206h 60h
AR1 AC0 T1 02_0106h ST1M40
MOV @(x+1),AC0 40h
MOV @(x+80h),AC0 30h
MOV T0,*AR1+ 107h 2
MOV *(#x),AC0 30h
MOV #4,@(x+128) 4
MOV *(AR1+T0),T1 108h 30h
BSET M40 1
MOV @(x+2),AC0 50h
MOV *AR1(T0),AC0 106h 50h
MOV *AR1(#100h),T1 106h 60h
MOV @(x+129),AR1 40h
MOV *+AR1(#-1),AC0 105h 21h

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SIEE, Slide 71 Copyrig
 Circular buffer and circular addressing
 A circular buffer of length N is a block
of contiguous memory words addressed
by a pointer using a modulo N
addressing mode.
 The 2 extreme words of the memory block
are considered as contiguous.
 Characteristics of a circular buffer:
 Instead of moving the N data in memory,
just modify the pointers.
 When a new data x(n) arrives, the pointer
is incremented and the new data is written
in place of the oldest one.

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 Trace of Memory and Pointer in a Circular
Buffer of Length 3
 Very often used for FIR filters.

Time n Time n+1 Time n+2 Time n+3

x(n-1) x(n-1) x(n+2) x(n+2)
x(n) x(n) x(n) x(n+3)
x(n-2) x(n+1) x(n+1) x(n+1)

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