Chapter 5

Arithmetic and Logic
Chapter 5
The AVR microcontroller

and embedded
systems
using assembly and c
AVR Microcontroller and Embedded System Using © 2011 Pearson Higher Education,
Assembly and C Upper Saddle River, NJ 07458. • All Rights
Objectives
• The concept of signed numbers and 2’s complement

• Addition and subtraction instructions
• Carry and overflow
• Logical instruction and masking
• Compare instruction and branching
• Shift, Rotate and Data serialization
• BCD, Packed BCD and ASCII conversion.
Some ideas
• 100 – 34 = ?
• 99 – 34 = ?
• 100 – 34 = (99-34) + 1
• 34 – 19 = ?
• 34 +100 -19 – 100 = 34 + (99-19)+1 -100
• 100000000 – 00101101 = ?
• =011111111 – 00101101 + 1 =A
• 010110110 – 00101101 =
• 010110110 + A – 100000000 =
ADD instructions
ADD Rd,Rr ;Rd = Rd + Rr ( Direct or immediate are not supported)
ADD instructions
ADD Rd,Rr ;Rd = Rd + Rr ( Direct or immediate are not supported)
ADC instructions
ADC Rd,Rr ; Rd = Rd + Rr + C ; it means add two registers along with C flag
16-bit addition with ADC instruction
16+7 = 23
17
SUB instruction
SUB Rd,Rr ;Rd = Rd - Rr ( immediate are not supported)
SUBI Rd,K ; Rd = Rd – K
W stands for Word which means 16 bits
SUB: Example
SBC instruction
SBC Rd,Rr ;Rd = Rd – Rr-C ( immediate are not supported)
SBCI Rd,Rr ;Rd = Rd – K-C
27 62 (H)
- 12 96 (H)
-----------
14 CC (H)
Multiplication
Division
There is no division instruction available in AVR. However, we can divided numbers by
repeated subtraction as shown in the example below:
.DEF NUM,R20
.DEF DEN,R21
.DEF QOT,R22
LDI NUM, 45
LDI DEN,10
CLR QOT
L1: SUB NUM,DEN

BRCS DONE
INC QOT
RJMP L1
DONE: ADD NUM,DEN
Logic Instructions
AND Rd,Rr ;Rd = Rd AND Rr
ANDI Rd,K
OR Rd,Rr ;Rd = Rd OR Rr
EOR Rd,Rr ;Rd = Rd XOR Rr ( immediate are not supported)
COM Rd ;Rd = 1’ Complement of Rd (11111111 – Rd)
NEG Rd ;Rd = 2’ Complement of Rd (100000000 – Rd)
• AND is used to clear an specific bit/s of a byte

• OR is used to set an specific bit/s of a byte
00 0 00 0 00 0
01 0 01 1 01 1
10 0 10 1 10 1
11 1 11 1 11 0
AND OR XOR
IF YOU AND ‘A’ WITH 1, WHAT DO YOU GET? A

IF YOU AND ‘A’ WITH 0, WHAT DO YOU GET? 0
AND OPERATION IS USED TO CLEAR BIT(S) IN A REGISTER
ANDI R17, 0B11101111 ; THIS WILL CLEAR BIT 4 ONLY IN R17
00 0
01 0
10 0
11 1
AND
IF YOU AND ‘A’ WITH 1, WHAT DO YOU GET? A

IF YOU AND ‘A’ WITH 0, WHAT DO YOU GET? 0
AND OPERATION IS USED TO CLEAR BIT(S) IN A REGISTER BY

ANDING WITH 0
EX. WRITE A CODE TO CLEAR BITS 0, 2, 5, 7 IN R17
ANDI R17, 0B01011010 ; THIS WILL CLEAR BIT 0, 2, 5, 7
00 0
01 1
10 1
11 1
OR
IF YOU OR ‘A’ WITH 1, WHAT DO YOU GET? 1

IF YOU OR ‘A’ WITH 0, WHAT DO YOU GET? A
OR OPERATION IS USED TO SET BIT(S) IN A REGISTER BY ORING WITH 1
EX. WRITE A CODE TO SET BITS 1, 3, 6, 7 IN R18
ORI R18, 0B11001010 ;
SBR, CBR FOR GPRs BUT CAN ONLY SET OR CLEAR ONE BIT AT A TIME
SBI AND CBI – THESE APPLY ONLY TO IO REGISTERS

00 0
01 1
10 1
11 0
XOR
IF YOU XOR ‘A’ WITH 1, WHAT DO YOU GET? A’

IF YOU XOR ‘A’ WITH 0, WHAT DO YOU GET? A
XOR OPERATION IS USED TO TOGGLE BIT(S) IN A REGISTER
EX. WRITE A CODE TO TOGGLE BITS 0, 2, 5, 7 IN R17
ANDI R17, 0B10100101 ;
Setting and Clearing bits
AND Rd,Rr ;Rd = Rd AND Rr
OR Rd,Rr ;Rd = Rd OR Rr
EOR Rd,Rr ;Rd = Rd XOR Rr ( immediate are not supported)
COM Rd ;Rd = 1’ Complement of Rd (11111111 – Rd)
NEG Rd ;Rd = 2’ Complement of Rd (100000000 – Rd)
• AND is used to clear an specific bit/s of a byte

• OR is used to set an specific bit/s of a byte
AND OR
EX-OR Function
QUIZ:
IF YOU XOR A REGISTER WITH $FF, WHAT DO YOU GET?

1’S COMPLEMENT OF THE REGISTER
LDI R18,$FF
EOR R17,R18
IF YOU XOR A REGISTER WITH ITSELF, WHAT DO YOU GET?

EOR R16,R16
LDI R16,0
CLR R16
Branch and CP Instructions
CP Rd, Rr ;Rd – Rr (only flags are set)
AFTER CP, YOU USE THE BRANCH INSTRUCTION
• BRVC is used to branch when oVerflow is clear to zero

• BRVS is used to branch when oVerflow is set to one
ROR instruction
ROR Rd ;Rd (only flags are set)
In ROR, as bits are rotated from left to right, the carry flag enters the MSB
and the LSB exits to the carry flag. In other words, in ROR the C is moved to
the MSB, and the LSB is moved to the C.
See what happens to 0010 0110 after running 3 ROR instructions:
CLC ;make C = 0 (carry is 0 )

LDI R20 , 0x26 ;R20 = 0010 0110
ROR R20 ;R20 = 0001 0011 C = 0
ROR R20 ;R20 = 0000 1001 C = 1
ROR R20 ;R20 = 1000 0100 C = 1
ROL instruction
ROL Rd ;Rd (only flags are set)
ROL. In ROL, as bits are shifted from right to left, the carry flag enters the LSB and
the MSB exits to the carry flag. In other words, in ROL the C is moved to the LSB,
and the MSB is moved to the C.
SEC ;make C = 1 (carry is 0)

LDI R20,0x15 ;R20 = 0001 0101
ROL R20 ;R20 = 0010 1011 C = 0
ROL R20 ;R20 = 0101 0110 C = 0
ROL R20 ;R20 = 1010 1100 C = 0
ROL R20 ;R20 = 0101 1000 C = 1
Parity error detection system – SERIAL Communication Systems
Data is sent with even parity or odd parity – you add one extra bit as
a parity bit to the data packet
Even parity means the number of ones in the data sent out is EVEN
Tx------------------------------------( ) ---------------------------------------Rx
10011010
Send data channel will add noise
For odd parity scheme:

Data : 10011011 10011010
Count the number of 1’s

Generate parity Checking parity
For even parity scheme:
Data is stored at $100 in RAM
Algorithm for generating parity bit:
1.Load the data value

2.Clear the parity bit
7-bit data value 3.Count the number of 1’s in the data
P c 4.Check if the number of 1’s is ODD or EVEN
5.If it is ODD, then P -> 1, else P -> 0
6.Store data value
Algorithm for checking parity:

01001101
1.Load the data value received from Tx
00100110 1 2.Count the number of 1’s in the data
3.Check if the number of 1’s is ODD or EVEN
4.If it is ODD, then indicate error, else no error
Data is stored at $200 in RAM
1. WRITE A PROGRAM FOR THE TRANSMITTER MODULE IN A SERIAL
COMMUNICATIONS SYSTEM TO GENERATE PARITY FOR A 7-BIT
DATA VALUE STORED IN RAM LOCATION $100. CONSIDER ODD
PARITY SCHEME.
2. WRITE A PROGRAM FOR THE RECEIVER MODULE TO CHECK. IF

THERE IS AN ERROR IN THE RECEIVED DATA. ASSUME EVEN
PARITY SCHEME IS USED. IF THERE IS ERROR IN DATA, THEN
STORE $FF IN R31 ELSE STORE 0
Counting 1s in a byte
Data Serialization
1010000011
SBI DDRB,1 SBI DDRB,1

LDI R16,8 LDI R16,8
LDI R17,0x41 LDI R17,0x41
SBI PORTB,1 SBI PORTB,1
BACK: ROR R17 BACK: ROL R17

BRCC ZERO BRCC ZERO

RJMP NXT RJMP NXT
ZERO: CBI PORTB,1 ZERO: CBI PORTB,1
NXT: DEC R16 NXT: DEC R16
BRNE BACK BRNE BACK
ROR R17 ROL R17

8 bit data bus
Microcontroller
Rx
Serial device
Tx
• 41H = 0100 0001
• PORT B PIN 1 (PB1) – THIS IS THE OUTPUT PIN

WHERE A SERIAL DEVICE IS CONNECTED
• 1. 00100000 1 – SET PB1 (SBI PORTB,1)

• 2. 10010000 0 – CLEAR PB1 (CBI PORTB,1)
• 3. 01001000 0 – CLEAR PB1 (CBI PORTB,1)
• 4. 00100100 0 - CLEAR PB1 (CBI PORTB,1)
Data Serialization
CBI DDRC,7 SEC

LDI R16,8 SET CARRY
CLC
CLC
BACK: SBIC PINC,7 CLEAR CARRY
SEC
SBIS PINC,7 Serial.read()
CLC
ROR R20 Serial.available()
DEC R16
BRNE BACK
LSL Instruction
LSL Rd ;logical shift left
In LSL, as bits are shifted from right to left,

0 enters the LSB and the MSB exits to the
carry flag. In other words, in LSL 0 is
moved to the LSB, and the
MSB is moved to the C.
this instruction multiplies content of the register by 2 assuming that after

LSL the carry flag is not set.
In the next code you can see what happens to 00100110 after running 3 LSL
instructions.
CLC ;make C = 0 (carry is 0 )
LDI R20 , 0x26 ;R20 = 0010 0110(38) c = 0
LSL R20 ;R20 = 0100 1100(74) C = 0
LSL R20 ;R20 = 1001 1000(148) C = 0
LSL R20 ;R20 = 0011 0000(98) C = 1 as C=1 and content of R20
;is not multiplied by 2
0000 0100 = 4 LSR R20
0000 1000 = 8
0001 0000 = 16 1000 0000 = 128
0010 0000 = 32 0100 0000 = 64
0100 0000 = 64 0010 0000 = 32
1000 0000 = 128 0001 0000 = 16
0000 0000 = 0, C = 1 0000 1000 = 8
0000 0100 = 4
LSL R20
EX2: R20 / 9
EX1: R20 X 9
R20 = 0000 1000 R20 = 1000 0001
LSL R20 LSR R20
0001 0000 0100 0000
LSL R20 LSR R20
0010 0000 0010 0000
0100 00000 0001 0000
1000 0000 0000 1000
0000 0000 0000 0100

WRITE A PROGRAM TO MULTIPLY THE CONTENTS OF R21 BY 10 WITHOUT
USING MUL INSTRUCTION OR REPEATED ADDITION. (LSL)
WRITE A PROGRAM TO DIVIDE THE CONTENTS OF R22 BY 10 WITHOUT

USING REPEATED SUBTRACTION. (LSR)
LSR Instruction
LSR Rd ;Rd (only flags are set)
In LSR, as bits are shifted from left to

right, 0 enters the MSB and the LSB exits
to the carry flag. In other words, in LSR
0 is moved to the MSB, and
the LSB is moved to the C.
this instruction divides content of the register by 2 and carry flag contains
the remainder of division.
In the next code you can see what happens to 0010 0110 after running 3 LSL
instructions.
LDI R20,0x26 ;R20 = 0010 0110 (38)

LSR R20 ;R20 = 0001 0011 (19) C = 0
LSR R20 ;R20 = 0000 1001 (9) C = 1
LSR R20 ;R20 = 0000 0100 (4) C = 1
ASR Instruction
ASR Rd ;Rd (only flags are set)
ASR means arithmetic shift right. ASR

instruction can divide signed number by 2.
In LSR, as bits are shifted from left to
right, MSB is held constant and the LSB
exits to the carry flag. In other words
MSB is not changed but is copied to D6,
D6 is moved to D5, D5 is moved to D4
and so on.
In the next code you can see what happens to 0010 0110 after running 5 ASL
instructions.
LDI R20 , 0D60 ;R20 = 1101 0000(-48) c = 0
LSL R20 ;R20 = 1110 1000(-24) C = 0
LSL R20 ;R20 = 1111 0100(-12) C = 0
LSL R20 ;R20 = 1111 1010(-6) C = 0
LSL R20 ;R20 = 1111 1101(-3) C = 0
LSL R20 ;R20 = 1111 1110(-1) C = 1
R20 = 1011 1000 , R20 = -0100 1000 = -72
LSR R20; R20 = 0101 1100; +92
ASR R20, R20 = 1101 1100 ; -00100100 = -36
1101 1100 0
LSR Limitation
SWAP Instruction
Swapping Nibbles in a Byte
BCD, Packed BCD and ASCII conversion.
•BCD
•ASCII Codes – 7 bit code : 128 codes
BCD Codes
Packed BCD
BCD1 BCD0
ASCII and BCD Codes for Digits 0–9
ASCII CODE: 7 bit code = 128 combinations
DIGITS 0 TO 9: $30 to $39
A = $41
a = $61
“ “ = $20
Enter key = $0D = 13
59
0000
0001 0101 1001 – BCD NUMBER
0010 LDI R18,59
0011 R18 = 32+16+8+2+1

00111011
0100
TABLE OF ASCII VALUES
0101
0000 0101 - 5
0110 0000 1001 - 9
0111 7
LDI R16,7
1000
1001 0000 0111 = R16
PACKING OF BCD NUMBERS – SAVING MEMORY
GIVEN TWO DECIMAL DIGITS IN ASCII

39H, 35H
FORM, PACK THEM INTO ONE BYTE
95H
R20 = 39H, R21 = 35H
STORE RESULT IN R22
R20 = 09, R21 = 05 BY ANDING WITH $0F LDI R20,$39

LDI R21,$35
SWAP R20; R20 = 90
ANDI R20, $0F ; R20 = 09
OR R20,R21; R20 = 95H ANDI R21, $0F, ; R21 = 05
SWAP R20 ; R20 = 90
OR R20,R21 ; R20 = 95
MOV R22,R20
UNPACKING OF BCD NUMBERS – FOR DISPLAY
GIVEN A PACKED BCD NUMBER, UNPACK AND CONVERT

TO ASCII TO BE DISPLAYED ON AN LCD CONNECTED TO
PORT C.
$95 SEPARATE -> $90, $05
95 ON THE LCD SCREEN

39, 35
LDI R20, $95

MOV R21,R20
ANDI R20, $F0 ; R20 = 90

SWAP R20 ; R20 = 09
ANDI R21,$0F ; R21 = 05
ORI R20,$30
OUT PORTC,R20
ORI R21,$30
OUT PORTC,R21
Packed BCD to ASCII conversion
To convert packed BCD to ASCII:
• you must first convert it to unpacked BCD.
• Then the unpacked BCD is tagged with 011 0000
(30H).
Packed BCD = 1001 0010
Un packed BCD = 0000 1001 , 0000 0010
ACSII = 0011 1001 , 0011 0010
Unpacking Packed BCD

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Arithmetic and Logic

The AVR microcontroller

• The concept of signed numbers and 2’s complement

16-bit addition with ADC instruction

W stands for Word which means 16 bits

L1: SUB NUM,DEN

DONE: ADD NUM,DEN

• AND is used to clear an specific bit/s of a byte

IF YOU AND ‘A’ WITH 1, WHAT DO YOU GET? A

AND OPERATION IS USED TO CLEAR BIT(S) IN A REGISTER

ANDI R17, 0B11101111 ; THIS WILL CLEAR BIT 4 ONLY IN R17

IF YOU AND ‘A’ WITH 1, WHAT DO YOU GET? A

AND OPERATION IS USED TO CLEAR BIT(S) IN A REGISTER BY

EX. WRITE A CODE TO CLEAR BITS 0, 2, 5, 7 IN R17

ANDI R17, 0B01011010 ; THIS WILL CLEAR BIT 0, 2, 5, 7

IF YOU OR ‘A’ WITH 1, WHAT DO YOU GET? 1

OR OPERATION IS USED TO SET BIT(S) IN A REGISTER BY ORING WITH 1

EX. WRITE A CODE TO SET BITS 1, 3, 6, 7 IN R18

ORI R18, 0B11001010 ;

SBI AND CBI – THESE APPLY ONLY TO IO REGISTERS

IF YOU XOR ‘A’ WITH 1, WHAT DO YOU GET? A’

XOR OPERATION IS USED TO TOGGLE BIT(S) IN A REGISTER

EX. WRITE A CODE TO TOGGLE BITS 0, 2, 5, 7 IN R17

ANDI R17, 0B10100101 ;

• AND is used to clear an specific bit/s of a byte

IF YOU XOR A REGISTER WITH $FF, WHAT DO YOU GET?

IF YOU XOR A REGISTER WITH ITSELF, WHAT DO YOU GET?

• BRVC is used to branch when oVerflow is clear to zero

See what happens to 0010 0110 after running 3 ROR instructions:

CLC ;make C = 0 (carry is 0 )

SEC ;make C = 1 (carry is 0)

For odd parity scheme:

Count the number of 1’s

1.Load the data value

Algorithm for checking parity:

Data is stored at $200 in RAM

2. WRITE A PROGRAM FOR THE RECEIVER MODULE TO CHECK. IF

SBI DDRB,1 SBI DDRB,1

SBI PORTB,1 SBI PORTB,1

BACK: ROR R17 BACK: ROL R17

SBI PORTB,1 SBI PORTB,1

ROR R17 ROL R17

SBI PORTB,1 SBI PORTB,1

• PORT B PIN 1 (PB1) – THIS IS THE OUTPUT PIN

• 1. 00100000 1 – SET PB1 (SBI PORTB,1)

CBI DDRC,7 SEC

In LSL, as bits are shifted from right to left,

this instruction multiplies content of the register by 2 assuming that after

LSL R20 LSR R20

0001 0000 0100 0000

LSL R20 LSR R20

0010 0000 0010 0000

0100 00000 0001 0000

1000 0000 0000 1000

0000 0000 0000 0100

WRITE A PROGRAM TO DIVIDE THE CONTENTS OF R22 BY 10 WITHOUT

In LSR, as bits are shifted from left to

LDI R20,0x26 ;R20 = 0010 0110 (38)

ASR means arithmetic shift right. ASR

LSR R20; R20 = 0101 1100; +92

ASR R20, R20 = 1101 1100 ; -00100100 = -36

ASCII and BCD Codes for Digits 0–9

DIGITS 0 TO 9: $30 to $39

0010 LDI R18,59