MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARMENT OF COMPUTER SYSTEMS

ENGINEERING
COMPUTER ORGANIZATION AND ARCHITECTURE
CSE-111

Lecture No. 07: ARCHITECTURE SPACE

Engr. Sarish Abid

Lecturer

Date: May 01, 2020

 Outline
Features of MIPS ISA

Other architectural variations

RICS and CISC

Examples

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What constitutes ISA?
Main Features:

Set of basic primitive operations

Storage structure- registers/memory

How addresses are specified

How instructions are encoded

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 MIPS ISA features - operations
Arithmetic

Logical

Relational

Branch /jump

Data movement

Procedure linkage

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 MIPS ISA features - storage

Memory
Register 0
0 4
1

31

  -4

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 MIPS ISA features - addressing

Addressing modes
Purpose
Immediate
Operand source
Register
Result destinations Base / index
Jump targets
PC relative
(pseudo) Direct
Register indirect

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 MIPS addressing modes-1

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 MIPS addressing modes-2

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 MIPS addressing modes-3

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MIPS ISA features - encoding

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 MIPS ISA features - summary
All instructions of same size

Only 3 formats

Fair number of GP registers

Simple operations – either arith/logic or memory access or

control transfer

Limited addressing modes

Separate fields for src1, src2 and dest

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 Alternative Architecture
Provide more powerful operations
E.g. “J++ and branch to L if J>N, where

J is in memory” or “copy a block of data in memory”

Goal is reduced number of instructions executed

Danger is a slower cycle time and/or a heigher CPI

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 Location of operands – R/M

R-R both operands in registers

R-M one operand in register and one in memory

M-M both operands in memory

R+M combines R-R, R-M, and M-M

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 How many operands fields?

3 address machine r1=r2+r3

2 address machine r1=r1+r2

1 address machine Acc=Acc+x Acc is implicit

0 address machine add values on top of stack

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 Register organizations

Register-less machine

Accumulator based machine

A few special purpose registers

Several general purpose registers

Large number of registers / register window

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 Additional addressing modes

Direct

Indirect

Base vs. index

Auto increment and auto decrement

Pre (post) increment/decrement

stack

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 RISC vs. CISC

Reduced (vs. complex) instruction set computer

Uniformity of instructions

Simple set of operations and addressing modes

Register based architecture with 3 address instruction

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 RISC examples

Virtually all new instruction set since 1982 have been RISC

SUN’s SPARK

HP’s PA-RISC

Motorola’s PowerPC

DEC’s ALPHA

CDC 6600 (1960’s)

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 CISC examples
VAX: minimize code size, make assembly language easy

Instructions from 1 to 54 byte long!

Motorola 680×0

Intel 80×86

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 Summary
Instruction complexity is only one variable

 Lower instruction count vs. higher CPI / lower clock rate

Design principle

 Simplicity favours regularity

 Smaller is faster

 Good design demands compromise

 Make the common case fast

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THANKS