Chapter 11

Reduced Instruction Set

Computing

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 Chapter Outline
• RISC Rationale
• Instruction Sets
• Instruction Pipelines
• Register Windows
• Instruction Pipeline Conflicts
• RISC vs. CISC
• Itanium Microprocessor

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 Speeding Up Typical Code

• 100% of instructions @ 20 ns

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 Speeding Up Typical Code

• 100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of
instructions at 3 * 18 ns

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 Speeding Up Typical Code

• 100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of
instructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)

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 Speeding Up Typical Code

• 100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of
instructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)
• 20c vs. 17.64c + 1.08c

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 Speeding Up Typical Code

• 100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of
instructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)
• 20c vs. 17.64c + 1.08c
• 20  18.72

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 RISC Characteristics

• Fixed-length instructions

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 RISC Characteristics

• Fixed-length instructions
• Limited loading and storing instructions

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 RISC Characteristics

• Fixed-length instructions
• Limited loading and storing instructions
• Fewer addressing modes

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 RISC Characteristics

• Fixed-length instructions
• Limited loading and storing instructions
• Fewer addressing modes
• Instruction pipeline

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 RISC Characteristics

• Fixed-length instructions
• Limited loading and storing instructions
• Fewer addressing modes
• Instruction pipeline
• Large number of registers

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 RISC Characteristics

• Hardwired control unit

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 RISC Characteristics

• Hardwired control unit

• Delayed loads and branches

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 RISC Characteristics

• Hardwired control unit

• Delayed loads and branches
• Speculative execution of instructions

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 RISC Characteristics

• Hardwired control unit

• Delayed loads and branches
• Speculative execution of instructions
• Optimizing compilers

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 RISC Characteristics

• Hardwired control unit

• Delayed loads and branches
• Speculative execution of instructions
• Optimizing compilers
• Separate instruction and data streams

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 RISC Instruction Sets

• Fewer instructions

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 RISC Instruction Sets

• Fewer instructions
• Executed in one clock cycle

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 RISC Instruction Sets

• Fewer instructions
• Executed in one clock cycle
• Orthogonal, but not too orthogonal
– A OR B = NOT((NOT A) AND (NOT B))
– A XOR B = (A AND (NOT B)) OR ((NOT A)
AND B)

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MIPS 4000 Instruction Types

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SPARC Instruction Formats

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Instruction Pipelines

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Instruction Pipelines

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Instruction Pipelines

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Instruction Pipelines

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Instruction Pipelines

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Instruction Pipelines

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 Instruction Pipeline
Advantages
• Reduced hardware
• Reduced clock period
• Reduced complexity of memory
interface

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 Pipeline Clock Rate
• Limited by slowest stage
• Speedup:

• Example:

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 Register Windowing
• Global Registers
• Windowed Registers
• Window Data Register
• Window Pointer Register

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Register Windowing

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Register Windowing

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Register Windowing

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Register Windowing

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 Register Renaming

• Arbitrary registers instead of fixed

windows
• More flexible, but harder to control

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 Instruction Pipeline Conflicts

• Data conflicts
• Branch conflicts

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Data Conflicts

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Data Conflicts

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No-op Insertion

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No-op Insertion

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Instruction Reordering

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Instruction Reordering

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 Instruction Reordering

• Not always possible

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Stall Insertion

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Stall Insertion

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Data Forwarding

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Data Forwarding

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Data Forwarding

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Branch Conflicts

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Branch Conflicts

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No-op Insertion

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No-op Insertion

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Instruction Reordering

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Instruction Reordering

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Conditional Branches

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No-op Insertion

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 Instruction Reordering

• Ignoring the data conflict:

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 Instruction Reordering

• Ignoring the data conflict:

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 Instruction Reordering

• Ignoring the data conflict:

• Not always possible to reorder

instructions - sometimes must resort to
no-op insertion
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 Annulling

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 Annulling

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Branch Prediction

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 RISC Advantages

• Simpler control units

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 RISC Advantages

• Simpler control units

• Can run at higher clock frequencies

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 RISC Advantages

• Simpler control units

• Can run at higher clock frequencies
• More chip space for registers

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 RISC Advantages

• Simpler control units

• Can run at higher clock frequencies
• More chip space for registers
• Easier to incorporate parallelism

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 RISC Advantages

• Simpler control units

• Can run at higher clock frequencies
• More chip space for registers
• Easier to incorporate parallelism
• Simpler compilers

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 CISC Advantages
• Complexity doesn’t always increase
cost
• Can incorporate previous designs
• Backward compatibility

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Itanium Microprocessor

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 Itanium Microprocessor
• IA-64 ISA
• Explicitly Parallel Instruction Computing
• Predication
• Speculative Execution

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Predication

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Predication

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Speculative Execution

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Speculative Execution

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 Summary
• RISC Rationale
• Instruction Sets
• Instruction Pipelines
• Register Windows
• Instruction Pipeline Conflicts
• RISC vs. CISC
• Itanium Microprocessor

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