Chapter-6

Digital Arithmetic:
Operations and Circuits

Afroza Sultana
 Binary Addition
• The addition of two binary number is performed in exactly
the same manner as the addition of decimal numbers.
• Least-significant-digit first.
• “Carry” of 1 into the next position may be needed.
• 4 different cases for binary addition
0+0=0
1+0=1
1 + 1 = 10 = 0 + carry of 1 into next position
1 + 1 + 1 = 11 = 1 + carry of 1 into next position
• The operations of subtraction, multiplication, and division
actually use only addition as their basic operation
 Examples

011 (3) 1001(9) 11.011(3.3 75)

 110(6)  1111(15)  10.110(2.7 50)
1001(9 ) 11000 ( 24) 110 . 001(6 .125 )
 Review Question
• Add the following pairs of binary numbers.
– 10110 + 00111
ans.) 11101

– 011.101 + 010.010
ans.) 101.111

– 10001111 + 00000001
ans.) 10010000
 Representing signed numbers
Sign-magnitude system:

Calculator and Computer do not normally use it, because

circuit implementation is more complex than other system. The
most commonly used system for representing signed binary
numbers is the 2’s compliment system.
 1’s Complement System
 Change each 0 to 1, and each 1 to 0.
 Example
(45) 1 0 1 1 0 1 original binary number
    
(- 45) 0 1 0 0 1 0 complement each bit

1 0 1 1 0 1 ( 45)
+ 0 1 0 0 1 0 (-45)
111111

Add one to this result, get zero.

 2’s Complement System

 Take the 1’s complement of the number

 Add 1 to the least-significant-bit position

101101 binary equivalent of 45

010010 complement each bit to form 1' s complement
 1 add 1 to form 2' s complement
010011 2' s complement of original binary number
 Representing signed numbers using
2’s complement form

• If the number is positive, the magnitude is

represented in its positional-weighted
binary form, and a sign bit of 0 is placed in
front of the MSB.
• If the number is negative, the magnitude is
represented in its 2’s complement form, and
a sign bit of 1 is placed in front of the MSB.
Example
 Example
• Represent each of the following signed decimal
numbers as a signed binary number in the 2’s-
complement system. Use a total of five bits
including the sign bit.

(a) +13 (b) –9 (c) +3 (d) –2 (e) –8

Ans:

(a) 01101 (b) 10111 (c) 00011 (d)11110 (e) 11000

 Negation
• Negation is the operation of converting a positive
number to its negative equivalent or a negative number
to its positive equivalent.
• We negate a signed binary number by 2’s-
complementing it.
• Example
– Each of the following numbers is a signed binary
number in the 2’s-complement system. Determine
the decimal value in each case:
(a)01100
(b)11010
(c)10001
Ans. (a) +12 (b) -6 (c) -15
 Special case in 2’s-complement
representation
• Whenever a signed number has a 1 in the sign bit and all 0s
for the magnitude bits, its decimal equivalent is –2N, where
N is the number of bits in the magnitude.
• The complete range of values that can be represented in the
2’s-complement system having N magnitude bits is –2N to
+(2N - 1).
• The range of unsigned decimal values that can be
represented in a byte is 256 different values (0-255)
• The range of signed decimal values that can be represented
in a byte is 256 different values (-128 to +127)
 Review Questions
• Represent each of the following values as an
eight-bit signed number in the 2’s-complement
system
(a) +13= 00001101 (b) –7 = 11111001
(c) –128 = 10000000

• Each of the following is a signed binary number

in the 2’s-complement system. Determine the
decimal equivalent for each.
(a) 100011= -29 (b) 1000000 = - 64
(c) 01111110 = +126
 Review Questions

• What range of signed decimal values can be

represented in 12 bits (including the sign bit)?
Ans: -2048 to +2047
• How many bits are required to represent decimal
values ranging from –50 to +50?
Ans: 7
• What is the largest negative decimal value that can
be represented by a two-byte number?
Ans: -32768
 Addition in 2’s-complement system

• Case I: Two Positive Numbers.

+9 : 0 1 0 0 1 (augend)
+4 : 0 0 1 0 0 (addend)
0 1 1 0 1 (sum = +13)

Sign bits
 Addition

• Case II: Positive Number and Smaller Negative

Number
+9 : 0 1001 (augend)
-4 : 1 1100 (addend)
1 0 0101
Sign bits

This carry is disregarded;

The result is 00101 (sum =+5)
 Addition
• Case III: Positive Number and Larger Negative
Number

-9 : 1 0 1 1 1
+4 : 0 0 1 0 0
1 1 0 1 1 (sum = -5)

Negative sign bit

 Addition

• Case IV: two negative Numbers

-9 : 1 0 1 1 1
-4 : 1 1 1 0 0
110011
Sign bit
This carry is disregarded;
The result is 10011(sum =-13)
 Addition
• Case V: Equal and Opposite Numbers

-9 : 1 0 1 1 1
+9 : 0 1 0 0 1
100000
Sign bit

Disregard;
The result is 00000 (sum = +0)
 Subtraction in the 2’s-complement
System
• The procedure for subtracting one binary
number (the subtrahend) from another binary
number (the minuend)

– Negate the subtrahend. This will change the

subtrahend to its equivalent value of opposite
sign.

– Add this to the minuend. The result of this

addition will represent the difference between
the subtrahend and the minuend.
 Subtraction

• Subtract 4 from 9
• (+9) – (+4) =(+9) + (-4)= (+5)

+9 : 0 1 0 0 1 (Minuend)
- 4 : 1 1 1 0 0 (Subtrahend)
1 0 0 1 0 1 (Difference = +5)

Disregard;
The result is 00101 (Difference = +5)
 Subtraction

• Subtract 8 from -9
• (-9) – (+8) =(-9) + (-8)= (-17)

-9 : 1 0 1 1 1 (Minuend)
- 8 : 1 1 0 0 0 (Subtrahend)
1 0 1 1 1 1 (Difference = -17)
Magnitude

Overflow Sign bit

The result is 101111 (Difference = -17)
 Arithmetic Overflow

• When two positive or two negative numbers are

being added, an overflow could occur if there is
a carry happening to the sign-bit position.

• Overflow can occur when the minuend and

subtrahend have different signs.
 BCD Addition

• Add using ordinary addition, the BCD code

groups for each digit.

• If the Sum equals 9 or less than 9, no

correction needed.

• Correction of 0110 is needed at the position

where sum is greater than 9.
 Examples

5 0101  BCD for 5

4  0100  BCD for 4
9 1001  BCD for 9

45 0100 0101  BCD for 45

 33  0011 0011  BCD for 33
78 0111 1000  BCD for 78
 Examples

+275 = 0 0 1 0 0 1 1 1 0 1 0 1
+641 = 0 1 1 0 0 1 0 0 0 0 0 1
+916 = 1 0 0 0 1 0 1 1 0 1 1 0
0110
1001 0001 0110

Invalid BCD in 2nd digit, needs correction in

the 2nd position.

The result is 1001 0001 0110 = BCD of 961

 Hexadecimal Arithmetic
• Hex Addition
– Add the two hex digits in decimal, mentally
inserting the decimal equivalent for those digits
larger than 9.
– If the sum is 15 or less, it can be directly
expressed as a hex digit.
– If the sum is greater than or equal to 16, subtract
16 and carry a 1 to the next digit position.
 Examples
• Add the hex numbers 58 and 24
58
24
7C
Ans:Sum=7C

• Add the hex numbers 3AF and 23C

3AF
23C
5EB Ans: Sum = 5EB
 Hex Subtraction
• A quicker procedure: subtract each hex digit
from F; then add 1.

F F F
-7
8
-3
C
-A
5
}  Subtract each digit from F

+1  Add 1
8 C 6  Hex equivalent of 2’s
complement
 Example

• Subtract 3A516 from 59216.

F F F
592 -3 -A -5
+C 5 B C 5 A
11 E D +1
C 5 B
Disregard carry
ALU
 Design of Full Adder
Logic circuit with 3 inputs and 2 outputs. The inputs are a bit
from the augends, a bit from the addend and a bit from a carry
CIN from a previous stage.

Truth table for a full-adder circuit

K Mappings for the full-adder outputs
 Full-adder Outputs

S  A ( B C IN  BCIN )  A( B CIN  BC IN )  A ( B  CIN )  A( B  CIN )

Let , X  B  C IN
S  A. X  A. X  A  X  A  B  C IN

COut  BC IN ( A  A)  AC IN ( B  B)  AB (C IN  C IN )  BC IN  AC IN  AB
Complete circuitry for a FA
Parallel Binary Adder
 Parallel Adder
• All the bits of the augend and the addend are
fed into the adder ckt simultaneously.
• Parallel addition is extremely fast.
Complete Parallel Adder With Registers
 IC Parallel Adder

Fig a) 4-bit Parallel Adder

b) 8-bit Parallel Adder cascading two 4-bit PA
 2’s Complement System

• The operations of addition and subtraction of

signed numbers can be performed using only
the addition operation if we use the 2’s
complement form to represent negative
numbers.
Addition
Subtraction
Combined Addition and Subtraction
 Combined Addition and Subtraction

• The adder / subtractor ckt is controlled by two

control signals ADD and SUB.
• When ADD= 1 and SUB=0 the ckt performs
addition.
• When ADD=0 and SUB =1, the ckt performs a 2’s
complement operation.
• The result of addition or subtraction appears at the
outputs ∑0 to ∑3