Ar101 Week10-16

Week 10
Arithmetic Unit (Part 3)
AR101 - BSIT
Computer Architecture and Organization
At the end of the session, the students should be
able to:
• Apply fast Multiplication Technique.
• Differentiate the hardware circuitry of Integer Division.
• Differentiate single-precision and double-precision of
floating-point numbers.
• Apply Arithmetic Operations in floating point numbers.
2
CC101 - INTRODUCTION TO COMPUTING
Week 10 - The Arithmetic Unit (Part 3)
Multiplication Algorithm
• A multiplication algorithm is an algorithm (or method)
to multiply two numbers. Depending on the size of the numbers,
different algorithms are used. Efficient multiplication algorithms have
existed since the advent of the decimal system.
• Computers initially used a very similar shift and add algorithm in

base 2, but modern processors have optimized circuitry for fast
multiplications using more efficient algorithms, at the price of a more
complex hardware realization.
3
AR101 - Computer Architecture and Organization
Some chips implement long multiplication, in hardware or in microcode, for various
integer and floating-point word sizes. In arbitrary-precision arithmetic, it is
common to use long multiplication with the base set to 2w, where w is the number of
bits in a word, for multiplying relatively small numbers.
To multiply two numbers with n digits using this method, one needs
about n2 operations. More formally: using a natural size metric of number of digits,
the time complexity of multiplying two n-digit numbers using long multiplication
is Θ(n2).
4
When implemented in software, long multiplication algorithms must deal with
overflow during additions, which can be expensive. A typical solution is to
represent the number in a small base, b, such that, for example, 8b is a
representable machine integer.
Several additions can then be performed before an overflow occurs. When the
number becomes too large, we add part of it to the result, or we carry and map the
remaining part back to a number that is less than b. This process is
called normalization
5
Computers used a "shift and add" algorithm to multiply small integers. Both base
2 long multiplication and base 2 peasant multiplication reduce to this same
algorithm.
In base 2, multiplying by the single digit of the multiplier reduces to a simple series
of logical AND operations. Each partial product is added to a running sum as soon
as each partial product is computed.
Most currently available microprocessors implement this or other similar

algorithms (such as Booth encoding) for various integer and floating-point sizes
in hardware multipliers or in microcode.
6
Fast Multiplication
• A technique called bit-pair recording halves the maximum number of

summands. It is derived directly from the Booth algorithm and twice as fast as
the worst-case Booth algorithm situation.
7
Bit-Pair Recording
8
Bit-Pair Recording
9
Bit-Pair Recording Examples

• Derive the bit-pair recorder of the following
A. 0 1 1 0 1
B. 1 0 1 1 1
C. 0 1 1 1 0
10
Bit-Pair Recording: Multiplication Examples

• Perform the following operation using bit-pair recording:
11
Integer Division
• Longhand division examples
12
Restoring Division
• The logic circuit arrangement
that implements restoring-
division technique is shown
below:
13
Restoring Division
Example
14
Non-Restoring Division
• If A is positive, we shift left and subtract M; that is, we perform 2A –
M.
• If A is negative, we restore it by performing A + M. and then we shift

it left and subtract M. This is equivalent to performing 2A + M.
• The q0 bit is appropriately set to 0 or 1 after the correct operation has

been performed.
15
Non-Restoring
Division Example
16
Floating-Point Numbers and Operation

• In the 2’s-complement system, signed value F, represented by the n-bit binary
fraction:
B = b0+. B-1 b-2… b-(n-1)
Is given by:
F(B) = - b0 x 20 + b-1 x 2-1 + b-2 x 2-2 + … + b-(n-1) x 2-(n-1)
Where the range of F is:
-1 ≤ F ≤ 1 – 2-(n-1)
• Consider the range of values possible representable in a 32-bit, signed, fixed-
point format. Interpreted as integers, the value range is approximately 0 to ± 2.15
x 109. If interpreted as fractions, the range is approximately ± 4.55 x 10-10 to ±1.
17
Floating-Point Numbers and Operation

• In the decimal scientific notation numbers may be written as 6.0246 x 1023, 6.6254 x
10-27, -1.0341 x 102, -7.3000 x 10-14 and so on.
• By convention, when the decimal point is placed to the right of the first (nonzero)
significant digit, the number is said to be normalized.
• A floating-point representation is one in which a number is represented by its sign, a

string of significant digits, commonly called mantissa, and an exponent to implied
base for the scale factor.
18
Floating-Point Number: Single-Precision

• The standard for representing floating-point numbers in 32 bits has been
developed and specified in detail by the IEEE.
19
Examples
20
Floating-Point Number: Double-Precision

• To provide more precision and range floating-point numbers, the IEEE
standard also specifies a double-precision format for floating-point
number representation:
21
Examples
• Example # 1:
Represent 5.7510 using single-precision
• Example # 2:
Convert 5010 to IEEE floating-point standard using double-

precision format
22
End of Lesson…
References:
[1] Multiplication algorithm – https://en.wikipedia.org/wiki/Multiplication_algorithm
[2] Williams, Stallings (2010), Computer Organization and Architecture: Designing for Performance (8 th Edition, Prentice Hall, New Jersey).
[3] Stalling, William, Computer Organization and Architecture: Principles of Structure and Function (4th Edition)
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WEEK 11
ARITHMETIC INSTRUCTIONS
AR101 - COMPUTER ARCHITECTURE AND ORGANIZATION

 Differentiate all Arithmetic Instructions.
 Apply the different Arithmetic Instructions.
2
AR101 - Architecture and Organization
WEEK 11 - ARITHMETIC INSTRUCTIONS
The ADD Instruction

• The ADD instruction adds the Destination Source Example
source operand to the Register Register ADD BX, CX
destination and then places the Register MM ADD DX, [BP + SI]
MM Register ADD [BX + DI], CX
result in the destination
Register Immediate ADD BX, 0015H
operand.
MM Immediate ADD byte ptr BETA, 12H
• Format: ADD D, S
• Action: D [D] + [S]
3
Example – ADD Instruction

• Determine the contents of all the affected general-purpose registers
and memory addresses after executing the following program. Each
instruction is dependent of one another. Whenever necessary, use the
memory map (handout) for additional data. Assume the following
register contents and assume that all flags are initially 0:
AX = 0015H BP = 0002H CS = 3000H
BX = 0019H SP = 0035H DS = 2000H
CX = 0012H DI = 0017H SS = 2000H
DX = 001BH SI = 001EH ES = 4000H
ADD AX,BX
ADD [SI], DI
4
Exercise # 1
• Unless otherwise stated, determine the contents of all the affected
general-purpose registers and memory addresses after executing the
following program. Each instruction is dependent of one another.
Whenever necessary, use the memory map (handout) for additional
data. Assume the following register contents and assume that all flags
are initially 0:
AX = 0015H BP = 0002H CS = 3000H
BX = 0019H SP = 0035H DS = 2000H
CX = 0012H DI = 0017H SS = 2000H
DX = 001BH SI = 001EH ES = 4000H
ADD AX, [CX]

ADD [DX], SI
5
The ADC Instruction

• The ADC (Add with Carry) instruction adds the source operand
and the carry flag to the destination operand and places the
result in the destination operand.
• Format: ADC D, S
• Action: [D] [D] + [S] + [CF]
• One of the uses of the ADC instruction is in the

implementation of 32-bit addition (adding two 32-bit
numbers).
6
Example – ADC Instruction

Determine the contents of all the AX = 0015H BP = 0002H CS = 3000H
affected general-purpose registers and BX = 0019H SP = 0035H DS = 2000H
memory addresses after executing the
following program. Each instruction is CX = 0012H DI = 0017H SS = 2000H
dependent of one another. Whenever DX = 001BH SI = 001EH ES = 4000H
necessary, use the memory map
(handout) for additional data. Assume
the following register contents and
assume that all flags are initially 0:
MOV AX,FAFAH
MOV BX, [SP]
ADD AX, BX
ADC SI, DI
7
Exercise # 2
Unless otherwise stated, determine the AX = 0015H BP = 0002H CS = 3000H
contents of all the affected general- BX = 0019H SP = 0035H DS = 2000H
purpose registers and memory
addresses after executing the following CX = 0012H DI = 0017H SS = 2000H
program. Each instruction is dependent DX = 001BH SI = 001EH ES = 4000H
of one another. Whenever necessary,
use the memory map (handout) for
additional data. Assume the following
register contents and assume that all
flags are initially 0:
MOV CX, EBADH

MOV BX, [SI]
ADD CX, BX
ADC AX, DX
8
The INC Instruction

The INC (Increment) instruction Destination Example
adds 1 to the destination operand. Register INC AX

MM INC byte ptr [BX]
Format: INC D
Action: D [D] + 1
9
Example – INC Instruction

INC AX
INC BX
INC CX
INC DX
10
The DAA Instruction

• The DAA (Decimal Adjust for Addition) instruction adjusts the result of a
previous addition of two valid packed decimal operands.
Format: DAA
Example:
MOV AL, 15H
MOV BL, 15H
ADD AL, BL
DAA
11
The DAA Instruction

• Determine the contents of all the AX = 0015H BP = 0002H CS = 3000H
affected general-purpose registers BX = 0019H SP = 0035H DS = 2000H
and memory addresses after
executing the following program. CX = 0012H DI = 0017H SS = 2000H
Each instruction is dependent of DX = 001BH SI = 001EH ES = 4000H
one another. Whenever necessary,
use the memory map (handout) for
additional data. Assume that all
flags are initially 0:
MOV AL, F5H

MOV BL, F5H
ADD AL, BL
DAA
12
The AAA Instruction

The AAA (ASCII Adjust for Addition) instruction adjusts the result of a
previous addition of two valid unpacked decimal operands.
Format: AAA
Example:
MOV AL, 35H ASCII value of 5
MOV BL, 34H ASCII value of 4
ADD AL, BL
AAA
13
Example – AAA Instruction

affected general purpose registers and
BX = 0019H SP = 0035H DS = 2000H
that all flags are initially 0:
MOV AL, 74H

MOV BL, 75H
ADD AL, BL
AAA
14
The SUB Instruction

The SUB instruction subtracts the Destination Source Example
source operand to the destination Register Register SUB BX, CX
and then places the result in the Register MM SUB DX, [BP + SI]
MM Register SUB [BX + DI], CX
destination operand.
Register Immediate SUB BX, 0015H
MM Immediate SUB byte ptr BETA, 12H
Format: SUB D, S
Action: D [D] - [S]
15
Example – SUB Instruction

memory addresses after executing the CX = 0012H DI = 0017H SS = 2000H
following program. Each instruction is
DX = 001BH SI = 001EH ES = 4000H
dependent of one another. Whenever
SUB AX, BX
SUB [SI], DI
16
The SBB Instruction

The ADC (Subtract with Borrow) instruction subtracts the source
operand and the carry flag from the destination operand and
places the result in the destination operand.
Format: SBB D, S
Action: [D] [D] - [S] - [CF]
Just like in addition, subtracting a 32-bit number from another 32-

bit number can be done with the combination of the Sub and SBB
instructions.
17
Example – SBB Instruction

MOV AX,7AFAH
MOV BX, LIST
SUB AX, BX
SBB SI, DI
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The DEC Instruction

The DEC (Decrement) instruction Destination Example
SUBTRACTS 1 from the destination Register DEC AX
operand. MM DEC byte ptr [BX]
Format: DEC D
Action: D [D] - 1
19
Example – DEC Instruction

DEC AX
DEC BX
DEC CX
DEC DX
20
The DAS Instruction

The DAS (Decimal Adjust for Subtraction) instruction adjusts the
result of a previous subtraction of two valid packed decimal
operands.
Format: DAS
Example:
MOV AL, 34H
MOV BL, 19H
SUB AL, BL
DAS
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Example – DAS Instruction

MOV AL, 3FH

MOV BL, 15H
SUB AL, BL
DAS
22
The AAS Instruction

The AAA (ASCII Adjust for Subtraction) instruction adjusts the result of
a previous Subtraction of two valid unpacked decimal operands.
Format: AAS
Example:
MOV AL, 39H ASCII value of 9
MOV BL, 34H ASCII value of 4
SUB AL, BL
AAS
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Example – AAS Instruction

MOV AL, 8EH

MOV BL, 62H
SUB AL, BL
AAS
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WEEK 12
LOGIC INSTRUCTIONS

 Identify the different Logic Instructions
 Apply the different Logic Instructions.
2
WEEK 12 - LOGIC INSTRUCTIONS
NEG INSTRUCTION
• The NEG (Negate) instruction Destination Example
converts the specified operand Register NEG AX
to its 2’s complement equivalent MM NEG byte ptr [BX]
and the result returned to the

operand location. This is in
effect, reversing the sign of an
integer.
• Format: INC D
• Action: D 0 – [D]
3
Example – NEG Instruction

• Determine the value of AL and the value of all flags (assume
all flags are initially 0) following the instruction sequence:
MOV AL, 05H

NEG AL
4
The CMP Instruction

• The CMP (Compare) instruction Destination Source Example
subtracts the source operand Register Register CMP BX, CX
from the destination operand. It Register MM CMP DX, [BP + SI]

MM Register CMP BETA, CX
then discards the result, but it
Register Immediate CMP BX, 0015H
updates the value of all status
MM Immediate CMP byte ptr BETA, 12H
flags.
• Format: CMP D, S
• Action: [D] - [S]
5
Example – CMP Instruction

• Determine the contents of all the AX = 0015H BP = 0002H CS = 3000H
affected general-purpose registers BX = 0019H SP = 0035H DS = 2000H
and memory addresses after
executing the following program. CX = 0012H DI = 0017H SS = 2000H
Each instruction is dependent of one DX = 001BH SI = 001EH ES = 4000H
another. Whenever necessary, use
the memory map (handout) for
additional data. Assume the
following register contents and
CMP AX,BX
CMP [SI], DI
6
Program Tracing Example

Trace the following program. Assume the following: All flags and registers (unless specified otherwise)
are initially zero, DS = 2000H, SS = 2001H, the label ALPHA = 001CH. Use the memory map (if necessary).
MOV AX, ALPHA Cont...

MOV SP, AX SBB AX, CX
POP BX ADC AX, 0029H
ADD BX, AX DAA
SUB BX, 9F79H NEG AX
XCHG BX, BP LEA SI, ALPHA
MOV CX, [BP] MOV DX, [SI]
7
The AND Instruction

The AND (Logical AND) instruction Destination Source Example
logically ANDs the source operand Register Register AND BX, CX
and the destination operand and Register MM AND DX, [BP + SI]
MM Register AND BETA, CX
stores the result in the destination
Register Immediate AND BX, 0015H
operand.
MM Immediate AND byte ptr BETA, 12H
Format: AND D, S
Action: D [D] · [S]
8
Example – AND Instruction

Determine the value of affected registers and the value of all
flags (assume all flags are initially 0) following the instruction
sequence:
MOV AL, 05H

MOV BL, FEH
AND AL, BL
9
The OR Instruction
The AND (Logical OR) instruction Destination Source Example
logically ORs the source operand Register Register OR BX, CX
and the destination operand and Register MM OR DX, [BP + SI]

MM Register OR BETA, CX
Register Immediate OR BX, 0015H
operand.
MM Immediate OR byte ptr BETA, 12H
Format: OR D, S
Action: D [D] + [S]
10
Example – OR Instruction
Determine the value of affected registers and the value of all flags
(assume all flags are initially 0) following the instruction sequence:
MOV CL, 05H

MOV DL, 80H
OR CL, DL
11
The XOR Instruction

The AND (Logical XOR) instruction Destination Source Example
logically XORs the source operand Register Register XOR BX, CX
and the destination operand and Register MM XOR DX, [BP + SI]
MM Register XOR BETA, CX
Register Immediate XOR BX, 0015H
operand.
MM Immediate XOR byte ptr BETA, 12H
Format: OR D, S
Action: D [D] [S]
12
Example – XOR Instruction

Determine the value of affected registers and the value of all flags (assume
all flags are initially 0) following the instruction sequence:
MOV AL, 15H

MOV BL, ABH
XOR AL, BL
13
The NOT Instruction

The NOT (Logical NOT) instruction Destination Example
performs a 1’s complement on the Register NOT AX
operand. MM NOT byte ptr {BX]
Format: NOT D
Action: D [D]’
14
Example – NOT Instruction

Perform the following operation. Each instruction is dependent on one
another. Assume that all flags are initially 0:
MOV BX, D32BH

MOV CX, 1056H
NOT BX
NOT CX
15
The TEST Instruction

The TEST instruction logically ANDS the source and the destination
operands. The result is discarded but the values of the status flags are
updated.
Format: TEST D, S
Action: [D] · [S]
16
Example – TEST Instruction

Perform the following operation. Each instruction is dependent on one
another. Assume that all flags are initially 0:
MOV SL, 2376H

MOV DI, 1941H
TEST SI, DI
17
Logic Instruction Program Tracing Example

• Trace the following program. MOV AX, ALPHA Cont…
MOV SP, AX MOV CX, [SP]
Assume the following: All flags NEG BX TEST BX, CX
and registers (unless specified AND BX, [AX] NOT AX
OR BX, 0020H XOR AL, CL
otherwise) are initially zero, DS = CMP BX, SP
2000H, SS = 2001H, the label
ALPHA = 001CH. Use the
memory map (if necessary).
18
Logic Instruction Program Tracing Example

• Trace the following program. MOV AL, 23H Cont…
MOV CH, 6BH XOR CH, AAH
Assume the following: All flags XOR AL, 0CH TEST CH, AL
and registers (unless specified ADD AL, 77H DEC AX
NEG BX OR CH, AL
otherwise) are initially zero, DS = AND CH, 33H SUB AX, CX
2000H, SS = 2001H, the label
ALPHA = 001CH. Use the
memory map (if necessary).
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20
WEEK 13
SHIFT AND ROTATE INSTRUCTIONS
AR101 - ARCHITECTURE AND COMPUTER ORGANIZATION

 Learn to identify the different SHIFT
Instructions.
 Learn to apply the different SHIFT Instructions.
 Learn to identify the different ROTATE
Instructions.
 Know how to apply the different ROTATE
Instructions.
2
WEEK 13 - SHIFT AND ROTATE INSTRUCTIONS
The Shift Instruction

• Shift Instructions can be classified as either logical shift or arithmetic shift.
• Shift Instructions can also be classified by the direction of the shift (i.e., shift
to the left or shift to the right).
• Thus, there are four types of shift instructions: shift logical left (SHL), shift
logical right (SHR), shift arithmetic left (SAL), shift arithmetic right (SAR).
3
The SHL/SAL Instruction

• SHL (Shift Logical Left) and SAL. (Shift Arithmetic Left) are two different mnemonics
but perform the same operation. Both instructions shift to the left of the destination
operand by the number of bits specified in the count operand.
• Format: SAL D, Count or SHL D, Count

• Action:
0
CF Operand
4
Example – SHL/SAL Instruction

Execute the following instructions and determine the status of the flags.
Example # 1:
MOV AL, 04H
SHL AL, 1
Example # 2:
MOV AL, 02H
MOV AL, 03H
SHL AL, CL
5
Exercise – SHL/SAL Instruction

MOV AL, AAH

MOV CL, 06H
SHL AL, CL
6
The SHR Instruction

The SHR (Shift Logical Right) instruction shifts to the right of the destination
operand by the number of bits specified in the count operand. As the bits are
being shifted, zeros are shifted in on the left.
Format: SHL D, Count

Action:
0
Operand CF
7
Example – SHR Instruction

Example # 1:
MOV AL, 05H
SHR AL, 1
Example # 2:
MOV AL, 20H
MOV AL, 03H
SHR AL, CL
8
Exercise – SHR Instruction

MOV AL, 6BH

MOV CL, 06H
SHL AL, CL
9
The SAR Instruction

The SAR (Shift Arithmetic Right) instruction shifts to the right of the destination
operand by the number of bits specified in the count operand. As the bits are
being shifted, the most significant bit is shifted to the left, preserving the sign
bit.
Format: SAR D, Count

Action:
10
Example –SAR Instruction

Example # 1:
MOV AL, FCH
SAR AL, 1
Example # 2:
MOV AL, 19H
MOV AL, 03H
SAR AL, CL
11
Exercise – SAR Instruction

MOV AL, 8DH

MOV CL, 06H
SHL AL, CL
12
Shift Instruction Exercise

Execute the following instructions. Assume that each instruction is dependent of
one another. Determine the status of the flags.
MOV AL, 9EH

MOV CL, 03H
SHL AL, CL
SAR AL, CL
SHR AL, CL
13
Quiz - Shift Instruction

MOV AL, 7EH

MOV CL, 02H
SHL AL, CL
SAR AL, CL
SHR AL, CL
14
Perform the indicated operation. Each instruction is

dependent of one another. Whenever necessary, use
Program Tracing the memory map (handout) for additional data.
Assume the following register contents and assume
Exercise that all flags are initially 0:
MOV DX, 007EH
XOR SI, DI
AX = 0015H BP = 0002H CS = 3000H XCHG DX, SI
BX = 0019H SP = 0035H DS = 2000H DEC SI,
CX = 0012H DI = 0017H SS = 2000H ADD[SI], AX
DX = 001BH SI = 001EH ES = 4000H DEC CX
SHR word ptr [SI]. CL
MOV BX, [SI]
MOV CX, 0009H
SAR BX, CL
15
Program Tracing Exercise

Unless otherwise stated, determine the contents of all affected general-purpose registers and
the flags after executing the following programs (assume that all registers and flags are
initially 0):
MOV DX, DB53H
SAR DX, 01H
SAR DX, 01H
SAL DH, 01H
SAL DL, 01H
SHR DX, 01H
SHR DX, 01H
SHL DH, 01H
SHL DL, 01H
What will be DX after executing? 16
The Rotate Instruction

Rotate nits out into the other end of the operand.
can be classified by the direction of the rotate (rotate to the left or rotate to the
right).
17
The Rotate Instruction

The different types of rotate instructions are:
vROL instruction
vROR instruction
vRCL instruction
vRCR instruction
18
The ROL Instruction

ROL (Rotate Left) instruction rotates to the left of the destination operand by
the number of bits specified in the count operand.
Format: ROL D, Count

Action:
19
Example # 1: Example – ROL Instruction

MOV AL, 04H
ROL AL, 1
After execution, AL = 08H. The flags will be:
CF = 0, OF = 0
Example # 2:
MOV AL, 55H
MOV AL, 03H
ROL AL, CL
CF = 0, OF = undefined
20
The ROR Instruction

ROR (Rotate Right) instruction rotates to the right of the destination operand by
the number of bits specified in the count operand.
Format: ROR D, Count

Action:
21
Example # 1: Example – ROR

MOV AL, 04H Instruction
ROR AL, 1
CF = 0, OF = 0
Example # 2:
MOV AL, 55H
MOV AL, 03H
ROR AL, CL
After execution, AL = AAH. The flags will be:
22
Exercise
one another. Assume that all flags are initially zero.
MOV AL, 5EH

MOV CL, 02H
ROR AL, CL
ROL AL, CL
23
The RCL Instruction

RCL (Rotate Left through Carry) instruction rotates to the left of the destination
operand by the number of bits specified in the count operand. The carry flag is
treated as part of the rotate.
Format: RCL D, Count

Action:
24
Example – RCL Instruction

RCL (Rotate Left through Carry) instruction rotates to the left of the destination operand by the number of
bits specified in the count operand. The carry flag is treated as part of the rotate.
Format: RCL D, Count
Action: Example # 1:
MOV AL, 04H
RCL AL, 1
Assume that CF = 1. After execution, AL = 09H. The flags will be:
CF = 0, OF = 0
Example # 2:
MOV AL, 55H
MOV AL, 03H
RCL AL, CL
Assume that CF = 0. After execution, AL = A9H. The flags will be:
25
The RCR Instruction

RCL (Rotate Right through Carry) instruction rotates to the right of the
destination operand by the number of bits specified in the count operand. The
carry flag is treated as part of the rotate.
Format: RCR D, Count

Action:
26
Example # 1:
MOV AL, 04H
Example – RCR Instruction
RCR AL, 1
Assume that CF = 1. After execution, AL = 82H. The flags will be:
CF = 0, OF = 1
Example # 2:
MOV AL, 55H
MOV AL, 03H
RCR AL, CL
Assume that CF = 0. After execution, AL = 4AH. The flags will be:
27
Quiz – Rotate Instructions

MOV AL, 7EH

MOV CL, 02H
ROR AL, CL
RCR AL, CL
RCL AL, CL
ROL AL, CL
28
Perform the indicated operation. Each instruction

Program Tracing is dependent of one another. When necessary,
use the memory map (handout) for additional
Example data. Assume that the following register contents
and assume that all flags are initially 0:
MOV DX, FFFEH
XOR SI, DI
AX = 0015H BP = 0002H CS = 3000H
XCHG DX, SI
BX = 0019H SP = 0035H DS = 2000H
CX = 0012H DI = 0017H SS = 2000H
DEC CX
DX = 001BH SI = 001EH ES = 4000H
RCR word ptr [SI], CL
MOV BX, [SI]
MOV CX, 0009H
ROL BX, CL
29
Program Tracing Example

Unless otherwise stated, determine the contents of all the affected
general-purpose registers and the flags after executing the following
programs (assume that all registers and flags are initially 0):
MOV DX, DB35H

ROR DX, 01H
RCR DX, 01H
ROL DH, 01H
ROL DL, 01H
RCL DX, 01H
RCR DX, 01H
30
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WEEK 14
THE PROCESSING UNIT (PART 1)

 Differentiate steps in Instruction Execution.
 Classify how gating circuits are used in Data
Transfers.
2
WEEK 14 - THE PROCESSING UNIT (PART 1)
Fundamental Concepts Review

• Instruction Set Processor (ISP)
- Simply known as the processor. The processing unit executes
machine instructions and coordinates with the activities of other
units.
- The processing unit to be called the central processing unit (CPU).
- The processor keeps track of the address of the memory location

containing the next instruction by using the dedicated register,
referred as the program counter (PC).
3

• In order to read or fetch an instruction or a data from the main memory:
1. The processor first sends the address of the memory location to be read.
2. The processor then issues or sends the read signal to the memory.
3. The word is then read out from the memory and is loaded to a processor
internal register.
4

• In order to store or write data into the memory:
1. The processor first sends the address of the memory location to be written.
2. The processor then sends the write signal together with the word to be
written to the memory.
5
Connection between Processor and Main Memory

Main Memory
MAR MDR CONTROL
PC R0
R1
IR … ALU
…
…
n is a general-purpose
Rn-1 register
6
Operating Steps
1. PC is set to point to the first instruction of the program.
2. The content of the PC are transferred to the MAR and a read signal is sent to
the MM.
3. The address word is read out of MM and loaded to the MDR.
4. The contents of the MDR are transferred to IR. The instruction is ready to be
decoded and executed.
5. During the Execution: the contents of the PC are incremented or updated to
point to the next instruction.
7
During the Execution:

If an operand or data needed by the instruction resides in the MM:
1. It will have to be fetched by sending it’s address to the MAR and initiating a
read cycle.
2. When an operand has been read from the Main Memory into the MDR, it
may be transferred from the MDR to the ALU.
8
During the Execution:

If a result is to be stored in the Main Memory:
1. The result is sent to the MDR

2. The address of the location where the result is to be stored is sent to the
MDR and a write cycle is to be initiated.
9
Steps in Instruction Execution

1. Fetch the contents of the memory location pointed to the PC.
IR [[PC]]
2. Increment the contents of the PC by 1.

IR [[PC] + 1]
3. Carry out the actions specified by the instruction in IR.
Note: Steps 1 and 2 are usually referred to as Fetch Phase;

Step 3 constitutes the Execution Phase
10
Data Paths in Single-Bus Organization

Internal Processor Bus
Instruction
Decoder …
IR Rn-1
1
PC Y
Address Lines
MAR MUX Select
Memory
Data Lines
Bus
MDR Add
B A ALU
Sub Control
R0 ALU Lines
XOR
Carry-In
R1
Z
11
Processor Operations
With a few exceptions, an instruction can be executed by performing one or
more of the following operations in some specified sequence:
1. Transfer a word of Data from one processor register to another or to the ALU.
2. Perform an arithmetic or logic operation and store a result in a processor
register.
3. Fetch the content of a given memory location and load them into a processor
register.
4. Store a word of data from a processor register into a given memory location.
12
Register Transfers
To enable data transfer between various blocks in a common data bus, input,
and output gating must be provided. The input and output gates for Register Ri
are controlled by the Ri(in) and Ri(Out) respectively.
Ri(in)
Ri
Ri(Out)
13
Example
Given:
R4 [R1]
describe the steps and control signals needed to execute the Instruction
Enable the output gate of register R1 by setting R1(Out) to 1. Then place the
contents of R1 on the processor bus.
Enable the input gate of register R4 by setting R4(in) to 1. This loads data from the
processor bus into Register R4.
14
Input and Output gating for the ALU

Yin
1 Y
Select MUX
A B
ALU
Zin
Z
ZOut
15
Performing an Arithmetic or Logic Operation

The ALU is a combinational circuit that has no internal storage. It performs arithmetic and logic
operations on two operands applied to A and B inputs. The result is temporarily stored in the register Z.
Example:
R3 [R1] + [R2]
1. R1(out), Yin
2. R2(Out), Select Y, Add, Z(in)
3. Z(out), R3(in)
16
Examples
Determine the control sequence of the following instructions using the single-
bus organization.
1. PC [PC] + 1
2. R1 [Y] + [R1]
3. Y [R1] + [PC] + [R2]

18
WEEK 15-16
THE PROCESSING UNIT (PART 2)

• Apply memory function complete signal in fetching a word
from a memory and storing a word into memory.
• Determine how to write the control sequence of a complete
instruction execution
• illustrate how branching is implemented in single bus
organization.
• Classify the Hardwired Control Technique.
• Determine how to design the combinational Circuit of a
given control signal
2
WEEK 15-16 - THE PROCESSING UNIT (PART 2)
FETCHING A WORD FROM MEMORY

• CPU transfers the address of the needed information word to the memory address
register (MAR). Address of the needed word is transferred to the primary memory.
• In the meantime, the CPU uses the control lines of the memory bus to mention that a
read operation is needed.
• After issuing this request, the CPU waits till it retains an answer from the memory,
informing it that the required function has been finished. It is accomplished through the
use of another control signal on the memory bus, which will be denoted as Memory
Function Completed (MFC).
• The memory sets this signal to one to mention that the contents of the particular
location in the memory have been read and are available on the data lines of the
memory bus.
• We will suppose that as soon as the MFC signal is set to one, the information on the
data lines is loaded into
3
FETCHING A WORD FROM MEMORY
4
INPUT AND OUTPUT GATING OF MAIN MEMORY

Peripheral Devices
• Input or output devices that are connected to computer are called peripheral devices.
These devices are designed to read information into or out of the memory unit upon
command from the CPU and are considered to be the part of computer system. These
devices are also called peripherals.
• For example: Keyboards, display units and printers are common peripheral devices.
• There are three types of peripherals:
• Input peripherals
• Output peripherals
• Input-Output peripherals
5
Interfaces
• Interface is a shared boundary btween two separate components of the computer
system which can be used to attach two or more components to the system for
communication purposes.
There are two types of interface:
• CPU Inteface
• I/O Interface
6
Input-Output Interface
• Peripherals connected to a computer need special communication links for
interfacing with CPU. In computer system, there are special hardware
components between the CPU and peripherals to control or manage the input-
output transfers. These components are called input-output interface
units because they provide communication links between processor bus and
peripherals. They provide a method for transferring information between internal
system and input-output devices.
7
Modes of I/O data transfer

Data transfer between the central unit and I/O devices can be handled in generally
three types of modes which are given below:
• Programmed I/O
• Interrupt Initiated I/O
• Direct Memory Access
8
Direct Memory Access
9
Memory Function Complete

• Memory function complete or MFC is just a signal that tells the cpu that the
current operation involving the memory is complete and by that definition it is
obvious that MFC signal will be generated in case of write operation also as in the
case of read operation.
10
Storing a WORD into the Memory

• That is similar process with fetching a word from memory.
• The required address is loaded into the MAR
• After that data to be written are loaded into MDR, and a write command is issued.
• If we suppose that the data word to be stored in the memory is in R2 and that the memory address is in
R1, the Write operation needed the following sequence:
• MAR - [R1]
• MDR -[R2]
• Write
• Wait for the MFC
• Move R2, (R1) requires the following sequence (signal):
• R1out, MARin
• R2out, MDRin. Write
• MDRoutE,WMFC
11
Execution of a complete instruction
12
Branching
• Branching is accomplished by replacing the current contents of the PC by the
branch address, That is, the address of the instruction to which branching is
required.
13
Branching
• Branching instructions refer to the act of switching execution to a different
instruction sequence as a result of executing a branch instruction.
The three types of branching instructions are:
• Jump (unconditional and conditional)
• Call (unconditional and conditional)
• Return (unconditional and conditional)
14
Jump Instruction
• The jump instruction transfers the program sequence to the memory address
given in the operand based on the specified flag. Jump instructions are 2 types:
• (a) Unconditional Jump Instructions: Transfers the program sequence to the
described memory address.
15
Jump Instruction
• (b) Conditional Jump Instructions: Transfers the program sequence to the
described memory address only if the condition in satisfied.
16
Call Instruction
• The call instruction transfers the program sequence to the memory address given
in the operand. Before transferring, the address of the next instruction after CALL
is pushed onto the stack. Call instructions are 2 types:
• (a) Unconditional Call Instructions: It transfers the program sequence to the
memory address given in the operand.
17
Call Instruction
• (b) Conditional Call Instructions: Only if the condition is satisfied, the instructions
executes.
18
Return Instruction
• The return instruction transfers the program sequence from the subroutine to the
calling program. Return instructions are 2 types:
• (a) Unconditional Return Instruction: The program sequence is transferred
unconditionally from the subroutine to the calling program.
19
Return Instruction
• (b) Conditional Return Instruction: The program sequence is transferred
unconditionally from the subroutine to the calling program only is the condition is
satisfied.
20
Unconditional Branching
21
Sequence of Control Signals
22

• 8282 (8 bits) latch :
The latches are buffered D FF. They are used to separate the valid address from the
multiplexed Address/data bus by using the control signal ALE, which is connected to
strobe(STB) of 8282.
• 8286 (8 bits) transceivers :
They are bidirectional buffers and also known as data amplifiers. They are used to separate
the valid data from multiplexed add/data bus.
23

• Timing diagram :
The working of min mode can be easily understood by timing diagrams.
24
Hardwired Control Unit:

• It is implemented as logical circuit (gates, flip-flops, decoders etc.) in the
hardware. This organization is very complicated if we have a large control unit.
• In this organization, if the design has to be modified or changed, requires changes
in the wiring among the various components. Thus the modification of all the
combinational circuits may be very difficult.
25
Microprogrammed Control Unit

• A microprogrammed control unit is implemented using programming approach. A
sequence of micro-operations are carried out by executing a program consistingof
micro-instructions.
• Micro-program, consisting of micro-instructions is stored in the control memory
of the control unit. Execution of a micro-instruction is responsible for generation
of a set of control signals.
26
Difference between Hardwired and

Microprogrammed Control Unit:
27
28

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Week 10

Arithmetic Unit (Part 3)

• Computers initially used a very similar shift and add algorithm in

Most currently available microprocessors implement this or other similar

• A technique called bit-pair recording halves the maximum number of

Bit-Pair Recording Examples

Bit-Pair Recording: Multiplication Examples

• If A is negative, we restore it by performing A + M. and then we shift

• The q0 bit is appropriately set to 0 or 1 after the correct operation has

Floating-Point Numbers and Operation

Floating-Point Numbers and Operation

• A floating-point representation is one in which a number is represented by its sign, a

Floating-Point Number: Single-Precision

Floating-Point Number: Double-Precision

Represent 5.7510 using single-precision

Convert 5010 to IEEE floating-point standard using double-

[1] Multiplication algorithm – https://en.wikipedia.org/wiki/Multiplication_algorithm

AR101 - COMPUTER ARCHITECTURE AND ORGANIZATION

The ADD Instruction

source operand to the Register Register ADD BX, CX

Example – ADD Instruction

ADD AX, [CX]

The ADC Instruction

• One of the uses of the ADC instruction is in the

Example – ADC Instruction

MOV CX, EBADH

The INC Instruction

adds 1 to the destination operand. Register INC AX

Example – INC Instruction

The DAA Instruction

The DAA Instruction

MOV AL, F5H

The AAA Instruction

Example – AAA Instruction

MOV AL, 74H

The SUB Instruction

source operand to the destination Register Register SUB BX, CX

Example – SUB Instruction

The SBB Instruction

Just like in addition, subtracting a 32-bit number from another 32-

Example – SBB Instruction

The DEC Instruction

SUBTRACTS 1 from the destination Register DEC AX

operand. MM DEC byte ptr [BX]

Example – DEC Instruction

The DAS Instruction

Example – DAS Instruction

MOV AL, 3FH

The AAS Instruction

Example – AAS Instruction

MOV AL, 8EH

AR101 - COMPUTER ARCHITECTURE AND ORGANIZATION

converts the specified operand Register NEG AX

to its 2’s complement equivalent MM NEG byte ptr [BX]

and the result returned to the

Example – NEG Instruction

MOV AL, 05H

The CMP Instruction

subtracts the source operand Register Register CMP BX, CX

from the destination operand. It Register MM CMP DX, [BP + SI]

Example – CMP Instruction

Program Tracing Example

MOV AX, ALPHA Cont...