1 CHAPTER 3

CENTRAL PROCESSING
UNT

ECEg3148 01/06/22
2 Lecture Outline
• Instruction Formats
 Three address instructions
 Two address instructions
 One address instructions
 Zero address instructions

01/06/22
 An instruction set
 The complete collection of instructions that are
understood by a CPU.
 Serves as an interface between software and hardware.
 Provides a mechanism by which the software tells the hardware
what should be done.
 Instruction Set Design
 One important design factor is the number of operands contained
in each instruction
 Has a significant impact on the word size and complexity of the CPU

 Joanne E. DeGroat, OSU

Instruction Set Design
 Consider how many operands we need for an ADD instruction
 If we want to add the contents of two memory locations together, then we
need to be able to handle at least two memory addresses
 Where does the result of the add go? We need a third operand to specify the
destination

 If all of these operands are memory addresses, we need a really

long instruction!
 The number of address fields in the instruction format depends
on the internal organization of CPU
 Joanne E. DeGroat, OSU
Classifying Instruction Set Architectures
 The type of internal storage in the CPU is the most basic differentiation. The
major choices are a stack, an accumulator, or a set of registers.

– Stack Computer Architecture

– AC Computer Architecture
– General Purpose Register Computer Architecture

Input Bus Input Bus

General Other
Purpose Stack
ALU
ALU
AC Registers ALU
Registers
Registers

Stack Architecture Output Bus Output Bus

AC Architecture
GPR Architecture

 Joanne E. DeGroat, OSU

Classifying ISAs
Accumulator (before 1960, e.g. 68HC11):
1-address add A acc acc + mem[A]

Stack (1960s to 1970s):

0-address add tos tos + next

Memory-Memory (1970s to 1980s):

2-address add A, B mem[A] mem[A] + mem[B]
3-address add A, B, C mem[A] mem[B] + mem[C]

Register-Memory (1970s to present, e.g. 80x86):

2-address add R1, A R1 R1 + mem[A]
load R1, A R1 mem[A]

Register-Register (Load/Store) (1960s to present, e.g. MIPS):

3-address add R1, R2, R3 R1 R2 + R3
load R1, R2 R1 mem[R2]
store R1, R2 mem[R1] R2

 Joanne E. DeGroat, OSU

 Operand Locations in Four ISA Classes
GPR

 Joanne E. DeGroat, OSU

 Code Sequence C = A + B
for Four Instruction Sets
Stack Accumulator Register Register (load-
(register-memory) store)
Push A Load A Load R1, A Load R1,A
Push B Add B Add R1, B Load R2, B
Add Store C Store C, R1 Add R3, R1, R2
Pop C Store C, R3

memory
 Joanne E. DeGroat, OSU memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
 NUMBER OF ADDRESSES
9

The number of address fields in the instruction format depends

on the internal organization of CPU
Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
POP M[X]  TOS

 Joanne E. DeGroat, OSU 01/06/22

 Three-Address Instructions:
10

Program to evaluate X = (A + B) * (C + D) :

ADD R1, A, B /* R1  M[A] + M[B] */

ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

 Joanne E. DeGroat, OSU 01/06/22

TWO-ADDRESS INSTRUCTIONS
11

Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */

 Joanne E. DeGroat, OSU

 ONE-ADDRESS INSTRUCTIONS
12

- Use an implied AC register for all data manipulation

- Program to evaluate X = (A + B) * (C + D) :

LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */

 Joanne E. DeGroat, OSU

Addressing Modes
 The different ways in which operands can be addressed are
called the addressing modes.
 Immediate, Direct, Indirect, Register, Register Indirect,
Displacement (Indexed) and Stack
 All computer architecture provide more than one address modes.
 The point is
 How the control unit can determine which address mode is
being used in a particular instruction.
 One or more bits of the instruction can be used as a mode fields.
 How to calculate the effective address.

 Joanne E. DeGroat, OSU

 Immediate Addressing
 The simplest addressing mode, in which operand is part of instruction.
 Example instruction: LOAD#1000,Ri.
 In this instruction, the operation to be performed is to load a value into a
register.
 Pro,

 No memory reference to fetch data, other than instruction fetch. Fast

 cons

 Limited range, the size of memory reference restrict to the size of

addressing field

 Joanne E. DeGroat, OSU

Direct Addressing
 Simple but not common in current architecture.
 Address field contains address of operand
 Effective address (EA) = address field (A)
 e.g. ADD A
 Add contents of cell A to accumulator
 Look in memory at address A for operand
 Single memory reference to access data
 No additional calculations to work out effective address
 Limited address space

 Joanne E. DeGroat, OSU

 Direct Addressing Diagram
 Assume a system capable of 16 different types of operation and has a 4kword. A word
= 16bits
 4bit for opcode and 12 bits for address reference. No problem
Instruction
Opcode Address A
Memory

Operand

 Joanne E. DeGroat, OSU

Direct Addressing Mode
ACC←M[ADRS]

 Joanne E. DeGroat, OSU

Direct addressing in a branch
instruction

 Joanne E. DeGroat, OSU

Indirect Addressing (1)
 Memory cell pointed to by address field contains the address
of (pointer to) the operand
 EA = (A)
 Look in A, find address (A) and look there for operand
 e.g. ADD (A)
 Add contents of cell pointed to by contents of A to accumulator

 Large address space

 2n where n = word length
 Two memory refer to fetch the operand Hence
slower
 Joanne E. DeGroat, OSU
Indirect Addressing Diagram
• Assume a system memory extended to 64k words. So how can
we address these 64k memory cells?
Instruction
Opcode Address A
Memory

Pointer to operand

Operand

 Joanne E. DeGroat, OSU

 Register Addressing (1)
 Operand is held in register named in address filed
 EA = R
 Similar to direct addressing except here the address field refers to a register rather than a
memory address.
 Limited number of registers
 The address field will have from 3 to 5 bits. Total of 8 or 32 registers can be referenced.
 pros.
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 No memory access
 Very fast execution
 Cons.
 Very limited address space

 Joanne E. DeGroat, OSU

Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand

 Joanne E. DeGroat, OSU

Register Indirect Addressing

 C.f. indirect addressing

 EA = (R)
 Operand is in memory cell pointed to by contents
of register R
 Large address space (2n)
 One fewer memory access than indirect addressing

 Joanne E. DeGroat, OSU

Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 Joanne E. DeGroat, OSU

Displacement Addressing Diagram
Address field hold two values, EA = A + (R)
A = base value, R = register that holds displacement
Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

 Joanne E. DeGroat, OSU

 Relative Addressing

 The referenced register R is the program counter (PC)-the current

instruction address.
 R = Program counter, PC
 The address field A holds displacement
 EA = A + (PC)
 get operand from A cells from current location pointed to by PC

 Indexed Addressing
 A = base, R = displacement
 EA = A + R
 Good for accessing arrays
 EA = A + R
 R++

 Joanne E. DeGroat, OSU

Stack Addressing
 Operand is (implicitly) on top of stack
 e.g.
 ADD Pop top two items from stack and add

 Joanne E. DeGroat, OSU

Examples

 These are the values loaded into the accumulator for each addressing mode.

 Joanne E. DeGroat, OSU 28

Numerical example

 Joanne E. DeGroat, OSU

Symbolic convention for addressing mode

 Joanne E. DeGroat, OSU