Corona: H103358 Rev A

CR-1 : @CORONA_LIB.
CORONA(SCH_1):PAGE1
8 7 6 5 4 3 2 1
PAGE CONTENTS PAGE CONTENTS
D
[1]
[2]
COVER PAGE
GCPU, SETUP
[36]
[37]
CONN, FAN
CONN, AVIP
CORONA D
[3]
[4]
GCPU, DEBUG BUS
GCPU, VIDEO + PCIEX
[38]
[39]
CONN, RJ45 USB AUX COMBO +BORON +PWR
CONN, USB +MEMPORTS +TOSLINK +WAVEPORT REV 1.01
[5] GCPU, EEPROM + JTAG [40] CONN, HDMI
[6] GCPU, PLL PWR + FSB PWR [41] CONN, ODD + HDD FAB E
[7]
[8]
GCPU, PWR
GCPU, PWR
[42]
[43]
VREGS, BLEEDERS
VREGS, INPUT + OUTPUT FILTERS XDK 4L
[9] GCPU, DECOUPLING [44] VREGS, CPU CONTROLLER
[10] GCPU, DECOUPLING [45] VREGS, CPU OUTPUT PHASE 1 & 2
[11] GCPU, DECOUPLING [46] VREGS, V5P0DUAL
[12]
[13]
[14]
GCPU, MEMORY CONTROLLER A + B
GCPU, MEMORY CONTROLLER C + D
MEMORY PARTITION A, TOP
[47]
[48]
[49]
VREGS, V5P0
VREGS, V3P3
VREGS, VEDRAM
H103358
C
[15]
[16]
MEMORY PARTITION A, BOTTOM
MEMORY PARTITION B, TOP
[50]
[51]
VREGS, VMEM
VREGS, VCS
REV A C
[17] MEMORY PARTITION B, BOTTOM [52] VREGS, LINEARS

[18] MEMORY PARTITION C, TOP [53] VREGS, STANDBY SWITCHERS
[19] MEMORY PARTITION C, BOTTOM [54] BOARD, DECOUPLING
[20] MEMORY PARTITION D, TOP [55] MARGIN, VMEM + VEDRAM
[21] MEMORY PARTITION D, BOTTOM [56] MARGIN, V3P3 + V5P0
[22] KSB, CLOCKS + STRAPPING [57] MARGIN, VREFS + VCS
[23] KSB, VIDEO + FAN + AUDIO [58] MARGIN,VGPUPCIE+VCPUPLL+V1P8+V12P0+TEMP
[24] KSB, PCIEX + SMM GPIO + JTAG [59] MARGIN, STANDBY SWITCHERS
[25] KSB, SMC [60] MARGIN, V1P2
B [26] KSB, FLASH + USB + SPI [61] EXTERNAL TEMPERATURE SENSORS B
[27] KSB, ETHERNET + AUDIO + SATA [62] XDK, DEBUG CONN
[28] KSB, DECOUPLING [63] DEBUG BOARD, GPU CONN + TERM
[29] KSB, BULK DECOUPLING [64] DEBUG TEST POINTS
[30] KSB, STANDBY POWER + GROUND [65] XDK, DEBUG TITAN
[31] KSB, MAIN POWER [66] DEBUG BOARD, SPYDER CONN
[32] KSB OUT, MMC + FLASH [67] LABELS & MOUNTING
[33] KSB OUT, AUDIO [68] POWER ARCHITECTURE
[34] KSB OUT, FLASH [69] SYSTEM BLOCK DIAGRAM
[35] INFARED + SWITCHES [70] SYSTEM RESET DIAGRAM
[71] COMPONENT STUFFING TABLES
[72] I2C REFERENCE TABLES
[73] DOC TRACKING
RULES: (APPLIED WHEN POSSIBLE)
1.) MSB TO LSB IS TOP TO BOTTOM
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
A 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING A
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
12.) SUFFIX _P FOR P JUNCTION
13.) SUFFIX _EN FOR ENABLE
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
15.) PWRGD FOR POWER GOOD
16.) REV AND FAB ARE SET USING CUSTOM VARIABLES. TOOLS>OPTIONS>VARIABLES PROJECT NAME PAGE FAB REV
MICROSOFT
[PAGE_TITLE=COVER PAGE] DRAWING
Thu Feb 17 21:37:16 2011 CONFIDENTIAL
CORONA_XDK_4L 1/87 E 1.01
8 7 6 5 4 3 2 1
CR-2 : @CORONA_LIB.CORONA(SCH_1):PAGE2
8 7 6 5 4 3 2 1
GCPU SETUP R4P5
25 IN CPU_RST_N 2 1 CPU_RST_V1P1_N OUT 63
1.27 KOHM 1%
1 1 402 CH 1 R4P4
FT3T10 FTP C5R11 2 KOHM
360 PF 1%
D 5%
50 V 2 CH
D
2 EMPTY 402
1 603
FT3T11 FTP
25 IN CPU_PWRGD
1
1 R3E10 C5R66
10 KOHM 360 PF
5% 5% U5E1 14 OF 17 IC
CH 50 V
2 402 2 EMPTY GCPU VERSION 1
603 D5 HARD_RESET_B
CHECKSTOP_B E5 CPU_CHECKSTOP_N OUT 63
R4D1 T5 POWER_GOOD
22 IN CPU_CLK_DP 2 1
0 OHM 5%
402 CH
IN CPU_CLK_DP_R2 P2 CPU_CLK_DP
R4D2 VID6 C24 CPU_VREG_APS6 OUT 43

22 IN CPU_CLK_DN 2 1 VID5 B24 CPU_VREG_APS5 OUT 43
0 OHM 5% VID4 A24 CPU_VREG_APS4 OUT 43
C 402 CH VID3 C23
B23
CPU_VREG_APS3
CPU_VREG_APS2 OUT 43
C
V_CPUCORE VID2 OUT 43
IN CPU_CLK_DN_R2 P1 CPU_CLK_DN VID1 A23 CPU_VREG_APS1 OUT 43
1
I112 FTP FT7P8
1
FTP FT7P7
1 R4R22 1 R4R23 1
100 OHM 100 OHM FTP FT7P6
1
5% 5% CPU_DBG_RST_EN INTERNAL PULLDN FTP FT7P5
1
2 EMPTY 2 EMPTY FTP FT7P4
GPU_DBG_RST_EN INTERNAL PULLDN 1
402 402 FTP FT7P3
I1131
DB4R3 I114
1
DB4R2 CPU_DBG_RST_EN P5 CPU_DBG_RST_EN<DN>
GPU_DBG_RST_EN R5 GPU_DBG_RST_EN<DN>
OUT EDRAM_PSRO_DOUT N6 PSRO_DOUT

OUT CPU_PSRO0_OUT G7 PSRO0_OUT
V_CPUPLL
WHEN V_CPUPLL=1.83V N: IF V_CPUPLL CHANGES
SET VGATE=1.20V 1 R5T8 VGATE RESISTORS SHOULD BE ADJUSTED
ACTUAL=1.202V 562 OHM
1% J6 CPU_LIMIT_BYPASS
B 2 CH
402
<DN>PULSE_LIMIT_BYPASS OUT
B
CPU_VGATE V6 V_GATE <DN>PLL_BYPASS F8 CPU_PLL_BYPASS OUT
1 R5T9
1.07 KOHM
1%
2 CH RESISTOR0_DP L7 RESISTOR0_DP
402 OUT RESISTOR0_DN M7 A3 CPU_SRVID
OUT RESISTOR0_DN SRVID OUT 51
EFU_POWERON C1 VREG_EFUSE_EN OUT 52
OUT CPU_EXT_CLK_EN F7 EXT_CLK_EN<DN>

CPU_TINIT J7 TI_39_TINIT
CPU_TE E7 TE CORE_HF_BGR_PLL M6 CORE_HF_BGR_PLL OUT
1 R4R21 1 R4R20
200 OHM 200 OHM X818336-001 BGA_2
5% 5%
2 CH 2 CH
402 402
6 LAYER ONLY SIGNALS
CORE_HF_BGR_PLL 6 LAYER ONLY; TP ONLY

CPU_LIMIT_BYPASS 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_PLL_BYPASS 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_CORE_HF_CLKOUT_DN 6 LAYER ONLY; TP ONLY
A CPU_CORE_HF_CLKOUT_DP 6 LAYER ONLY; TP ONLY
A
CPU_EXT_CLK_EN 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_DLL_SNIF_OUT 6 LAYER ONLY; TP ONLY
CPU_VDDS0_DP 6 LAYER ONLY
CPU_VDDS0_DN 6 LAYER ONLY
CPU_VDDS1_DP 6 LAYER ONLY
CPU_VDDS1_DN 6 LAYER ONLY
RESISTOR0_DP 6 LAYER ONLY
RESISTOR0_DN 6 LAYER ONLY
MICROSOFT PROJECT NAME PAGE FAB REV
[PAGE_TITLE=GCPU SETUP] EDRAM_PSRO_DOUT 6 LAYER ONLY DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, DEBUG BUS
D D
U5E1 15 of 17 IC
GCPU VERSION 1
B9 15
CPU_DBG<0..15> OUT 3
CPU_DLL_SNIF_OUT W6 TB15_GPUCLK1
OUT DLL_SNIF_OUT D7 14
TB14_GPUCLK0
TB13_CPUCLK1 E8 13
OUT CPU_DBG_TBCLK1 B5 TBCLK1 D6 12
CPU_DBG_TBCLK0 A4 TB12_CPUCLK0
OUT TBCLK0 D9 11
TB11_GPU_HB
1 TB10_RESET2 C8 10
FT5P1 FTP
1 TB9_RESET1 A8 9
FT5P2 FTP
TB8_RESET0 D8 8
TB7_POST_OUT7 C5 7
B27 SPARE7
TB6_POST_OUT6 A5 6
H6 SPARE6
TB5_POST_OUT5 B6 5
J4 SPARE5
TB4_POST_OUT4 C6 4
K7 SPARE4
TB3_POST_OUT3 A6 3
L4 SPARE3
TB2_POST_OUT2 C7 2
AJ30 SPARE2 ALL POST IN'S HAVE INTERNAL PULLUPS
TB1_POST_OUT1 A7 1
AP26 SPARE1 B8 0
C AP7 SPARE0
TB0_POST_OUT0
POST_IN<0..4>
4 3 2 1 0 C
<UP>POST_IN4 F6 4
<UP>POST_IN3 G6 3
<UP>POST_IN2 G5 2
<UP>POST_IN1 F5 1
<UP>POST_IN0 H5 0
R4R5 1 R4R3 1 R4R8 1 R4R6 1 R4R13 1
X818336-001 BGA_2 200 OHM 200 OHM 200 OHM 200 OHM 200 OHM
5% 5% 5% 5% 5%
EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2
402 402 402 402 402
1 4
FT4R6 FTP
1 3
FT4R4 FTP
1 2
FT4R8 FTP
1 1
FT4R7 FTP
1 0
FT4R9 FTP
B B
CPU_DBG<0..15>
3 IN 15 CPU_DBG15_GPUCLK1 1
FTP FT5R9
14 CPU_DBG14_GPUCLK0 1
FTP FT5R12
13 CPU_DBG13_CPUCLK1 1
FTP FT5R13
12 CPU_DBG12_CPUCLK0 1
FTP FT5R11
11 CPU_DBG11_GPU_HB 1
FTP FT5R16
10 CPU_DBG10_RST2 1
FTP FT5R15
9 CPU_DBG9_RST1 1
FTP FT5R10
8 CPU_DBG8_RST0 1
FTP FT5R14
7 CPU_DBG7_POST7 1
FTP FT5R1
6 CPU_DBG6_POST6 1
FTP FT5R2
5 CPU_DBG5_POST5 1
FTP FT5R3
4 CPU_DBG4_POST4 1
FTP FT5R4
3 CPU_DBG3_POST3 1
FTP FT5R5
2 CPU_DBG2_POST2 1
FTP FT5R6
1 CPU_DBG1_POST1 1
FTP FT5R7
0 CPU_DBG0_POST0 1
FTP FT5R8
A A

[PAGE_TITLE=GCPU, DEBUG BUS] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, VIDEO + PCIEX

D GPU_CLK_DP 1
R4E1
2 C4E1
D
22 IN 0.1 UF 10%
0 OHM 5% 6.3 V U5E1 5 OF 17 IC 1
402 CH X5R FTP FT3T2
402 GCPU VERSION 1
GPU_CLK_DP_C 1 2 GPU_CLK_DP_R2 R2 NB_CLK_DP RST_DONE U6 GPU_RST_DONE 25
OUT OUT
R4E2 C5E2
PEX_TX1_DP U2 PEX_GPU_SB_L1_DP_C 1 2 PEX_GPU_SB_L1_DP 24 62
22 GPU_CLK_DN 1 2 1 2 GPU_CLK_DN_R2 R1 NB_CLK_DN OUT
IN
0 OHM 5% 0.1 UF 10%
402 CH C4E2 6.3 V
0.1 UF 10% X5R C5E1 PEX_GPU_SB_L1_DN
GPU_CLK_DN_C 6.3 V PEX_TX1_DN U1 PEX_GPU_SB_L1_DN_C 402 1 2 24 62
OUT X5R OUT
402 0.1 UF 10%
1 6.3 V
FT3R17 FTP
C5E4 X5R
25 GPU_RST_N D2 RST_IN_N* PEX_TX0_DP W2 PEX_GPU_SB_L0_DP_C 1 2 402 PEX_GPU_SB_L0_DP 24 62
IN OUT
PEX_SB_GPU_L1_DP T2 0.1 UF 10%
24 IN PEX_RX1_DP 6.3 V
24 IN PEX_SB_GPU_L1_DN T1 PEX_RX1_DN X5R C5E3
24 PEX_SB_GPU_L0_DP V2 PEX_RX0_DP PEX_TX0_DN W1 PEX_GPU_SB_L0_DN_C 402 1 2 PEX_GPU_SB_L0_DN 24 62
IN PEX_SB_GPU_L0_DN V1
OUT
24 IN PEX_RX0_DN
0.1 UF 10%
6.3 V
X5R
C 22 IN PIX_CLK_2X_DP N1 PIX_CLK_IN_DP J2
402 GPU_PIX_CLK_1X C
PIX_CLK_2X_DN N2 PIX_CLK_OUT OUT 23
22 IN PIX_CLK_IN_DN
PEX_RCAL V3 PEX_RCAL
2 R5T1 F2 14
PIX_DATA<14..0> OUT 23
PIX_DATA14
4.99 KOHM PIX_DATA13 F1 13
1% F3 12
PIX_DATA12
1 CH G2 11
402 PIX_DATA11
PIX_DATA10 G1 10
61 IN GPU_TEMP_P P4 NB_THERMD_P PIX_DATA9 H3 9
PIX_DATA8 H2 8
PIX_DATA7 H1 7
PIX_DATA6 J1 6
PIX_DATA5 K3 5
PIX_DATA4 K2 4
61 OUT GPU_TEMP_N P3 NB_THERMD_N PIX_DATA3 K1 3
PIX_DATA2 L2 2
61 IN EDRAM_TEMP_P V4 ED_THERMD_P PIX_DATA1 L1 1
PIX_DATA0 M3 0
VSYNC_OUT M1 GPU_VSYNC_OUT OUT 23

HSYNC_OUT M2 GPU_HSYNC_OUT OUT 23
B EDRAM_TEMP_N V5 B
61 OUT ED_THERMD_N
61 IN CPU_TEMP_P M5 CPU_THERMD_P
61 OUT CPU_TEMP_N L5 CPU_THERMD_N
MEM_RST AD27 MEM_RST OUT 14 15 16 17 18 19 20 21

MEM_SCAN_EN AB33 MEM_SCAN_EN OUT 14 15 16 17 18 19 20 21
MEM_CALA W27 MEM_CALA MEM_SCAN_OEN_A AF7 MEM_SCAN_TOP_EN OUT 14 16 18 20
MEM_CALB AG18 MEM_CALB MEM_SCAN_OEN_B AE7
1 R7T7 1 R7R6 2 R6F6 2 R7E2
2 R6T6 X818336-001 BGA_2 1 KOHM 1 KOHM 1 KOHM 1 KOHM
2 R6T3 240 OHM
240 OHM 5% 5% 5% 5%
1%
1% 2 CH 2 CH 1 CH 1 CH
1 CH 402 402 402 402
1 CH 402
402
V_MEM
VIDEO DECOUPLING V_MEM
V_MEM 1 R6U6
U5U2 EMPTY 1 KOHM
5%
A 5 VCC
2 CH
402
A
MEM_SCAN_BOT_EN_N 2 A
C5T36 Y 4 MEM_SCAN_BOT_EN 15 17 19 21
0.1 UF 1 NC OUT
10%
6.3 V R5U6 1
X5R 1 KOHM 3 GND
402 5%
CH 2
402 X801851-001

[PAGE_TITLE=GCPU, VIDEO + PCIEX] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, EEPROM + JTAG
D D
V_MEM
1
FT4P10 FTP
1 V_MEM
FT4P6 FTP 2 R4R2
1 100 OHM
FT4P5 FTP
1 5%
FT4P4 FTP U5E1 17 of 17 IC
1 1 EMPTY V_MEM
FT4P7 FTP DB4R1
GCPU VERSION 1 402
TP 2 R4R12
63 OUT CPU_TCLK C2 CPU_TCLK<UP> <DN>SROM_EN E3 GPU_SROM_EN 1 10 KOHM V_MEM
CPU_TDO B1 5%
63 OUT CPU_TDO<UP>
C 63 OUT CPU_TDI
CPU_TMS
B2
B4
CPU_TDI<UP>
1 CH
402 C
63 OUT CPU_TMS<UP> EMPTY
CPU_TRST_N A2 U4P1
63 OUT CPU_TRST_B<UP> R4P6 AT25020A
<DN>SROM_SCLK D3 GPU_SROM_SCLK 1 2 6 SCK
R3C15
63 CPU_TRST_N_R 1 2 1 KOHM 5%
OUT 402 CH
5% 0 OHM 1 R4C3 R4R11 8
CH 402 E1 GPU_SROM_SO 1 2 5 VCC
200 OHM <DN>SROM_SI SDI
5% 1 KOHM 5% 2
402 CH SDO 1
2 EMPTY 7 C4P5
V_MEM V_MEM 402 R4R7 HOLD_N*
<UP>SROM_CS D1 GPU_SROM_CS 1 2 1 CS_N* 0.1 UF
10%
1 KOHM 5% 3 WP_N* GND 4 6.3 V
402 CH 2 X5R
1 R4C8 1 R3C26 402
1 100 OHM 100 OHM X800552-001
FT4R11 FTP 5% 5%
2 EMPTY 2 EMPTY E2
GPU_TRST_N 402 402 R6 <DN>SROM_SO
63 OUT GPU_TRST_B<DN>
63 OUT GPU_TRST_ED_N U5 GPU_TRST_ED_B<DN> 1 R4R10
10 KOHM
FT4P8 FTP
1
1 5% GPU_SROM_SCLK_R IN 63
C3C5 X818336-001 BGA_2 2 EMPTY GPU_SROM_SO_R IN 63
0.01 UF 402 GPU_SROM_CS_N_R 63
10%
GPU_SROM_WP_N IN
16 V IN 63
B 2 EMPTY
402
GPU_SROM_SI OUT 63
B
A A

[PAGE_TITLE=GCPU, EEPROM + JTAG] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, PLL POWER + FSB POWER
V_GPUPCIE V_CPUEDRAM V_CPUPLL V_EFUSE U5E1 16 of 17 IC
GCPU VERSION 1
E4 VDDE CORE_HF_CLKOUT_DP L6 CPU_CORE_HF_CLKOUT_DP OUT
D CPU_VDDS1_DP H25
CORE_HF_CLKOUT_DN K6 CPU_CORE_HF_CLKOUT_DN OUT D
OUT VDDS1_DP
OUT CPU_VDDS1_DN J26 VDDS1_DN
OUT CPU_VDDS0_DP P7 VDDS0_DP

OUT CPU_VDDS0_DN N7 VDDS0_DN
FB5R1
1 2 V_CPU_PVDDA_MEM D4 PVDDA_MEM
FB 1 C5R14
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R1 X5R
1 2 2 805 C4
V_CPU_PVSSA_MEM PVSSA_MEM
SHORT
FB5T2
1 2 V_CPU_PVDDA_PEX U3 PVDDA_PEX
FB 1 C5T9
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5T1 X5R
1 22 805 V_CPU_PVSSA_PEX U4 PVSSA_PEX
C SHORT C
FB5R2
1 2 V_CPU_PVDDA_HS C3 PVDDA_HS
FB 1 C5R17
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R2 X5R
1 2 2 805 B3
V_CPU_PVSSA_HS PVSSA_HS
SHORT
FB5T3
1 2 V_CPU_PVDDA_ED W5 PVDDA_ED
FB 1
0.2A 603 C5T13
0.5 DCR 4.7 UF
10%
6.3 V
ST5T2 2 X5R
1 2 603 V_CPU_PVSSA_ED W4 PVSSA_ED
SHORT 1
DB5R5
FB5R5
B 1 2
C5R54
V_CPU_VDDA_RNG N4 VDDA_RNG
B
FB 1
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R5 X5R
1 2 2 805 N3
V_CPU_GNDA_RNG GNDA_RNG
SHORT
FB5R4
1 2 V_CPU_CORE_HF_VDDA_PLL J5 CORE_HF_VDDA_PLL
FB 1 C5R42
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R4 X5R
1 2 2 805 V_CPU_CORE_HF_GNDA_PLL K5 CORE_HF_GNDA_PLL
SHORT
FB5R3
1 2 V_GPU_VDDA_PLL G4 GPU_VDDA_PLL
FB
0.2A 603 1
0.5 DCR C5R31
10 UF
20%
6.3 V
ST5R3 2 X5R
1 2 805 V_GPU_GNDA_PLL H4 GPU_GNDA_PLL
SHORT
A R3
A
VDD_VTT
FB5T1
1 2 V_CPU_VDD_VTTA R4 VDD_VTTA
FB
0.2A 603 1 1
0.5 DCR C5T4 C5T6
4.7 UF 0.1 UF X818336-001 BGA_2
10% 10%
2
6.3 V
2
6.3 V
X5R X5R DRAWING
[PAGE_TITLE=GCPU, PLL POWER + FSB POWER] 603 402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, POWER
D D
V_CPUVCS V_CPUVCS V_MEM V_MEM V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE

U5E1 8 OF 17 IC U5E1 10 OF 17 IC
U5E1 9 OF 17 IC
U5E1 6 OF 17 IC
GCPU VERSION 1 GCPU VERSION 1
GCPU VERSION 1 A21 H16
GCPU VERSION 1 R23 Y12 VDD_CORE189 VDD_CORE143
A11 V_CS20 F10 A33 AG23 VDD_CORE91 VDD_CORE45 A19 H14
V_CS28 V_MEM111 V_MEM56 R21 AA25 VDD_CORE188 VDD_CORE142
A9 V_CS19 G11 B34 AG20 VDD_CORE90 VDD_CORE44 A17 H12
B10 V_CS18 G9 C31 AG17 VDD_CORE89 VDD_CORE43 A15 J25
C11 V_CS17 H10 C29 AG15 VDD_CORE88 VDD_CORE42 A13 J23
C9 V_CS16 H8 C27 AG13 VDD_CORE87 VDD_CORE41 B22 J21
C D10
E11
V_CS23 V_CS15 J9
K10
D32
D30
V_MEM106 V_MEM51 AG10
AG7 R11
VDD_CORE86
VDD_CORE85
VDD_CORE40
VDD_CORE39 AA15
B20
B18
VDD_CORE183 VDD_CORE137 J19
J17 C
V_CS22 V_CS14 V_MEM105 V_MEM50 T26 AA13 VDD_CORE182 VDD_CORE136
E9 V_CS13 K8 D28 AG4 VDD_CORE84 VDD_CORE38 B16 J15
V_CS21 V_MEM104 V_MEM49 T24 AB26 VDD_CORE181 VDD_CORE135
V_CS12 L9 D25 AH32 VDD_CORE83 VDD_CORE37 B14 J13
V_MEM103 V_MEM48 T22 AB24 VDD_CORE180 VDD_CORE134
V_CS11 M10 E31 AH29 VDD_CORE82 VDD_CORE36 B12 J11
V_CS10 M8 E26 AH27 VDD_CORE81 VDD_CORE35 C21 K26
V_CS9 N9 F32 AH24 VDD_CORE80 VDD_CORE34 C19 K24
V_CS8 P10 F28 AH19 VDD_CORE79 VDD_CORE33 C17 K22
V_CS7 P8 G31 AH14 VDD_CORE78 VDD_CORE32 C15 K20
V_CS6 R9 G29 AH9 VDD_CORE77 VDD_CORE31 C13 K18
V_MEM97 V_MEM42 U25 AB12 VDD_CORE174 VDD_CORE128
V_CS5 T10 G27 AH8 VDD_CORE76 VDD_CORE30 D24 K16
V_MEM96 V_MEM41 U23 AC25 VDD_CORE173 VDD_CORE127
V_CS4 T8 G25 AH6 VDD_CORE75 VDD_CORE29 D22 K14
V_CS3 U9 H32 AH3 VDD_CORE74 VDD_CORE28 D20 K12
V_CS2 V10 H28 AJ31 VDD_CORE73 VDD_CORE27 D18 L25
V_CS1 V8 H26 AJ28 VDD_CORE72 VDD_CORE26 D16 L23
V_CS0 W9 J32 AJ26 VDD_CORE71 VDD_CORE25 D14 L21
J29 AJ22 VDD_CORE70 VDD_CORE24 D12 L19
K27 AJ21 VDD_CORE69 VDD_CORE23 E23 L17
X818336-001 BGA_2 V_MEM89 V_MEM34 V26 AD26 VDD_CORE166 VDD_CORE120
L31 AJ16 VDD_CORE68 VDD_CORE22 E21 L15
V_MEM88 V_MEM33 V24 AD24 VDD_CORE165 VDD_CORE119
L28 AJ12 VDD_CORE67 VDD_CORE21 E19 L13
M30 AJ11 VDD_CORE66 VDD_CORE20 E17 L11
M27 AJ7 VDD_CORE65 VDD_CORE19 E15 M26
N29 AJ4 VDD_CORE64 VDD_CORE18 E13 M24
B V_CPUEDRAM V_CPUEDRAM P31
V_MEM84
V_MEM83
V_MEM29
V_MEM28 AK32 V16
V14
VDD_CORE63 VDD_CORE17 AD16
AD14
F24
VDD_CORE161
VDD_CORE160
VDD_CORE115
VDD_CORE114 M22 B
P29 AK23 VDD_CORE62 VDD_CORE16 F22 M20
U5E1 7 OF 17 IC R27 AK13 VDD_CORE61 VDD_CORE15 F20 M18
V_MEM81 V_MEM26 W25 AE25 VDD_CORE158 VDD_CORE112
T32 AK3 VDD_CORE60 VDD_CORE14 F18 M16
GCPU VERSION 1 V_MEM80 V_MEM25 W23 AE23 VDD_CORE157 VDD_CORE111
R7 AB6 T28 AL31 VDD_CORE59 VDD_CORE13 F16 M14
V_EDRAM47 V_EDRAM23 V_MEM79 V_MEM24 W21 AE21 VDD_CORE156 VDD_CORE110
T6 AB4 V31 AL29 VDD_CORE58 VDD_CORE12 F14 M12
U7 AB2 V27 AL27 VDD_CORE57 VDD_CORE11 F12 N25
W7 AC11 W32 AL24 VDD_CORE56 VDD_CORE10 G23 N23
Y11 AC10 W29 AL21 VDD_CORE55 VDD_CORE9 G21 N21
Y10 AC9 Y27 AL17 VDD_CORE54 VDD_CORE8 G19 N19
V_EDRAM42 V_EDRAM18 V_MEM74 V_MEM19 W11 AF26 VDD_CORE151 VDD_CORE105
Y8 AC8 AA31 AL14 VDD_CORE53 VDD_CORE7 G17 N17
V_EDRAM41 V_EDRAM17 V_MEM73 V_MEM18 Y26 AF24 VDD_CORE150 VDD_CORE104
Y6 AC7 AA28 AL11 VDD_CORE52 VDD_CORE6 G15 N15
Y4 AC6 AB30 AL8 VDD_CORE51 VDD_CORE5 G13 N13
Y2 AC5 AB27 AL6 VDD_CORE50 VDD_CORE4 H24 N11
Y1 AC4 AC29 AL4 VDD_CORE49 VDD_CORE3 H22 P26
AA11 AC3 AD31 AM34 VDD_CORE48 VDD_CORE2 H20 P24
AA10 AC2 AD29 AM30 VDD_CORE47 VDD_CORE1 H18 P22
AA9 AC1 AE8 AM28 VDD_CORE46 VDD_CORE0 P20
V_EDRAM34 V_EDRAM10 V_MEM66 V_MEM11 VDD_CORE97
AA8 V_EDRAM33 V_EDRAM9 AD11 AE4 V_MEM65 V_MEM10 AM26 VDD_CORE96 P18
AA7 AD10 AF32 AM19 X818336-001 BGA_2 P16
V_EDRAM32 V_EDRAM8 V_MEM64 V_MEM9 VDD_CORE95
AA6 V_EDRAM31 V_EDRAM7 AD8 AF28 V_MEM63 V_MEM8 AM16 VDD_CORE94 P14
AA5 V_EDRAM30 V_EDRAM6 AD6 AF27 V_MEM62 V_MEM7 AM9 VDD_CORE93 P12
AA4 V_EDRAM29 V_EDRAM5 AD4 AF6 V_MEM61 V_MEM6 AM7 VDD_CORE92 R25
AA3 V_EDRAM28 V_EDRAM4 AD2 AF3 V_MEM60 V_MEM5 AM5
AA2 V_EDRAM27 V_EDRAM3 AD1 AG31 V_MEM59 V_MEM4 AM3 X818336-001 BGA_2
AA1 V_EDRAM26 V_EDRAM2 AE11 AG28 V_MEM58 V_MEM3 AN33
AB10 V_EDRAM25 V_EDRAM1 AE9 AG25 V_MEM57 V_MEM2 AN1
AB8 V_EDRAM24 V_EDRAM0 AF10 V_MEM1 AP34
A V_MEM0 AP2 A
X818336-001 BGA_2
X818336-001 BGA_2

[PAGE_TITLE=GCPU, POWER] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, POWER
D D
U5E1 11 OF 17 IC
U5E1 12 OF 17 IC
GCPU VERSION 1
AF15 GCPU VERSION 1
VSS65 K29 R16
Y3 AF13 VSS260 VSS195
VSS130 VSS64 K25 R14
AA32 AF11 VSS259 VSS194 U5E1 13 OF 17 IC
VSS129 VSS63 K23 R12
AA27 AF9 VSS258 VSS193
VSS128 VSS62 K21 R10 GCPU VERSION 1
AA26 AF8 VSS257 VSS192 A34 E24
VSS127 VSS61 K19 R8 VSS354 VSS318
AA24 AF4 VSS256 VSS191 A22 E22
VSS126 VSS60 K17 T31 VSS353 VSS317
AA22 AG32 VSS255 VSS190 A20 E20
AA20 AG29 VSS254 VSS189 A18 E18
AA18 AG27 VSS253 VSS188 A16 E16
AA16 AG26 VSS252 VSS187 A14 E14
AA14 AG24 VSS251 VSS186 A12 E12
AA12 AG22 VSS250 VSS185 A10 E10
VSS120 VSS54 L32 T17 VSS347 VSS311
AB25 AG21 VSS249 VSS184 B33 E6
AB23 AG19 VSS248 VSS183 B21 F31
AB21 AG16 VSS247 VSS182 B19 F29
AB19 AG14 VSS246 VSS181 B17 F27
AB17 AG12 VSS245 VSS180 B15 F23
AB15 AG11 VSS244 VSS179 B13 F21
AB13 AG9 VSS243 VSS178 B11 F19
AB11 AG8 VSS242 VSS177 B7 F17
VSS112 VSS46 L14 U30 VSS339 VSS303
C AB9
AB7
VSS111 VSS45 AG6
AG3
L12
VSS241
VSS240
VSS176
VSS175 U27
C28
C25
VSS338 VSS302 F15
F13 C
AB5 AH31 VSS239 VSS174 C22 F11
VSS107 VSS41 M25 U20 VSS334 VSS298
AC31 AH4 VSS236 VSS171 C16 G32
AC27 AJ32 VSS235 VSS170 C14 G28
AC26 AJ29 VSS234 VSS169 C12 G24
AC24 AJ27 VSS233 VSS168 C10 G22
AC22 AJ25 VSS232 VSS167 D31 G20
AC20 AJ20 VSS231 VSS166 D29 G18
AC18 AJ17 VSS230 VSS165 D27 G16
VSS100 VSS34 M11 V29 VSS327 VSS291
AC16 AJ15 VSS229 VSS164 D23 G14
AC14 AJ10 VSS228 VSS163 D21 G12
AC12 AJ8 VSS227 VSS162 D19 G10
VSS97 VSS31 N31 V21 VSS324 VSS288
AD32 AJ6 VSS226 VSS161 D17 G8
AD25 AJ3 VSS225 VSS160 D15 G3
AD23 AK31 VSS224 VSS159 D13 H31
AD21 AK18 VSS223 VSS158 D11 H29
AD19 AK4 VSS222 VSS157 E32 H27
AD17 AL32 VSS221 VSS156 H23
VSS91 VSS25 N18 V9 VSS282
VSS90 VSS24 N16 V7 VSS281
B AD9
VSS89
VSS88
VSS23
VSS22 AL26
N14
N12
VSS218 VSS153 W31
W26
VSS280
VSS279 H17 B
VSS87 VSS21 N10 W24 VSS278
AE29 AL12 VSS214 VSS149 H9
VSS84 VSS18 P32 W18 VSS275
AE27 AL9 VSS213 VSS148 H7
AE26 AL7 VSS212 VSS147 J31
AE20 AM33 VSS209 VSS144 J22
VSS77 VSS11 P15 Y29 VSS268
VSS72 VSS6 R29 Y17 VSS263
AF31 AM8 VSS201 VSS136 J3
VSS71 VSS5 R26 Y15 VSS261
AF25 AM6 VSS200 VSS135
VSS70 VSS4 R24 Y13
AF23 AM4 VSS199 VSS134
VSS69 VSS3 R22 Y9
AF21 AN34 VSS198 VSS133 X818336-001 BGA_2
VSS68 VSS2 R20 Y7
AF19 AP33 VSS197 VSS132
VSS67 VSS1 R18 Y5
AF17 AP1 VSS196 VSS131
VSS66 VSS0
X818336-001 BGA_2
X818336-001 BGA_2
A A

DRAWING
[PAGE_TITLE=GCPU, POWER] Thu Feb 17 10:12:27 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE V_CPUEDRAM V_CPUVCS
D D
C6R4 C5D13 C5R8 C5R9 C5T26 C5E6 C5R35 C5D1

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R X5R
603 603 603 603 402 603 402 603
C5R15 C5D14 C6D3 C5D7 C5T32 C5E5 C5R58 C5R4

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 402 603 402 603
C5R7
C6R3 C5D3 1 2 C5D6 C5T24 C5T35 C5R43 C5D4
1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
4.7 UF 10% 4.7 UF 10% 6.3 V 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R
C 603 603
603
603 402 603 402 603 C
C5D5
C5R10 C5D8 C6R6 1 2 C5T31 C5E7 C5T7 C5R1
1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 6.3 V 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R 603 X5R X5R X5R X5R
603 603 603 402 603 402 603
C6D4
C5R6 1 2 C5D9 C5T27 C5T34 C5R50
C5D12 1 2 1 2 1 2 1 2 1 2
1 2
4.7 UF 10%
4.7 UF 10% 6.3 V 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10%
4.7 UF 10% 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V
6.3 V X5R 603 X5R X5R X5R X5R
X5R 603 603 402 603 402
603
C6R2 C5R5 C6R1 C5R18 C5T22 C5T43 C5T1

1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R
B 603 603 603 603 402 603 402 B
C5R12 C5D2 C5R3 C5D10 C5T23 C5E8
1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
603 603 603 603 402 603
C6D5 C5R16 C6R7 C5D11 C5T20 C5E9

1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 402 603
C6D1 C6D2 C6D6 C5T33 C5T25 C4T3

1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 402 603
C5R2
C6R5 C5R13 1 2 C6T22 C5T21 C4T4
1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
A
4.7 UF 10%
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
0.1 UF 10%
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
A
603
603 603 603 402 603
C6T23
1 2
4.7 UF 10%
6.3 V
X5R
603

[PAGE_TITLE=GCPU, DECOUPLING] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE
D D
C5T12 C5R26 C5T17 C5T10 C6R36
1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C5R33 C6R25 C6T11 C5T8 C5R63

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C5R39 C5R60 C6R42 C6R45 C5R28

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
C 402 402 402 402 402
C
C5R40 C5R61 C5R37 C5R49 C5R59
1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6T7 C6T20 C6R37 C6R33 C5R27

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C5R38 C5R32 C5R57 C6T8 C5R62

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
B 402 402 402 402 402
B
C6T12 C6T6 C5R64 C6R15 C5R55
1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6R31 C6R28 C5R46 C6R21 C5R51

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6R38 C5R36 C5R45 C6R20 C6R18

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6R43 C5T11 C6T14 C6R44 C6R17

1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
A 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R A
402 402 402 402 402

DRAWING
[PAGE_TITLE=GCPU, DECOUPLING] Thu Feb 17 10:12:27 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE
D D
C5R25 C6R8 C6R39 C5R30 C6T5 C5T14

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C6T15 C6R34 C6T3 C5R52 C5R21 C6T9

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C5T19 C6R19 C6R35 C5T15 C5T16 C5T3

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
C 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R C
402 402 402 402 402 402
C6T18 C5R53 C6R22 C5T28 C6T19 C6R13

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C6R9 C5T30 C5R44 C5R41 C6T25 C5R34

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C6R10 C5T29 C5R47 C6R24 C6R12 C6R14

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
B 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R B
402 402 402 402 402 402
C5R20 C5R24 C5R48 C6T2 C5T2 C5T5

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C5R19 C5R56 C6R26 C6T16 C6T17 C6T13

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C5R22 C6T4 C6R32 C5T18 C6R40 C6T24

1 2 1 2 1 2 1 2 1 2 1 2
0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402
C5R23 C5R29 C6R29 C6R30 C6R41

1 2 1 2 1 2 1 2 1 2
A 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
A
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

[PAGE_TITLE=GCPU, DECOUPLING] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU, MEMORY CONTROLLER 0 PARTITION A & B
U5E1 4 OF 17 IC U5E1 3 OF 17 IC
D 15 14 BI MA_DQ31
MA_DQ30
T34
T33
MA_DQ31 17 16 BI MB_DQ31
MB_DQ30
H33
G34
MB_DQ31 D
15 14 BI MA_DQ30 17 16 BI MB_DQ30
15 14 BI MA_DQ29 U31 MA_DQ29 17 16 BI MB_DQ29 H34 MB_DQ29
15 14 BI MA_DQ28 R33 MA_DQ28 17 16 BI MB_DQ28 F34 MB_DQ28
15 14 BI MA_DQ27 U33 MA_DQ27 17 16 BI MB_DQ27 K31 MB_DQ27
15 14 BI MA_DQ26 R32 MA_DQ26 17 16 BI MB_DQ26 D34 MB_DQ26
15 14 BI MA_DQ25 V33 MA_DQ25 17 16 BI MB_DQ25 K32 MB_DQ25
15 14 BI MA_DQ24 R31 MA_DQ24 17 16 BI MB_DQ24 C34 MB_DQ24
15 14 OUT MA_WDQS3 R34 MA_WDQS3 17 16 OUT MB_WDQS3 E34 MB_WDQS3
15 14 IN MA_RDQS3 U32 MA_RDQS3 17 16 IN MB_RDQS3 J33 MB_RDQS3
15 14 OUT MA_DM3 U34 MA_DM3 17 16 OUT MB_DM3 J34 MB_DM3
15 14 BI MA_DQ23 Y34 MA_DQ23 MA_CLK1_DP AE28 MA_CLK1_DP OUT 15 17 16 BI MB_DQ23 M32 MB_DQ23 MB_CLK1_DP B32 MB_CLK1_DP OUT 17
15 14 BI MA_DQ22 Y33 MA_DQ22 MA_CLK1_DN AE30 MA_CLK1_DN OUT 15 17 16 BI MB_DQ22 M34 MB_DQ22 MB_CLK1_DN A32 MB_CLK1_DN OUT 17
15 14 BI MA_DQ21 Y32 MA_DQ21 MA_CLK0_DP AC33 MA_CLK0_DP OUT 14 17 16 BI MB_DQ21 M31 MB_DQ21 MB_CLK0_DP B31 MB_CLK0_DP OUT 16
15 14 BI MA_DQ20 AA33 MA_DQ20 MA_CLK0_DN AC34 MA_CLK0_DN OUT 14 17 16 BI MB_DQ20 M33 MB_DQ20 MB_CLK0_DN A31 MB_CLK0_DN OUT 16
15 14 BI MA_DQ19 W33 MA_DQ19 17 16 BI MB_DQ19 K33 MB_DQ19
15 14 BI MA_DQ18 AB31 MA_DQ18 MA_A12 AL33 MA_A<11..0> 17 16 BI MB_DQ18 N34 MB_DQ18 MB_A12 C30
MB_A<11..0>
MA_DQ17 V34 AH34 11 OUT 14 15 MB_DQ17 K34 F25 11 OUT 16 17
15 14 BI MA_DQ17 MA_A11 17 16 BI MB_DQ17 MB_A11
15 14 BI MA_DQ16 AB32 MA_DQ16 MA_A10 AL34 10 17 16 BI MB_DQ16 P33 MB_DQ16 MB_A10 A25 10
15 14 OUT MA_WDQS2 AA34 MA_WDQS2 MA_A9 AG34 9 17 16 OUT MB_WDQS2 N33 MB_WDQS2 MB_A9 E29 9
15 14 IN MA_RDQS2 Y31 MA_RDQS2 MA_A8 AD33 8 17 16 IN MB_RDQS2 L34 MB_RDQS2 MB_A8 B30 8
15 14 OUT MA_DM2 W34 MA_DM2 MA_A7 AF34 7 17 16 OUT MB_DM2 L33 MB_DM2 MB_A7 B29 7
AE33 6 A30 6
C 15 14 BI MA_DQ15 W28 MA_DQ15
MA_A6
MA_A5 AD34 5 17 16 BI MB_DQ15 J28 MB_DQ15
MB_A6
MB_A5 C32 5 C
15 14 BI MA_DQ14 R30 MA_DQ14 MA_A4 AF33 4 17 16 BI MB_DQ14 C33 MB_DQ14 MB_A4 A29 4
15 14 BI MA_DQ13 W30 MA_DQ13 MA_A3 AG33 3 17 16 BI MB_DQ13 J30 MB_DQ13 MB_A3 E25 3
15 14 12 BI MA_DQ12 R28 MA_DQ12 MA_A2 AH33 2 17 16 12 BI MB_DQ12 D33 MB_DQ12 MB_A2 G26 2
15 14 BI MA_DQ11 V28 MA_DQ11 MA_A1 AK33 1 17 16 BI MB_DQ11 F33 MB_DQ11 MB_A1 B25 1
15 14 BI MA_DQ10 T29 MA_DQ10 MA_A0 AJ34 0 17 16 BI MB_DQ10 E33 MB_DQ10 MB_A0 F26 0
15 14 BI MA_DQ9 U29 MA_DQ9 MA_BA<2..0> 17 16 BI MB_DQ9 G30 MB_DQ9 MB_BA<2..0>
MA_DQ8 U28 AE34 2 OUT 14 15 MB_DQ8 F30 E28 2 OUT 16 17
15 14 BI MA_DQ8 MA_BA2 17 16 BI MB_DQ8 MB_BA2
15 14 12 OUT MA_WDQS1 T30 MA_WDQS1 MA_BA1 AE32 1 17 16 12 OUT MB_WDQS1 E30 MB_WDQS1 MB_BA1 B28 1
15 14 IN MA_RDQS1 V30 MA_RDQS1 MA_BA0 AK34 0 17 16 IN MB_RDQS1 G33 MB_RDQS1 MB_BA0 E27 0
15 14 OUT MA_DM1 V32 MA_DM1 17 16 OUT MB_DM1 H30 MB_DM1
MA_CKE AJ33 MA_CKE OUT 14 15 MB_CKE A27 MB_CKE OUT 16 17
15 14 BI MA_DQ7 Y30 MA_DQ7 MA_WE_N* AF29 MA_WE_N OUT 14 15 17 16 BI MB_DQ7 K30 MB_DQ7 MB_WE_N* B26 MB_WE_N OUT 16 17
15 14 BI MA_DQ6 AD28 MA_DQ6 MA_CAS_N* AG30 MA_CAS_N OUT 14 15 17 16 BI MB_DQ6 P28 MB_DQ6 MB_CAS_N* C26 MB_CAS_N OUT 16 17
15 14 BI MA_DQ5 Y28 MA_DQ5 MA_RAS_N* AH30 MA_RAS_N OUT 14 15 17 16 BI MB_DQ5 K28 MB_DQ5 MB_RAS_N* D26 MB_RAS_N OUT 16 17
15 14 12 BI MA_DQ4 AD30 MA_DQ4 MA_CS1_N* AF30 MA_CS1_N OUT 14 15 17 16 12 BI MB_DQ4 P30 MB_DQ4 MB_CS1_N* A28 MB_CS1_N OUT 16 17
15 14 BI MA_DQ3 AB28 MA_DQ3 MA_CS0_N* AE31 MA_CS0_N OUT 14 17 16 BI MB_DQ3 M28 MB_DQ3 MB_CS0_N* A26 MB_CS0_N OUT 16
15 14 BI MA_DQ2 AC30 MA_DQ2 17 16 BI MB_DQ2 N30 MB_DQ2
15 14 BI MA_DQ1 AB29 MA_DQ1 17 16 BI MB_DQ1 M29 MB_DQ1
15 14 BI MA_DQ0 AC28 MA_DQ0 17 16 BI MB_DQ0 N28 MB_DQ0
15 14 12 OUT MA_WDQS0 AC32 MA_WDQS0 17 16 12 OUT MB_WDQS0 N32 MB_WDQS0
15 14 IN MA_RDQS0 AA29 MA_RDQS0 17 16 IN MB_RDQS0 L29 MB_RDQS0
B 15 14 OUT MA_DM0 AA30 MA_DM0 17 16 OUT MB_DM0 L30 MB_DM0
B
R6T8
AB34 MA_VREF0 15 14 12 OUT MA_WDQS1 1 2 P34 MB_VREF0
4.75 KOHM 1% R6R2
X818336-001 BGA_2 402 CH X818336-001 BGA_2 MB_WDQS1 1 2
MA_DQ12 17 16 12 OUT
15 14 12 BI 4.75 KOHM 1%
402 CH
17 16 12 BI MB_DQ12
R6T7
15 14 12 BI MA_DQ4 1 2 R6R1
V_MEM 4.75 KOHM 1% 17 16 12 BI MB_DQ4 1 2
402 CH V_MEM 4.75 KOHM 1%
15 14 12 OUT MA_WDQS0 402 CH
17 16 12 OUT MB_WDQS0
1 R6T5 1 R6T2
549 OHM
1% V_MEM 549 OHM V_MEM
1%
2 EMPTY MEMORY CONTROLLER A, DECOUPLING 2 EMPTY MEMORY CONTROLLER B, DECOUPLING
402
MB_VREF0 402
MA_VREF0
1 R6T4 1 R6T1
NEED NEW VREF RESISTORS 1.27 KOHM C6T27 C6T10 C6T32 C6T29 1.27 KOHM C6R27 C6R11 C6R16 C6T30 C6R23 C6R46
1% 0.1 UF 0.1 UF 0.1 UF 1% 0.1 UF 0.1 UF 0.1 UF 4.7 UF 0.1 UF 0.1 UF
0.1 UF 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 EMPTY 10% 6.3 V 6.3 V 6.3 V 2 EMPTY 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 6.3 V X5R X5R X5R 402 X5R X5R X5R X5R X5R X5R
X5R 402 402 402 402 402 402 603 402 402
402
A A
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE

R6T4, R6T1, R5T3, R5T4
MEM VREF RESISTOR VALUE N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU, MEMORY CONTROLLER 1 PARTITION C & D
U5E1 2 OF 17 IC U5E1 1 OF 17 IC
19 18 BI MC_DQ31 AP15 MC_DQ31 21 20 BI MD_DQ31 AM23 MD_DQ31
D 19 18 BI MC_DQ30
MC_DQ29
AM15
AN15
MC_DQ30 21 20 BI MD_DQ30
MD_DQ29
AL23
AP23
MD_DQ30 D
19 18 BI MC_DQ29 21 20 BI MD_DQ29
19 18 BI MC_DQ28 AL15 MC_DQ28 21 20 BI MD_DQ28 AP24 MD_DQ28
19 18 BI MC_DQ27 AL13 MC_DQ27 21 20 BI MD_DQ27 AP22 MD_DQ27
19 18 BI MC_DQ26 AN16 MC_DQ26 21 20 BI MD_DQ26 AN25 MD_DQ26
19 18 BI MC_DQ25 AM13 MC_DQ25 21 20 BI MD_DQ25 AN21 MD_DQ25
19 18 BI MC_DQ24 AP17 MC_DQ24 21 20 BI MD_DQ24 AP25 MD_DQ24
19 18 OUT MC_WDQS3 AP16 MC_WDQS3 21 20 OUT MD_WDQS3 AN24 MD_WDQS3
19 18 IN MC_RDQS3 AN14 MC_RDQS3 21 20 IN MD_RDQS3 AN23 MD_RDQS3
19 18 OUT MC_DM3 AP14 MC_DM3 21 20 OUT MD_DM3 AN22 MD_DM3
19 18 BI MC_DQ23 AP11 MC_DQ23 MC_CLK1_DP AP9 MC_CLK1_DP OUT 19 21 20 BI MD_DQ23 AN19 MD_DQ23 MD_CLK1_DP AJ24 MD_CLK1_DP OUT 21
19 18 BI MC_DQ22 AL10 MC_DQ22 MC_CLK1_DN AP8 MC_CLK1_DN OUT 19 21 20 BI MD_DQ22 AP19 MD_DQ22 MD_CLK1_DN AK24 MD_CLK1_DN OUT 21
19 18 BI MC_DQ21 AN11 MC_DQ21 MC_CLK0_DP AP6 MC_CLK0_DP OUT 18 21 20 BI MD_DQ21 AN20 MD_DQ21 MD_CLK0_DP AL25 MD_CLK0_DP OUT 20
19 18 BI MC_DQ20 AM10 MC_DQ20 MC_CLK0_DN AP5 MC_CLK0_DN OUT 18 21 20 BI MD_DQ20 AL18 MD_DQ20 MD_CLK0_DN AM25 MD_CLK0_DN OUT 20
19 18 BI MC_DQ19 AN13 MC_DQ19 21 20 BI MD_DQ19 AL20 MD_DQ19
19 18 BI MC_DQ18 AN10 MC_DQ18 MC_A12 AE1 MC_A<11..0> 21 20 BI MD_DQ18 AP18 MD_DQ18 MD_A12 AK30
MD_A<11..0>
MC_DQ17 AP13 AH1 11 OUT 18 19 MD_DQ17 AP21 AN31 11 OUT 20 21
19 18 BI MC_DQ17 MC_A11 21 20 BI MD_DQ17 MD_A11
19 18 BI MC_DQ16 AN9 MC_DQ16 MC_A10 AE2 10 21 20 BI MD_DQ16 AN18 MD_DQ16 MD_A10 AN32 10
19 18 OUT MC_WDQS2 AP10 MC_WDQS2 MC_A9 AJ2 9 21 20 OUT MD_WDQS2 AM18 MD_WDQS2 MD_A9 AK26 9
19 18 IN MC_RDQS2 AP12 MC_RDQS2 MC_A8 AP4 8 21 20 IN MD_RDQS2 AP20 MD_RDQS2 MD_A8 AK25 8
19 18 OUT MC_DM2 AN12 MC_DM2 MC_A7 AK1 7 21 20 OUT MD_DM2 AM20 MD_DM2 MD_A7 AN26 7
MC_A6 AL1 6 MD_A6 AH26 6
MC_DQ15 AJ9 AP3 5 MD_DQ15 AJ19 AH25 5
C 19
19
18
18
BI
BI MC_DQ14 AJ13
MC_DQ15
MC_DQ14
MC_A5
MC_A4 AK2 4
21 20
21 20
BI
BI MD_DQ14 AH23
MD_DQ15
MD_DQ14
MD_A5
MD_A4 AN27 4 C
19 18 BI MC_DQ13 AK9 MC_DQ13 MC_A3 AJ1 3 21 20 BI MD_DQ13 AK19 MD_DQ13 MD_A3 AP32 3
19 18 13 BI MC_DQ12 AH13 MC_DQ12 MC_A2 AH2 2 21 20 13 BI MD_DQ12 AJ23 MD_DQ12 MD_A2 AN29 2
19 18 BI MC_DQ11 AK11 MC_DQ11 MC_A1 AF1 1 21 20 BI MD_DQ11 AK21 MD_DQ11 MD_A1 AM32 1
19 18 BI MC_DQ10 AK12 MC_DQ10 MC_A0 AG2 0 21 20 BI MD_DQ10 AK22 MD_DQ10 MD_A0 AN30 0
19 18 BI MC_DQ9 AH11 MC_DQ9 MC_BA<2..0> 21 20 BI MD_DQ9 AH21 MD_DQ9 MD_BA<2..0>
MC_DQ8 AM12 AL2 2 OUT 18 19 MD_DQ8 AM22 AK27 2 OUT 20 21
19 18 BI MC_DQ8 MC_BA2 21 20 BI MD_DQ8 MD_BA2
19 18 13 OUT MC_WDQS1 AH12 MC_WDQS1 MC_BA1 AM1 1 21 20 13 OUT MD_WDQS1 AH22 MD_WDQS1 MD_BA1 AN28 1
19 18 IN MC_RDQS1 AK10 MC_RDQS1 MC_BA0 AF2 0 21 20 IN MD_RDQS1 AK20 MD_RDQS1 MD_BA0 AK29 0
19 18 OUT MC_DM1 AH10 MC_DM1 21 20 OUT MD_DM1 AH20 MD_DM1
MC_CKE AG1 MC_CKE OUT 18 19 MD_CKE AP30 MD_CKE OUT 20 21
19 18 BI MC_DQ7 AN8 MC_DQ7 MC_WE_N* AH5 MC_WE_N OUT 18 19 21 20 BI MD_DQ7 AH18 MD_DQ7 MD_WE_N* AP28 MD_WE_N OUT 20 21
19 18 BI MC_DQ6 AN2 MC_DQ6 MC_CAS_N* AG5 MC_CAS_N OUT 18 19 21 20 BI MD_DQ6 AJ14 MD_DQ6 MD_CAS_N* AP29 MD_CAS_N OUT 20 21
19 18 BI MC_DQ5 AK8 MC_DQ5 MC_RAS_N* AF5 MC_RAS_N OUT 18 19 21 20 BI MD_DQ5 AJ18 MD_DQ5 MD_RAS_N* AP31 MD_RAS_N OUT 20 21
19 18 13 BI MC_DQ4 AN3 MC_DQ4 MC_CS1_N* AJ5 MC_CS1_N OUT 18 19 21 20 BI MD_DQ4 AK14 MD_DQ4 MD_CS1_N* AK28 MD_CS1_N OUT 20 21
19 18 BI MC_DQ3 AN6 MC_DQ3 MC_CS0_N* AM2 MC_CS0_N OUT 18 21 20 BI MD_DQ3 AM17 MD_DQ3 MD_CS0_N* AP27 MD_CS0_N OUT 20
19 18 BI MC_DQ2 AK5 MC_DQ2 21 20 BI MD_DQ2 AK15 MD_DQ2
19 18 BI MC_DQ1 AK6 MC_DQ1 21 20 BI MD_DQ1 AK16 MD_DQ1
19 18 BI MC_DQ0 AN5 MC_DQ0 21 20 BI MD_DQ0 AH16 MD_DQ0
19 18 13 OUT MC_WDQS0 AN4 MC_WDQS0 21 20 OUT MD_WDQS0 AH15 MD_WDQS0
19 18 IN MC_RDQS0 AK7 MC_RDQS0 21 20 IN MD_RDQS0 AK17 MD_RDQS0
19 18 OUT MC_DM0 AN7 MC_DM0 21 20 OUT MD_DM0 AH17 MD_DM0
B MC_WDQS1
R5T7
1 2 B
19 18 13 OUT R6T9
AE5 MC_VREF0 4.75 KOHM 1% AN17 MD_VREF0 21 20 13 OUT MD_WDQS1 1 2
402 CH 4.75 KOHM 1%
X818336-001 BGA_2 19 18 13 BI MC_DQ12 X818336-001 BGA_2 402 CH
21 20 13 BI MD_DQ12
R5T6 V_MEM
19 18 13 BI MC_DQ4 1 2
4.75 KOHM 1% MEMORY CONTROLLER D, DECOUPLING
402 CH
V_MEM 19 18 13 OUT MC_WDQS0 V_MEM
1 C5T48 1 C5T39 1 C6T31 1 C5T38
2 R5T2 V_MEM 1 R5T5 0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
549 OHM 549 OHM
1%
MEMORY CONTROLLER C, DECOUPLING 1% 2 6.3 V
X5R 2 6.3 V
X5R 2 6.3 V
X5R 2 6.3
X5R
V
1 EMPTY 2 EMPTY 402 402 402 402
402 402
MC_VREF0
MD_VREF0
1 R5T3 1 C5U2 1 C5T37 1 C5T41 1 C6T28 1 C5T49
1.27 KOHM 0.1 UF 0.1 UF 0.1 UF
1% 4.7 UF 0.1 UF 10% 10% 10% 1 R5T4
NEED TO VREF RESISTOR VALUES 10% 10% 6.3 V 6.3 V
2 EMPTY 2 6.3 V
2 6.3 V 2 X5R 2 X5R 2 6.3
X5R
V 1.27 KOHM
1%
402 X5R X5R 402 402 402 1 C6T26 1 C5T42 1 C5T45 1 C5T44
603 402 2 EMPTY
402 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 6.3
X5R
V
A 402 402 402 402 A

1 C5T50 1 C5T46 1 C6T33 1 C5T47
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
R6T4, R6T1, R5T3, R5T4 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
402 402 402 402
GPU MEM VREF RESISTOR VALUE
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
72% 1.40KOHM
73% 1.47KOHM
74% 1.54KOHM
DRAWING
[PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Thu Feb 17 10:12:19 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION A, TOP
CHIP SELECT = 0, MIRROR FUNCTION = 0
V_MEM
D D
1 R7E5 1 R7E4
60.4 OHM 60.4 OHM
1% 1% V_MEM
2 CH
402 2 CH
402
U7E1 IC
U7E1 IC
GDDR136 (1Gbit) GDDR136 (1Gbit)
V1 VDDQ<21> MF=0
12 IN MA_CLK0_DP J11 CLK_DP MF=1 DQ31 T3 MA_DQ31 BI 12 15 R12
MA_CLK0_DN J10 T2 MA_DQ30 VDDQ<20>
12 IN CLK_DN DQ30 BI 12 15 R9 VDDQ<19> T12
MEM_RST V9 R3 MA_DQ29 VSSQ<19>
4 IN RESET DQ29 BI 12 15 R4 T9
R2 MA_DQ28 VDDQ<18> VSSQ<18>
DQ28 BI 12 15 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MA_DQ27 BI 12 15 N12 T1
N2 MA_DQ26 VDDQ<16> VSSQ<16>
DQ26 BI 12 15 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MA_DQ25 BI 12 15 V12 P9
M2 MA_DQ24 VDDQ<14> VSSQ<14>
DQ24 BI 12 15 N4 VDDQ<13> VSSQ<13> P4
WDQS3 P2 MA_WDQS3 IN 12 N1 P1
P3 MA_RDQS3 VDDQ<12> VSSQ<12>
RDQS3 OUT 15 12 J9 VSSQ<11> L11
N3 MA_DM3 VDDQ<11>
DM3 IN 12 J4 VDDQ<10> VSSQ<10> L2
E12 VDDQ<9> VSSQ<9> G11
MA_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MA_DQ23 BI 12 15 E9 G2
12 IN 11 L4 T11 MA_DQ22 VDDQ<8> VSSQ<8>
A11/A7 DQ22 BI 12 15 E4 VDDQ<7> D12
10 K2 R10 MA_DQ21 VSSQ<7>
C 9 M9
A10/A8
A9/A3
DQ21
DQ20 R11 MA_DQ20 BI
BI
12 15
12 15
E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
8 K11 M10 MA_DQ19 VDDQ<5> VSSQ<5>
A8/A10 DQ19 BI 12 15 C9 VDDQ<4> D1
7 L9 N11 MA_DQ18 VSSQ<4>
A7/A11 DQ18 BI 12 15 C4 VDDQ<3> B12
6 K10 L10 MA_DQ17 VSSQ<3>
A6/A2 DQ17 BI 12 15 C1 VDDQ<2> B9
5 H11 M11 MA_DQ16 VSSQ<2>
A5/A1 DQ16 BI 12 15 A12 VDDQ<1> B4
4 K9 P11 MA_WDQS2 VSSQ<1>
A4/A0 WDQS2 IN 12 A1 VDDQ<0> B1
3 M4 P10 MA_RDQS2 VSSQ<0>
A3/A9 RDQS2 OUT 15 12
2 K3 A2/A6 DM2 N10 MA_DM2 IN 12 V2 V3
1 H2 VDD<7> VSS<7>
A1/A5 M12 VDD<6> L12
0 K4 G10 MA_DQ15 VSS<6>
A0/A4 DQ15 BI 12 15 M1 VDD<5> L1
F11 MA_DQ14 VSS<5>
MA_BA<2..0> DQ14 BI 12 15 V11 VDD<4> VSS<4> G12
12 IN 2 H10 F10 MA_DQ13
BA2/RAS_N DQ13 BI 12 15 F12 VDD<3> G1
1 G9 E11 MA_DQ12 VSS<3>
BA1/BA0 DQ12 BI 12 15 F1 VDD<2> A10
0 G4 C10 MA_DQ11 VSS<2>
BA0/BA1 DQ11 BI 12 15 A11 VDD<1> V10
C11 MA_DQ10 VSS<1>
DQ10 BI 12 15 A2 VDD<0> VSS<0> A3
12 IN MA_CKE H4 CKE/WE_N DQ9 B10 MA_DQ9 BI 12 15
12 IN MA_WE_N H9 WE_N/CKE DQ8 B11 MA_DQ8 BI 12 15 K12
MA_CAS_N F4 D11 MA_WDQS1 VDDA<1>
12 IN CAS_N/CS_N WDQS1 IN 12 K1 VDDA<0>
12 IN MA_RAS_N H3 RAS_N/BA2 RDQS1 D10 MA_RDQS1 OUT 15 12
12 IN MA_CS0_N F9 CS_N/CAS_N DM1 E10 MA_DM1 IN 12 J12
MA_CS1_N J3 VSSA<1>
12 IN CS1_N (1Gbit only, single-load) J1 VSSA<0>
4 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MA_DQ7 BI 12 15
B MEM_SCAN_EN V4
DQ6 F2
F3
MA_DQ6
MA_DQ5 BI 12 15
B
4 IN SCAN_EN DQ5 BI 12 15
E2 MA_DQ4 X802980-019
DQ4 BI 12 15
14 IN MEM_A_VREF1 H1 VREF1 DQ3 C3 MA_DQ3 BI 12 15
DQ1 B3 MA_DQ1 BI 12 15
WDQS0 D2 MA_WDQS0 IN 12
D3 MA_RDQS0 MX_CS1_N CONNECTED
RDQS0 OUT 15 12
TO J3 TO SUPPORT 1G
DM0 E3 MA_DM0 IN 12
RAM CONFIGS.
ZQ A4 MA_ZQ_TOP
V_MEM 1 R7E8
243 OHM
X802980-019 1%
2 CH
402
1 R7T5
549 OHM PARTITION A DECOUPLING
1% V_MEM V_MEM
2 CH MEMORY A, TOP, DECOUPLING
402
MEM_A_VREF1 OUT 14 15
1 C7E8
4.7 UF C7E14 C7E11 C7E6 C7E5 C7E13 C7E10 C7E4 C7E7
10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1 R7T4 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
1.27 KOHM 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1% C7T7 603 X5R X5R X5R X5R X5R X5R X5R X5R
2 CH 0.1 UF 402 402 402 402 402 402 402 402
10%
A 402 6.3 V
X5R
TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE A
402 R7T4, R7E7, R7R4, R7D5, R5U4, R5F2, R6U4, R6F2
MEM VREF RESISTOR VALUE

69% 1.21KOHM
70% 1.27KOHM
72% 1.40KOHM
THESE ARE THE MEM VREFS NEEDED

DRAWING
[PAGE_TITLE=MEMORY PARTITION A, TOP] Thu Feb 17 10:12:21 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEM
MEMORY PARTITION A, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1
D D
1 R7T3 1 R7T2
60.4 OHM 60.4 OHM
1% 1%
2 CH 2 CH U7T1 EMPTY
402 402 V_MEM
GDDR136 (1Gbit)
12 IN MA_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MA_DQ23 BI 12 14 U7T1 EMPTY
12 IN MA_CLK1_DN J10 CLK_DN DQ30 T2 MA_DQ22 BI 12 14
4 MEM_RST V9 RESET DQ29 R3 MA_DQ21 12 14
GDDR136 (1Gbit)
IN R2 MA_DQ20 BI V1 VDDQ<21> MF=0
DQ28 BI 12 14 R12 VDDQ<20>
DQ27 M3 MA_DQ19 BI 12 14 R9 T12
N2 MA_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 12 14 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MA_DQ17 BI 12 14 R1 T4
M2 MA_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 12 14 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MA_WDQS2 IN 12 N9 P12
P3 MA_RDQS2 VDDQ<15> VSSQ<15>
RDQS3 OUT 14 12 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MA_DM2 IN 12 N4 P4
VDDQ<13> VSSQ<13>
N1 VDDQ<12> VSSQ<12> P1
MA_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MA_DQ31 BI 12 14 J9 L11
12 IN 11 L9 T11 MA_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 12 14 J4 L2
10 K11 R10 MA_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 12 14 E12 G11
C 9
8
M4
K2
A3/A9 DQ20 R11
M10
MA_DQ28
MA_DQ27 BI 12 14 E9
VDDQ<9>
VDDQ<8>
VSSQ<9>
VSSQ<8> G2 C
A10/A8 DQ19 BI 12 14 E4 D12
7 L4 N11 MA_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 12 14 E1 D9
6 K3 L10 MA_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 12 14 C12 VDDQ<5> D4
5 H2 M11 MA_DQ24 VSSQ<5>
A1/A5 DQ16 BI 12 14 C9 VDDQ<4> D1
4 K4 P11 MA_WDQS3 VSSQ<4>
A0/A4 WDQS2 IN 12 C4 VDDQ<3> B12
3 M9 P10 MA_RDQS3 VSSQ<3>
A9/A3 RDQS2 OUT 14 12 C1 VDDQ<2> B9
2 K10 N10 MA_DM3 VSSQ<2>
A6/A2 DM2 IN 12 A12 VDDQ<1> B4
1 H11 VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MA_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 12 14
MA_BA<2..0> DQ14 F11 MA_DQ6 BI 12 14 V2 V3
12 IN 2 H3 F10 MA_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 12 14 M12 L12
1 G4 E11 MA_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 12 14 M1 L1
0 G9 C10 MA_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 12 14 V11 G12
C11 MA_DQ2 VDD<4> VSS<4>
DQ10 BI 12 14 F12 VDD<3> VSS<3> G1
12 IN MA_CKE H9 WE_N/CKE DQ9 B10 MA_DQ1 BI 12 14 F1 A10
MA_WE_N H4 B11 MA_DQ0 VDD<2> VSS<2>
12 IN CKE/WE_N DQ8 BI 12 14 A11 VDD<1> V10
MA_CAS_N F9 D11 MA_WDQS0 VSS<1>
12 IN CS_N/CAS_N WDQS1 IN 12 A2 VDD<0> A3
MA_RAS_N H10 D10 MA_RDQS0 VSS<0>
12 IN BA2/RAS_N RDQS1 OUT 14 12
12 IN MA_CS1_N F4 CAS_N/CS_N DM1 E10 MA_DM0 IN 12 K12
J3 VDDA<1>
CS1_N (1Gbit only, single-load) K1 VDDA<0>
4 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MA_DQ15 BI 12 14
F2 MA_DQ14
B 4 IN MEM_SCAN_EN V4 SCAN_EN
DQ6
DQ5 F3 MA_DQ13 BI
BI
12 14
12 14
J12
J1
VSSA<1>
B
E2 MA_DQ12 VSSA<0>
DQ4 BI 12 14
B3 MA_DQ9 X802980-019
DQ1 BI 12 14
WDQS0 D2 MA_WDQS1 IN 12
RDQS0 D3 MA_RDQS1 OUT 14 12
DM0 E3 MA_DM1 IN 12
ZQ A4 MA_ZQ_BOT
1 R7T6
243 OHM
X802980-019 1%
V_MEM 2 CH
402
1 R7E6 V_MEM
549 OHM
1%
2 CH MEMORY A, BOTTOM, DECOUPLING
402
MEM_A_VREF0 OUT 14 15
1 R7E7 C7T12 C7T9 C7T5 C7T4 C7T11 C7T8 C7T3 C7T6

1.27 KOHM 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1% C7E9 10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
2 CH 0.1 UF
A 402
10%
6.3 V
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402 A
X5R
402

DRAWING
[PAGE_TITLE=MEMORY PARTITION A, BOTTOM] Thu Feb 17 10:12:21 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION B, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0
V_MEM
D D
1 R7D3 1 R7D2 V_MEM

60.4 OHM 60.4 OHM
1% 1%
U7D1 IC
2 CH 2 CH
402 402 GDDR136 (1Gbit)
U7D1 IC V1 VDDQ<21> MF=0
R12 VDDQ<20>
GDDR136 (1Gbit) R9 VDDQ<19> VSSQ<19> T12
12 IN MB_CLK0_DP J11 CLK_DP MF=1 DQ31 T3 MB_DQ31 BI 12 17 R4 T9
MB_CLK0_DN J10 T2 MB_DQ30 VDDQ<18> VSSQ<18>
12 IN CLK_DN DQ30 BI 12 17 R1 VDDQ<17> T4
MEM_RST V9 R3 MB_DQ29 VSSQ<17>
4 IN RESET DQ29 BI 12 17 N12 T1
R2 MB_DQ28 VDDQ<16> VSSQ<16>
DQ28 BI 12 17 N9 VDDQ<15> VSSQ<15> P12
DQ27 M3 MB_DQ27 BI 12 17 V12 P9
N2 MB_DQ26 VDDQ<14> VSSQ<14>
DQ26 BI 12 17 N4 VDDQ<13> VSSQ<13> P4
DQ25 L3 MB_DQ25 BI 12 17 N1 P1
M2 MB_DQ24 VDDQ<12> VSSQ<12>
DQ24 BI 12 17 J9 VSSQ<11> L11
P2 MB_WDQS3 VDDQ<11>
WDQS3 IN 12 J4 VDDQ<10> VSSQ<10> L2
RDQS3 P3 MB_RDQS3 OUT 17 12 E12 G11
N3 MB_DM3 VDDQ<9> VSSQ<9>
DM3 IN 12 E9 VDDQ<8> VSSQ<8> G2
E4 VDDQ<7> VSSQ<7> D12
J2 T10 MB_DQ23
C 12 IN MB_A<11..0> 11 L4
A12 (1Gbit only, dual-load)
A11/A7
DQ23
DQ22 T11 MB_DQ22 BI
BI
12 17
12 17
E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
10 K2 R10 MB_DQ21 VDDQ<5> VSSQ<5>
A10/A8 DQ21 BI 12 17 C9 VDDQ<4> D1
9 M9 R11 MB_DQ20 VSSQ<4>
A9/A3 DQ20 BI 12 17 C4 VDDQ<3> B12
8 K11 M10 MB_DQ19 VSSQ<3>
A8/A10 DQ19 BI 12 17 C1 VDDQ<2> B9
7 L9 N11 MB_DQ18 VSSQ<2>
A7/A11 DQ18 BI 12 17 A12 VDDQ<1> B4
6 K10 L10 MB_DQ17 VSSQ<1>
A6/A2 DQ17 BI 12 17 A1 VDDQ<0> B1
5 H11 M11 MB_DQ16 VSSQ<0>
A5/A1 DQ16 BI 12 17
4 K9 A4/A0 WDQS2 P11 MB_WDQS2 IN 12 V2 V3
3 M4 P10 MB_RDQS2 VDD<7> VSS<7>
A3/A9 RDQS2 OUT 17 12 M12 VDD<6> L12
2 K3 N10 MB_DM2 VSS<6>
A2/A6 DM2 IN 12 M1 VDD<5> L1
1 H2 VSS<5>
A1/A5 V11 VDD<4> G12
0 K4 G10 MB_DQ15 VSS<4>
A0/A4 DQ15 BI 12 17 F12 VDD<3> G1
F11 MB_DQ14 VSS<3>
MB_BA<2..0> DQ14 BI 12 17 F1 VDD<2> VSS<2> A10
12 IN 2 H10 F10 MB_DQ13
BA2/RAS_N DQ13 BI 12 17 A11 VDD<1> V10
1 G9 E11 MB_DQ12 VSS<1>
BA1/BA0 DQ12 BI 12 17 A2 VDD<0> A3
0 G4 C10 MB_DQ11 VSS<0>
BA0/BA1 DQ11 BI 12 17
DQ10 C11 MB_DQ10 BI 12 17 K12
MB_CKE H4 B10 MB_DQ9 VDDA<1>
12 IN CKE/WE_N DQ9 BI 12 17 K1 VDDA<0>
12 IN MB_WE_N H9 WE_N/CKE DQ8 B11 MB_DQ8 BI 12 17
12 IN MB_CAS_N F4 CAS_N/CS_N WDQS1 D11 MB_WDQS1 IN 12 J12
MB_RAS_N H3 D10 MB_RDQS1 VSSA<1>
12 IN RAS_N/BA2 RDQS1 OUT 17 12 J1 VSSA<0>
12 IN MB_CS0_N F9 CS_N/CAS_N DM1 E10 MB_DM1 IN 12
B 12 IN MB_CS1_N
MEM_SCAN_TOP_EN
J3
A9
CS1_N (1Gbit only, single-load)
G3 MB_DQ7 B
4 IN MF DQ7 BI 12 17
F2 MB_DQ6 X802980-019
DQ6 BI 12 17
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MB_DQ5 BI 12 17
DQ4 E2 MB_DQ4 BI 12 17
16 IN MEM_B_VREF1 H1 VREF1 DQ3 C3 MB_DQ3 BI 12 17
DQ1 B3 MB_DQ1 BI 12 17
WDQS0 D2 MB_WDQS0 IN 12
RDQS0 D3 MB_RDQS0 OUT 17 12
DM0 E3 MB_DM0 IN 12
ZQ A4 MB_ZQ_TOP
V_MEM 1 R7E1
243 OHM
X802980-019 1%
2 CH
402
1 R7R2
549 OHM PARTITION B DECOUPLING
1%
2 CH
402
MEM_B_VREF1 OUT 16 17
V_MEM V_MEM
MEMORY B, TOP, DECOUPLING
1 R7R4
1.27 KOHM C7R6
1%
A 2 CH
0.1 UF
10%
1 C7D11 A
402 6.3 V 4.7 UF C7D13 C7D9 C7E3 C7E2 C7D14 C7D10 C7D7 C7D8
X5R 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
402 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402

DRAWING
[PAGE_TITLE=MEMORY PARITION B, TOP] Thu Feb 17 10:12:22 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION B, BOTTOM
D D
V_MEM
1 R7R1 1 R7R3
60.4 OHM 60.4 OHM
1% 1%
U7R1 EMPTY
2 CH 2 CH V_MEM
402 402 GDDR136 (1Gbit)
12 IN MB_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MB_DQ23 BI 12 16 U7R1 EMPTY
12 IN MB_CLK1_DN J10 CLK_DN DQ30 T2 MB_DQ22 BI 12 16
4 MEM_RST V9 RESET DQ29 R3 MB_DQ21 12 16
GDDR136 (1Gbit)
IN R2 MB_DQ20 BI V1 VDDQ<21> MF=0
DQ28 BI 12 16 R12 VDDQ<20>
DQ27 M3 MB_DQ19 BI 12 16 R9 T12
N2 MB_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 12 16 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MB_DQ17 BI 12 16 R1 T4
M2 MB_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 12 16 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MB_WDQS2 IN 12 N9 P12
P3 MB_RDQS2 VDDQ<15> VSSQ<15>
RDQS3 OUT 16 12 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MB_DM2 IN 12 N4 P4
VDDQ<13> VSSQ<13>
N1 P1
C 12 IN MB_A<11..0> 11
J2
L9
A12 (1Gbit only, dual-load) DQ23 T10
T11
MB_DQ31
MB_DQ30 BI 12 16 J9
VDDQ<12>
VDDQ<11>
VSSQ<12>
VSSQ<11> L11 C
A7/A11 DQ22 BI 12 16 J4 L2
10 K11 R10 MB_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 12 16 E12 G11
9 M4 R11 MB_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 12 16 E9 G2
8 K2 M10 MB_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 12 16 E4 D12
7 L4 N11 MB_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 12 16 E1 D9
6 K3 L10 MB_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 12 16 C12 VDDQ<5> D4
5 H2 M11 MB_DQ24 VSSQ<5>
A1/A5 DQ16 BI 12 16 C9 VDDQ<4> D1
4 K4 P11 MB_WDQS3 VSSQ<4>
A0/A4 WDQS2 IN 12 C4 VDDQ<3> B12
3 M9 P10 MB_RDQS3 VSSQ<3>
A9/A3 RDQS2 OUT 16 12 C1 VDDQ<2> B9
2 K10 N10 MB_DM3 VSSQ<2>
A6/A2 DM2 IN 12 A12 VDDQ<1> B4
1 H11 VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MB_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 12 16
MB_BA<2..0> DQ14 F11 MB_DQ6 BI 12 16 V2 V3
12 IN 2 H3 F10 MB_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 12 16 M12 L12
1 G4 E11 MB_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 12 16 M1 L1
0 G9 C10 MB_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 12 16 V11 G12
C11 MB_DQ2 VDD<4> VSS<4>
DQ10 BI 12 16 F12 VDD<3> VSS<3> G1
12 IN MB_CKE H9 WE_N/CKE DQ9 B10 MB_DQ1 BI 12 16 F1 A10
MB_WE_N H4 B11 MB_DQ0 VDD<2> VSS<2>
12 IN CKE/WE_N DQ8 BI 12 16 A11 VDD<1> V10
MB_CAS_N F9 D11 MB_WDQS0 VSS<1>
12 IN CS_N/CAS_N WDQS1 IN 12 A2 VDD<0> A3
MB_RAS_N H10 D10 MB_RDQS0 VSS<0>
12 IN BA2/RAS_N RDQS1 OUT 16 12
MB_CS1_N F4 E10 MB_DM0
B 12 IN J3
CAS_N/CS_N
CS1_N (1Gbit only, single-load)
DM1 IN 12 K12
K1
VDDA<1>
B
MEM_SCAN_BOT_EN A9 G3 MB_DQ15 VDDA<0>
4 IN MF DQ7 BI 12 16
DQ6 F2 MB_DQ14 BI 12 16 J12
MEM_SCAN_EN V4 F3 MB_DQ13 VSSA<1>
4 IN SCAN_EN DQ5 BI 12 16 J1 VSSA<0>
DQ4 E2 MB_DQ12 BI 12 16
B3 MB_DQ9 X802980-019
DQ1 BI 12 16
WDQS0 D2 MB_WDQS1 IN 12
RDQS0 D3 MB_RDQS1 OUT 16 12
DM0 E3 MB_DM1 IN 12
ZQ A4 MB_ZQ_BOT
V_MEM 1 R7T1
243 OHM
X802980-019 1%
2 CH
1 R7D4 402
549 OHM
1% V_MEM
2 CH
402
MEM_B_VREF0 16 17
MEMORY B, BOTTOM, DECOUPLING
OUT
1 R7D5
1.27 KOHM C7R7 C7R4 C7T2 C7T1 C7R8 C7R5 C7R2 C7R3
1% C7D12 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
A 2 CH 0.1 UF
10%
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
A
402 6.3 V X5R X5R X5R X5R X5R X5R X5R X5R
X5R 402 402 402 402 402 402 402 402
402

[PAGE_TITLE=MEMORY PARITION B, BOTTOM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION C, TOP
V_MEM
D D
1 R5F4 1 R5F3
60.4 OHM 60.4 OHM V_MEM
1% 1%
2 CH 2 CH U5F1 IC
402 402 U5F1 IC
GDDR136 (1Gbit)
GDDR136 (1Gbit) V1 VDDQ<21> MF=0
13 IN MC_CLK0_DP J11 CLK_DP MF=1 DQ31 T3 MC_DQ31 BI 13 19 R12 VDDQ<20>
13 IN MC_CLK0_DN J10 CLK_DN DQ30 T2 MC_DQ30 BI 13 19 R9 VDDQ<19> VSSQ<19> T12
4 IN MEM_RST V9 RESET DQ29 R3 MC_DQ29 BI 13 19 R4 VDDQ<18> VSSQ<18> T9
DQ28 R2 MC_DQ28 BI 13 19 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MC_DQ27 BI 13 19 N12 VDDQ<16> VSSQ<16> T1
DQ26 N2 MC_DQ26 BI 13 19 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MC_DQ25 BI 13 19 V12 VDDQ<14> VSSQ<14> P9
DQ24 M2 MC_DQ24 BI 13 19 N4 VDDQ<13> VSSQ<13> P4
WDQS3 P2 MC_WDQS3 IN 13 N1 VDDQ<12> VSSQ<12> P1
RDQS3 P3 MC_RDQS3 OUT 19 13 J9 VDDQ<11> VSSQ<11> L11
DM3 N3 MC_DM3 IN 13 J4 VDDQ<10> VSSQ<10> L2
MC_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MC_DQ23 BI 13 19 E9 VDDQ<8> VSSQ<8> G2
13 IN 11 L4 T11 MC_DQ22 E4 D12
A11/A7 DQ22 BI 13 19 VDDQ<7> VSSQ<7>
C 10
9
K2
M9
A10/A8 DQ21 R10
R11
MC_DQ21
MC_DQ20 BI 13 19 E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
A9/A3 DQ20 BI 13 19 VDDQ<5> VSSQ<5>
8 K11 A8/A10 DQ19 M10 MC_DQ19 BI 13 19 C9 VDDQ<4> VSSQ<4> D1
7 L9 A7/A11 DQ18 N11 MC_DQ18 BI 13 19 C4 VDDQ<3> VSSQ<3> B12
6 K10 A6/A2 DQ17 L10 MC_DQ17 BI 13 19 C1 VDDQ<2> VSSQ<2> B9
5 H11 A5/A1 DQ16 M11 MC_DQ16 BI 13 19 A12 VDDQ<1> VSSQ<1> B4
4 K9 A4/A0 WDQS2 P11 MC_WDQS2 IN 13 A1 VDDQ<0> VSSQ<0> B1
3 M4 A3/A9 RDQS2 P10 MC_RDQS2 OUT 19 13
2 K3 A2/A6 DM2 N10 MC_DM2 IN 13 V2 VDD<7> VSS<7> V3
1 H2 A1/A5 M12 VDD<6> VSS<6> L12
0 K4 A0/A4 DQ15 G10 MC_DQ15 BI 13 19 M1 VDD<5> VSS<5> L1
MC_BA<2..0> DQ14 F11 MC_DQ14 BI 13 19 V11 VDD<4> VSS<4> G12
13 IN 2 H10 F10 MC_DQ13 F12 G1
BA2/RAS_N DQ13 BI 13 19 VDD<3> VSS<3>
1 G9 BA1/BA0 DQ12 E11 MC_DQ12 BI 13 19 F1 VDD<2> VSS<2> A10
0 G4 BA0/BA1 DQ11 C10 MC_DQ11 BI 13 19 A11 VDD<1> VSS<1> V10
DQ10 C11 MC_DQ10 BI 13 19 A2 VDD<0> VSS<0> A3
13 IN MC_CKE H4 CKE/WE_N DQ9 B10 MC_DQ9 BI 13 19
13 IN MC_WE_N H9 WE_N/CKE DQ8 B11 MC_DQ8 BI 13 19 K12 VDDA<1>
13 IN MC_CAS_N F4 CAS_N/CS_N WDQS1 D11 MC_WDQS1 IN 13 K1 VDDA<0>
13 IN MC_RAS_N H3 RAS_N/BA2 RDQS1 D10 MC_RDQS1 OUT 19 13
13 IN MC_CS0_N F9 CS_N/CAS_N DM1 E10 MC_DM1 IN 13 J12 VSSA<1>
13 IN MC_CS1_N J3 CS1_N (1Gbit only, single-load) J1 VSSA<0>
MEM_SCAN_TOP_EN A9 G3 MC_DQ7
B 4 IN MF DQ7
DQ6 F2 MC_DQ6 BI
BI
13 19
13 19 B
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ5 BI 13 19 X802980-019
DQ4 E2 MC_DQ4 BI 13 19
18 IN MEM_C_VREF1 H1 VREF1 DQ3 C3 MC_DQ3 BI 13 19
DQ1 B3 MC_DQ1 BI 13 19
WDQS0 D2 MC_WDQS0 IN 13
RDQS0 D3 MC_RDQS0 OUT 19 13
DM0 E3 MC_DM0 IN 13
ZQ A4 MC_ZQ_TOP
1 R5F5
243 OHM
X802980-019 1%
V_MEM 2 CH
402
1 R5U5
549 OHM
1%
2 CH MC_CLK0
402 MEM_C_VREF1 OUT 18 19
STITCHING CAP PARTITION C DECOUPLING V_MEM
1 R5U4 V_MEM V_MEM
C5U9 MEMORY C, TOP, DECOUPLING
1.27 KOHM 0.1 UF
1% 10%
A 2 CH 6.3 V
X5R
A
402 402 1 C5U1
0.1 UF 1 C5F10 C6F10 C6F8 C6F4 C6F1 C6F2 C6F5 C6F7 C6F9
10% 4.7 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 2 X5R X5R X5R X5R X5R X5R X5R X5R X5R
603 402 402 402 402 402 402 402 402

[PAGE_TITLE=MEMORY PARTITION C, TOP] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION C, BOTTOM
V_MEM
D D
1 R5U3 1 R5U2
60.4 OHM 60.4 OHM
1% 1%
2 CH 2 CH
402 402
U5U1 EMPTY
V_MEM
GDDR136 (1Gbit) U5U1 EMPTY
13 IN MC_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MC_DQ23 BI 13 18
13 IN MC_CLK1_DN J10 CLK_DN DQ30 T2 MC_DQ22 BI 13 18 GDDR136 (1Gbit)
4 IN MEM_RST V9 RESET DQ29 R3 MC_DQ21 BI 13 18 V1 VDDQ<21> MF=0
DQ28 R2 MC_DQ20 BI 13 18 R12 VDDQ<20>
DQ27 M3 MC_DQ19 BI 13 18 R9 VDDQ<19> VSSQ<19> T12
DQ26 N2 MC_DQ18 BI 13 18 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MC_DQ17 BI 13 18 R1 VDDQ<17> VSSQ<17> T4
DQ24 M2 MC_DQ16 BI 13 18 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MC_WDQS2 IN 13 N9 VDDQ<15> VSSQ<15> P12
RDQS3 P3 MC_RDQS2 OUT 18 13 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MC_DM2 IN 13 N4 VDDQ<13> VSSQ<13> P4
MC_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MC_DQ31 BI 13 18 J9 VDDQ<11> VSSQ<11> L11
13 IN 11 L9 T11 MC_DQ30 J4 L2
C 10 K11
A7/A11
A8/A10
DQ22
DQ21 R10 MC_DQ29 BI
BI
13 18
13 18 E12
VDDQ<10>
VDDQ<9>
VSSQ<10>
VSSQ<9> G11 C
9 M4 A3/A9 DQ20 R11 MC_DQ28 BI 13 18 E9 VDDQ<8> VSSQ<8> G2
8 K2 A10/A8 DQ19 M10 MC_DQ27 BI 13 18 E4 VDDQ<7> VSSQ<7> D12
7 L4 A11/A7 DQ18 N11 MC_DQ26 BI 13 18 E1 VDDQ<6> VSSQ<6> D9
6 K3 A2/A6 DQ17 L10 MC_DQ25 BI 13 18 C12 VDDQ<5> VSSQ<5> D4
5 H2 A1/A5 DQ16 M11 MC_DQ24 BI 13 18 C9 VDDQ<4> VSSQ<4> D1
4 K4 A0/A4 WDQS2 P11 MC_WDQS3 IN 13 C4 VDDQ<3> VSSQ<3> B12
3 M9 A9/A3 RDQS2 P10 MC_RDQS3 OUT 18 13 C1 VDDQ<2> VSSQ<2> B9
2 K10 A6/A2 DM2 N10 MC_DM3 IN 13 A12 VDDQ<1> VSSQ<1> B4
1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> B1
0 K9 A4/A0 DQ15 G10 MC_DQ7 BI 13 18
MC_BA<2..0> DQ14 F11 MC_DQ6 BI 13 18 V2 VDD<7> VSS<7> V3
13 IN 2 H3 F10 MC_DQ5 M12 L12
RAS_N/BA2 DQ13 BI 13 18 VDD<6> VSS<6>
1 G4 BA0/BA1 DQ12 E11 MC_DQ4 BI 13 18 M1 VDD<5> VSS<5> L1
0 G9 BA1/BA0 DQ11 C10 MC_DQ3 BI 13 18 V11 VDD<4> VSS<4> G12
DQ10 C11 MC_DQ2 BI 13 18 F12 VDD<3> VSS<3> G1
13 IN MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 BI 13 18 F1 VDD<2> VSS<2> A10
13 IN MC_WE_N H4 CKE/WE_N DQ8 B11 MC_DQ0 BI 13 18 A11 VDD<1> VSS<1> V10
13 IN MC_CAS_N F9 CS_N/CAS_N WDQS1 D11 MC_WDQS0 IN 13 A2 VDD<0> VSS<0> A3
13 IN MC_RAS_N H10 BA2/RAS_N RDQS1 D10 MC_RDQS0 OUT 18 13
13 IN MC_CS1_N F4 CAS_N/CS_N DM1 E10 MC_DM0 IN 13 K12 VDDA<1>
J3 CS1_N (1Gbit only, single-load) K1 VDDA<0>
B 4 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3
F2
MC_DQ15
MC_DQ14 BI 13 18
J12 B
DQ6 BI 13 18 VSSA<1>
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ13 BI 13 18 J1 VSSA<0>
DQ4 E2 MC_DQ12 BI 13 18
18 IN MEM_C_VREF1 H12 VREF0 DQ2 C2 MC_DQ10 BI 13 18 X802980-019
WDQS0 D2 MC_WDQS1 IN 13
RDQS0 D3 MC_RDQS1 OUT 18 13
DM0 E3 MC_DM1 IN 13
ZQ A4 MC_ZQ_BOT
1 R5U1
V_MEM 243 OHM
X802980-019 1%
2 CH
402
1 R5F1 V_MEM
549 OHM MEMORY C, BOTTOM, DECOUPLING
1%
2 CH
402 MEM_C_VREF0 OUT 18 19
C6U9 C6U6 C6U3 C6U1 C6U2 C6U4 C6U5 C6U8

0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1 R5F2 10% 10% 10% 10% 10% 10% 10% 10%
1.27 KOHM 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1% C5F1 X5R X5R X5R X5R X5R X5R X5R X5R
0.1 UF 402 402 402 402 402 402 402 402
2 CH 10% A
A 402 6.3 V
X5R
402

[PAGE_TITLE=MEMORY PARITION C, BOTTOM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION D, TOP
V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0
1 R6F4 1 R6F3
D 60.4 OHM
1%
60.4 OHM
1%
D
2 CH 2 CH V_MEM
402 402
U6F1 IC
U6F1 IC GDDR136 (1Gbit)
V1 VDDQ<21> MF=0
GDDR136 (1Gbit) R12 VDDQ<20>
13 IN MD_CLK0_DP J11 CLK_DP MF=1 DQ31 T3 MD_DQ31 BI 13 21 R9 T12
MD_CLK0_DN J10 T2 MD_DQ30 VDDQ<19> VSSQ<19>
13 IN CLK_DN DQ30 BI 13 21 R4 T9
MEM_RST V9 R3 MD_DQ29 VDDQ<18> VSSQ<18>
4 IN RESET DQ29 BI 13 21 R1 VDDQ<17> T4
R2 MD_DQ28 VSSQ<17>
DQ28 BI 13 21 N12 T1
M3 MD_DQ27 VDDQ<16> VSSQ<16>
DQ27 BI 13 21 N9 VDDQ<15> VSSQ<15> P12
DQ26 N2 MD_DQ26 BI 13 21 V12 P9
L3 MD_DQ25 VDDQ<14> VSSQ<14>
DQ25 BI 13 21 N4 VDDQ<13> VSSQ<13> P4
DQ24 M2 MD_DQ24 BI 13 21 N1 P1
P2 MD_WDQS3 VDDQ<12> VSSQ<12>
WDQS3 IN 13 J9 VSSQ<11> L11
P3 MD_RDQS3 VDDQ<11>
RDQS3 OUT 21 13 J4 VDDQ<10> VSSQ<10> L2
DM3 N3 MD_DM3 IN 13 E12 G11
VDDQ<9> VSSQ<9>
MD_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MD_DQ23 BI 13 21 E4 D12
13 IN 11 L4 T11 MD_DQ22 VDDQ<7> VSSQ<7>
A11/A7 DQ22 BI 13 21 E1 VDDQ<6> D9
10 K2 R10 MD_DQ21 VSSQ<6>
A10/A8 DQ21 BI 13 21 C12 VDDQ<5> D4
9 M9 R11 MD_DQ20 VSSQ<5>
A9/A3 DQ20 BI 13 21 C9 D1
C 8
7
K11
L9
A8/A10 DQ19 M10
N11
MD_DQ19
MD_DQ18 BI 13 21 C4
VDDQ<4>
VDDQ<3>
VSSQ<4>
VSSQ<3> B12 C
A7/A11 DQ18 BI 13 21 C1 VDDQ<2> B9
6 K10 L10 MD_DQ17 VSSQ<2>
A6/A2 DQ17 BI 13 21 A12 VDDQ<1> B4
5 H11 M11 MD_DQ16 VSSQ<1>
A5/A1 DQ16 BI 13 21 A1 VDDQ<0> B1
4 K9 P11 MD_WDQS2 VSSQ<0>
A4/A0 WDQS2 IN 13
3 M4 A3/A9 RDQS2 P10 MD_RDQS2 OUT 21 13 V2 V3
2 K3 N10 MD_DM2 VDD<7> VSS<7>
A2/A6 DM2 IN 13 M12 VDD<6> L12
1 H2 VSS<6>
A1/A5 M1 VDD<5> L1
0 K4 G10 MD_DQ15 VSS<5>
A0/A4 DQ15 BI 13 21 V11 VDD<4> G12
F11 MD_DQ14 VSS<4>
MD_BA<2..0> DQ14 BI 13 21 F12 VDD<3> VSS<3> G1
13 IN 2 H10 F10 MD_DQ13
BA2/RAS_N DQ13 BI 13 21 F1 VDD<2> A10
1 G9 E11 MD_DQ12 VSS<2>
BA1/BA0 DQ12 BI 13 21 A11 VDD<1> V10
0 G4 C10 MD_DQ11 VSS<1>
BA0/BA1 DQ11 BI 13 21 A2 VDD<0> A3
C11 MD_DQ10 VSS<0>
DQ10 BI 13 21
13 IN MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 BI 13 21 K12
MD_WE_N H9 B11 MD_DQ8 VDDA<1>
13 IN WE_N/CKE DQ8 BI 13 21 K1 VDDA<0>
13 IN MD_CAS_N F4 CAS_N/CS_N WDQS1 D11 MD_WDQS1 IN 13
13 IN MD_RAS_N H3 RAS_N/BA2 RDQS1 D10 MD_RDQS1 OUT 21 13 J12
MD_CS0_N F9 E10 MD_DM1 VSSA<1>
13 IN CS_N/CAS_N DM1 IN 13 J1 VSSA<0>
13 IN MD_CS1_N J3 CS1_N (1Gbit only, single-load)
4 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MD_DQ7 BI 13 21
DQ6 F2 MD_DQ6 BI 13 21
MEM_SCAN_EN V4 F3 MD_DQ5 X802980-019
B 4 IN SCAN_EN DQ5
DQ4 E2 MD_DQ4 BI
BI
13 21
13 21 B
20 IN MEM_D_VREF1 H1 VREF1 DQ3 C3 MD_DQ3 BI 13 21
DQ1 B3 MD_DQ1 BI 13 21
WDQS0 D2 MD_WDQS0 IN 13
RDQS0 D3 MD_RDQS0 OUT 21 13
DM0 E3 MD_DM0 IN 13
ZQ A4 MD_ZQ_TOP
1 R6F5
243 OHM
X802980-019 1%
V_MEM 2 CH
402
1 R6U5
549 OHM
1%
2 CH
402
MEM_D_VREF1 OUT 20 21
PARTITION D DECOUPLING
1 R6U4 V_MEM V_MEM
1.27 KOHM C6U7
1% 0.1 UF MEMORY D, TOP, DECOUPLING
2 CH 10%
402 6.3 V
A X5R
402
1 C6F11 A
4.7 UF
10%
6.3 V
C5F9 C5F7 C5F4 C5F3 C5F2 C5F5 C5F6 C5F8
2 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
X5R 10% 10% 10% 10% 10% 10% 10% 10%
603 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402

[PAGE_TITLE=MEMORY PARTITION D, TOP] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY PARTITION D, BOTTOM
V_MEM
D D
1 R6U2 1 R6U3
60.4 OHM
60.4 OHM 1%
1%
2 CH 2 CH
402 U6U1 EMPTY
402
GDDR136 (1Gbit) V_MEM
13 IN MD_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MD_DQ23 BI 13 20
MD_CLK1_DN J10 T2 MD_DQ22 U6U1 EMPTY
13 IN CLK_DN DQ30 BI 13 20
4 IN MEM_RST V9 RESET DQ29 R3 MD_DQ21 BI 13 20 GDDR136 (1Gbit)
DQ28 R2 MD_DQ20 BI 13 20 V1 VDDQ<21> MF=0
DQ27 M3 MD_DQ19 BI 13 20 R12 VDDQ<20>
DQ26 N2 MD_DQ18 BI 13 20 R9 VDDQ<19> VSSQ<19> T12
DQ25 L3 MD_DQ17 BI 13 20 R4 VDDQ<18> VSSQ<18> T9
DQ24 M2 MD_DQ16 BI 13 20 R1 VDDQ<17> VSSQ<17> T4
WDQS3 P2 MD_WDQS2 IN 13 N12 VDDQ<16> VSSQ<16> T1
RDQS3 P3 MD_RDQS2 OUT 20 13 N9 VDDQ<15> VSSQ<15> P12
DM3 N3 MD_DM2 IN 13 V12 VDDQ<14> VSSQ<14> P9
MD_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MD_DQ31 BI 13 20 N1 VDDQ<12> VSSQ<12> P1
13 IN 11 L9 T11 MD_DQ30 J9 L11
A7/A11 DQ22 BI 13 20 VDDQ<11> VSSQ<11>
C 10
9
K11
M4
A8/A10 DQ21 R10
R11
MD_DQ29
MD_DQ28 BI 13 20 J4
E12
VDDQ<10> VSSQ<10> L2
G11 C
A3/A9 DQ20 BI 13 20 VDDQ<9> VSSQ<9>
8 K2 A10/A8 DQ19 M10 MD_DQ27 BI 13 20 E9 VDDQ<8> VSSQ<8> G2
7 L4 A11/A7 DQ18 N11 MD_DQ26 BI 13 20 E4 VDDQ<7> VSSQ<7> D12
6 K3 A2/A6 DQ17 L10 MD_DQ25 BI 13 20 E1 VDDQ<6> VSSQ<6> D9
5 H2 A1/A5 DQ16 M11 MD_DQ24 BI 13 20 C12 VDDQ<5> VSSQ<5> D4
4 K4 A0/A4 WDQS2 P11 MD_WDQS3 IN 13 C9 VDDQ<4> VSSQ<4> D1
3 M9 A9/A3 RDQS2 P10 MD_RDQS3 OUT 20 13 C4 VDDQ<3> VSSQ<3> B12
2 K10 A6/A2 DM2 N10 MD_DM3 IN 13 C1 VDDQ<2> VSSQ<2> B9
1 H11 A5/A1 A12 VDDQ<1> VSSQ<1> B4
0 K9 A4/A0 DQ15 G10 MD_DQ7 BI 13 20 A1 VDDQ<0> VSSQ<0> B1
MD_BA<2..0> DQ14 F11 MD_DQ6 BI 13 20
13 IN 2 H3 F10 MD_DQ5 V2 V3
RAS_N/BA2 DQ13 BI 13 20 VDD<7> VSS<7>
1 G4 BA0/BA1 DQ12 E11 MD_DQ4 BI 13 20 M12 VDD<6> VSS<6> L12
0 G9 BA1/BA0 DQ11 C10 MD_DQ3 BI 13 20 M1 VDD<5> VSS<5> L1
DQ10 C11 MD_DQ2 BI 13 20 V11 VDD<4> VSS<4> G12
13 IN MD_CKE H9 WE_N/CKE DQ9 B10 MD_DQ1 BI 13 20 F12 VDD<3> VSS<3> G1
13 IN MD_WE_N H4 CKE/WE_N DQ8 B11 MD_DQ0 BI 13 20 F1 VDD<2> VSS<2> A10
13 IN MD_CAS_N F9 CS_N/CAS_N WDQS1 D11 MD_WDQS0 IN 13 A11 VDD<1> VSS<1> V10
13 IN MD_RAS_N H10 BA2/RAS_N RDQS1 D10 MD_RDQS0 OUT 20 13 A2 VDD<0> VSS<0> A3
13 IN MD_CS1_N F4 CAS_N/CS_N DM1 E10 MD_DM0 IN 13
J3 CS1_N (1Gbit only, single-load) K12 VDDA<1>
MEM_SCAN_BOT_EN A9 G3 MD_DQ15 K1
B 4 IN MF DQ7
DQ6 F2 MD_DQ14 BI
BI
13 20
13 20
VDDA<0>
B
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MD_DQ13 BI 13 20 J12 VSSA<1>
DQ4 E2 MD_DQ12 BI 13 20 J1 VSSA<0>
DQ1 B3 MD_DQ9 BI 13 20 X802980-019
WDQS0 D2 MD_WDQS1 IN 13
RDQS0 D3 MD_RDQS1 OUT 20 13
DM0 E3 MD_DM1 IN 13
ZQ A4 MD_ZQ_BOT
1 R6U1
V_MEM 243 OHM
X802980-019 1%
2 CH
402
1 R6F1
549 OHM
1%
2 CH
402
MEM_D_VREF0 OUT 20 21
1 R6F2 V_MEM
1.27 KOHM C6F3 V_MEM
1% 0.1 UF MEMORY D, BOTTOM, DECOUPLING
10% MEMORY D, BOTTOM, DECOUPLING
2 CH 6.3 V
A 402 X5R
402 A
C5U12 C6U10 C6F6 C7E12 C7T10 C7E1 C7D15 C7R9 C5U8 C5U5 C5U4 C5U3 C5U6 C5U7 C5U11 C5U10
10% 10% 10% 10% 10% 10% 10% 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402

[PAGE_TITLE=MEMORY PARTITION D, BOTTOM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, CLOCKS + STRAPPING + POR

V_12P0
D V12P0_PWRGD OUT 25 42
D
XTAL BYPASS: STUFF R3, R4, R5, AND C153 AND
APPLY SQUARE WAVE TO XTAL_IN (VL=0V VH=1V)
KEEP R5 CLOSE TO KSB CHIP
RESISTOR VALUES CHOSEN TO GIVE V_12P0_DET 1P8V NOMINAL 1
FTP FT2P6
1 1 R3R5 2 1 R3R17 2
DB3D2
1% 84.52 KOHM 1% 15 KOHM V_RST_OK
CH 402 CH 402 OUT
Y3D1 1
25 MHZ 2 C3R55 1
470 PF FTP FT3R3
1 2 5%
R3D26 50 V
49.9 OHM 2 EMPTY SB_MAIN_PWRGD
SM 1% 402 IN 25
XTAL EMPTY U3D1 IC
2 2 402
KSB 1
FTP FT3P5
C3D7 C3D8 1
2 R3P2 1 SB_RST_N 25
27 PF 22 PF 1 OF 9 1
IN
5% 5% V_12P0_OK C5 1 KOHM 5%
50 V 50 V V19 402 CH R2P3
1 COG 1 NPO V_12P0_DET W20 V_RST_OK<DN>
402 402 V_12P0_DET 10 KOHM
DB2C2
1 POR_BYPASS B4 POR_BYPASS<DN> 5%
V_3P3STBY C4 CH
MAIN_PWR_OK 402
2
C 2
SB_RST_N* C9
D7
SB_RST_N_R
SMC_RST_N_R C
SMC_RST_N_OUT
R3D17
XTAL_IN AB21 XTAL_IN 1
8.25 KOHM CPU_CLK_DP U21 CPU_CLK_DP_R
1% CPU_CLK_DN V21 CPU_CLK_DN_R R3P15
10 KOHM 2 R3P16 1 SMC_RST_N
EMPTY 5% OUT 25 42 62
402 NB_CLK_DP V22 GPU_CLK_DP_R 1 KOHM 5%
1 W22 GPU_CLK_DN_R CH 402 CH
XTAL_OUT AA21 NB_CLK_DN 402
XTAL_OUT
2
2
AA22 XTAL_VSS
1
R3D19 C3D1
1.5 KOHM 0.01 UF PCIEX_CLK_IN_DP Y15 EXT_PCIEX_CLK_DP R3D6 1 R3D7 2
1% 10%
16 V PCIEX_CLK_IN_DN AA15 EXT_PCIEX_CLK_DN
EMPTY 2 EMPTY 33 OHM 5% 49.9 OHM 1%
402 402 402 CH 402 CH
1
PIX_CLK_OUT_DP U22 PIX_CLK_2X_DP_R CPU_CLK_DP OUT 2
PIX_CLK_OUT_DN T22 PIX_CLK_2X_DN_R CPU_CLK_DN OUT 2
DB3D31 EXT_CLK48_IN Y20 CLK48<DN>
R3D8 1 R3D9 2
DB3D11 EXT_CLK48_SEL W19 CLK48_BYPASS<DN> 33 OHM 5% 49.9 OHM 1%
402 CH 402 CH
B B
62 61 55 25 BI SMB_DATA A4 SMB_DATA R3D10 1 R3D11 2
62 61 55 25 BI SMB_CLK A5 SMB_CLK
33 OHM 5% 49.9 OHM 1%
402 CH 402 CH
GPU_CLK_DP OUT 4 62
GPU_CLK_DN V_3P3
X850744-001 PBGA404 OUT 4 62
I155 R3D12 1 R3D13 2
33 OHM 5% 49.9 OHM 1% 2
402 CH 402 CH
R3D28
10 KOHM
1%
CH
402
1
I2C ADDRESS 1 DB3R6
0011 100 R/W HEX 0111 000 R/W HEX 1 DB3R7
WRITE 0011 100 0 0X38 WRITE 0111 000 0 0X70
READ 0011 100 1 0X39 READ 0111 000 1 0X71 2
0011 110 R/W HEX R3D29
WRITE 0011 110 0 0X3C 10 KOHM
READ 0011 110 1 0X3D 1%
CH
1 R3D5 2 1 R3D14 2 402
1
33 OHM 5% 60.4 OHM 1%
402 CH 402 CH
A PIX_CLK_2X_DP
A
OUT 4
PIX_CLK_2X_DN OUT 4
1 R3D3 2 1 R3D4 2
1
33 OHM 5% 60.4 OHM 1% FTP FT3R7
1
402 CH 402 CH FTP FT3R2

[PAGE_TITLE=KSB, CLOCKS + STRAPING] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB
KSB, VIDEO + FAN U3D1
2 OF 9
IC
OUT
OUT
37
37
37
OUT
GPU_PIX_CLK_1X J20 OUT 37
4 IN PIX_CLK_IN
4 PIX_DATA<14..0>
IN 14 G20 PIX_DATA14 DAC_D_OUT_DP A20 VID_DACD_DP
13 G21 F18
D 12 G22
PIX_DATA13
PIX_DATA12
DAC_D_OUT_DN
DAC_B_OUT_DP A21 VID_DACB_DP D
11 H20 PIX_DATA11 DAC_B_OUT_DN G18
10 H21 PIX_DATA10 DAC_A_OUT_DP C22 VID_DACA_DP
9 H22 PIX_DATA9 DAC_A_OUT_DN G19
8 J21 PIX_DATA8 DAC_C_OUT_DP D22 VID_DACC_DP
7 J22 PIX_DATA7 DAC_C_OUT_DN H18
6 K21 PIX_DATA6
5 K22 PIX_DATA5
4 K20 PIX_DATA4
3 L21 PIX_DATA3
2 L22 PIX_DATA2
1 L20 PIX_DATA1
0 M20 PIX_DATA0
4 IN GPU_HSYNC_OUT M22 HSYNC_IN

4 IN GPU_VSYNC_OUT M21 VSYNC_IN
DAC_RSET D20 DAC_RSET
1 R3P11
5.11 KOHM
0.1%
2 CH
402
C C
HSYNC_OUT B19 VID_HSYNC_OUT_R OUT 37
VSYNC_OUT C19 VID_VSYNC_OUT_R OUT 37
OUT 40
C3C4
2 1 HDMI_TXC_DP_R 2 R3C23 1
0.1 UF 10% 301 OHM 1%

R4G2 TMDS_TXC_DP A16 HDMI_TXC_DP 6.3 V 603 EMPTY
61 IN BRD_TEMP_P 1 2 BRD_TEMP_P_DIODE Q4G1 EMPTY
402
0 OHM 5% 2 EMPTY TMDS_TXC_DN B16 HDMI_TXC_DN 40
402 EMPTY 1
OUT
3 OUT 40
C3C1 2 R3C20 1
2 1 HDMI_TX2_DP_R
TMDS_TX2_DP B13 HDMI_TX2_DP 0.1 UF 10% 301 OHM 1%

R4G1 6.3 V 603 EMPTY
61 38 OUT BRD_TEMP_N 1 2 BRD_TEMP_N_DIODE EMPTY
TMDS_TX2_DN C13 HDMI_TX2_DN 402 40
0 OHM 5% OUT
402 EMPTY 40 IN HDMI_HPD D18 HDMI_HPD
OUT 40
B 2
C3C2
1 HDMI_TX1_DP_R 2 R3C21 1 B
TMDS_TX1_DP A14 HDMI_TX1_DP 0.1 UF 10% 301 OHM 1%
6.3 V 603 EMPTY
KSB_RSET H4 EMPTY
RSET B14 HDMI_TX1_DN 402
TMDS_TX1_DN
1 R2P4
2 KOHM OUT
1%
1 2 CH OUT 40
FT3P1 FTP 402 C3C3
HDMI_TX0_DP
40
TMDS_TX0_DP B15 2 1 HDMI_TX0_DP_R 2 R3C22 1
0.1 UF 10% 301 OHM 1%

SMC_PWM0 2 R3P3 1 FAN_OP1_DP F22 TMDS_TX0_DN C15 HDMI_TX0_DN 6.3 V 603 EMPTY
25 IN FAN_OP1_DP EMPTY
205 KOHM 1% 402 40
402 EMPTY 1
C3P2
OUT
0.22 UF 1 CUSTOM THERMAL
10% DB3P1
6.3 V 1 CALIBRATION PADS
ST3C5 2 DB3R1
CPU_TEMP_N_KSB 2 1
EMPTY
402 36 IN FAN1_FDBK F21 FAN_OP1_DN LOCATION MUST
64 61 IN A12 HDMI_DDC_CLK 1
DDC_SCK BI 37 40 55 DB3P2 REMAIN LOCKED
SHORT DDC_SDA B12 HDMI_DDC_DATA BI 37 40 55 1
DB3R2
P22 TEMP_N
ST3C2
64 61 IN GPU_TEMP_N_KSB 2 1
1
SHORT C3R1
FAN_OUT1 E21 FAN1_OUT 36 100 PF
ST3C4 OUT 5%
EDRAM_TEMP_N_KSB 2 1 50 V
A
64 61 IN
N22 CAL_TEMP_P
2 EMPTY
402 A
SHORT TEMP3_P CAL_TEMP_N OUT 23
ST3C3 TEMP2_P P20 GPU_TEMP_P_KSB OUT 61 64
61 IN BRD_TEMP_N_KSB 2 1
TEMP1_P P21 CPU_TEMP_P_KSB OUT 61 64
SHORT
ST3C1 TEMP0_P R21 EDRAM_TEMP_P_KSB OUT 61 64
23 IN CAL_TEMP_N 2 1
N21 BRD_TEMP_P_KSB
TEMP4_P OUT 61
SHORT
X850744-001 PBGA404

[PAGE_TITLE=KSB, VIDEO + FAN] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3 KSB, PCIEX + SMM GPIO + JTAG
U3D1 KSB IC
1 1 1 1 1 4 OF 9
D R2C14
10 KOHM
R2C12
10 KOHM
R2C18
10 KOHM
R2C16
10 KOHM
R2C20
10 KOHM PEX_TX1_DP AA19 PEX_SB_GPU_L1_DP_C 1
C3D5
2 PEX_SB_GPU_L1_DP OUT 4 62
D
5% 5% 5% 5% 5%
0.1 UF 10%
EMPTY EMPTY EMPTY EMPTY EMPTY 6.3 V
402 402 402 402 402 X5R
2 2 2 2 2 402
0 1 2 3 5 SB_GPIO<0..15> BI 24 62 C3D6
PEX_TX1_DN AB19 PEX_SB_GPU_L1_DN_C 1 2 PEX_SB_GPU_L1_DN 4 62
1 1 1 1 1
OUT
0.1 UF 10%
R2C13 R2C11 R2C17 R2C15 R2C19 6.3 V
1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM X5R
5% 5% 5% 5% 5% 402
CH CH CH CH CH
402 402 402 402 402 C3D3
2 2 2 2 2 AA17 PEX_SB_GPU_L0_DP_C 1 2 PEX_SB_GPU_L0_DP
PEX_TX0_DP OUT 4 62
0.1 UF 10%
6.3 V
X5R
402
4 PEX_GPU_SB_L1_DP Y18 PEX_RX1_DP C3D4

IN PEX_TX0_DN AB17 PEX_SB_GPU_L0_DN_C 1 2 PEX_SB_GPU_L0_DN 4 62
4 IN PEX_GPU_SB_L1_DN AA18 PEX_RX1_DN OUT
0.1 UF 10%
C 4 IN PEX_GPU_SB_L0_DP
PEX_GPU_SB_L0_DN
Y16
AA16
PEX_RX0_DP 6.3 V
X5R C
4 IN PEX_RX0_DN 402
V_3P3STBY
A2 KER_DBG_TXD_R 2 R2C9 1 KER_DBG_TXD
UART0_TXD OUT 62
R3G19 62 KER_DBG_RXD A3 UART0_RXD<UP> 47 OHM 5%
1 10 KOHM IN 402 CH
5%
CH
2 402
R2C21
24 IN AUD_SPI_MOSI_R 1 2 AUD_SPI_MOSI OUT 35
0 OHM 5%
402 CH 1 R2C1
10 KOHM TST_PT E18 KSB_DEBUG 1 DB3P3
5%
2 EMPTY
402
V_3P3STBY
R3G18
1 10 KOHM
B 5% B
CH F2 AUD_SPI_MISO_R
R2C25 2 402 GPIO15 IN 24
62 24 OUT AUD_SPI_MISO_R 1 2 AUD_SPI_MISO IN 35 GPIO14 F3 AUD_SSB_R OUT 24 62
0 OHM 5% 1 R2C24 GPIO13 E1 SCART_RGB OUT 37 62
402 CH 10 KOHM GPIO12 E4 AUD_RST_N OUT 33
5% GPIO<1> = 0 ENABLE DEBUG OUTPUT GPIO11 E3 AUD_RDY_BSBY_R 24 62 R2P9
F4 62 FAN_TACH_SMM_R
OUT 5% 2 1 0 OHM FAN_TACH
2 EMPTY 1 DISABLE DEBUG OUTPUT GPIO10 IN 36
402 GPIO9 G4 WSS_CNTL0 OUT 37 62 CH 402
GPIO<0,2,3> = 111 XENON GPIO8 G3 WSS_CNTL1 OUT 37 62
110 ZEPHYR A GPIO7 D3 AUD_SPI_MOSI_R 24 62
OUT
V_3P3STBY 101 ZEPHYR B GPIO6 D4 AUD_SPI_CLK_R
OUT 24 62 DEBUG BUS
100 ZEPHYR C GPIO5 E2 SB_GPIO<5> 24 62
C1 SB_GPIO<4>
BI NET NAME DEBUG BUS BIT
R3G3 011 FALCON GPIO4 OUT 24 62
1 10 KOHM 010 JASPER GPIO3 C2 SB_GPIO<3> 24 62
5% D1 SB_GPIO<2>
OUT SB_GPIO<0> 0
001 TRINITY GPIO2 OUT 24 62
CH 000 CORONA GPIO1 B1 SB_GPIO<1> 24 62
2 402 B2 SB_GPIO<0>
BI SB_GPIO<2> 1
R2C23 GPIO0 OUT 24 62
24 IN AUD_SPI_CLK_R 1 2 AUD_SPI_CLK OUT 35
SB_TCLK T19 SB_GPIO<3> 2
0 OHM 5% 1 R2C22 63 IN TCK<DN>
402 CH 10 KOHM 63 OUT SB_TDO R19 TDO
5% SB_TDI R20 SB_GPIO<4> 3
63 IN TDI<UP>
2 EMPTY 63 IN SB_TMS U19 TMS<UP>
402 SB_TRST N19 AUD_SPI_CLK_R 4
63 IN TRST<DN>
1
FT3T8 FTP SB_GPIO<5> 5
V_3P3STBY 1 X850744-001
FT3T7 FTP
1 PBGA404
FT3T6 FTP WSS_CNTL1 6
1 V_3P3STBY
A R2G6
1 10 KOHM
FT3T5 FTP
FT3T4 FTP
1
R3G20
WSS_CNTL0 7 A
5%
1 10 KOHM FAN_TACH 8
CH 5%
2 402
R2G5
AUD_RDY_BSBY_R 1 2 AUD_RDY_BSBY CH AUD_RDY_BSBY_R 9
24 IN OUT 35
R2P5 2 402
0 OHM 5% 24 AUD_SSB_R 1 2 AUD_SSB 35 SCART_RGB 10
402 CH 1 R2G7 IN OUT
10 KOHM 0 OHM 5% 1 R2C26
5% 402 CH 10 KOHM AUD_SSB_R 11
2 EMPTY 5%
402 AUD_SPI_MISO_R 12
2 EMPTY
402

[PAGE_TITLE=KSB, PCIEX + SMM GPIO + JTAG] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, SMC N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE V_3P3STBY
U3D1 KSB IC DBG_LED0 PULLUP = SMC DEVELOPMENT MODE
1
I189
5 OF 9 R3C16 R2G3
1 2 KOHM
FT2P1 FTP SMC_UART1_TXD A7 SMC_DBG_TXD_R 1 2 SMC_DBG_TXD OUT 62 1%
47 OHM 5%
D 22 IN SMC_RST_N D8 SMC_RST_N_IN* SMC_P2_GPIO7 W12 VREG_V5P0_EN 402 CH OUT 47
CH
402 D
2
C3P9 SMC_P2_GPIO6 W13 DBG_LED0 OUT 63
1 UF EXT_TEMP_PWR_CTRL 1
10% SMC_P2_GPIO5 Y11 61
16 V 1
OUT R2G4
DB2G3 1
X5R DB3R5 2 KOHM
603 SMC_P2_GPIO4 AB11 BINDSW_N IN 38 1%
AB10 VREG_VMEM_PWRGD EMPTY
SMC_P2_GPIO3 IN 50 402
2
SMC_P2_GPIO2 AA11 VREG_VMEM_EN OUT 50
SMC_P2_GPIO1 AA12 VREG_VEDRAM_PWRGD IN 49
SMC_P2_GPIO0 Y12 VREG_V5P0_PWRGD IN 47

62 IN SMC_DBG_RXD A6 SMC_UART1_RXD<UP> 1 DB2E2
1 DB2E3
62 IN SMC_DBG_EN D6 SMC_DBG<DN> 1 DB2D1
SMC_P1_GPIO7 W11 VREG_V3P3_EN OUT 48
AV_MODE1 2 R2M1 1 AV_MODE1_R A8
37 IN SMC_P4_GPIO7 V9 TILTSW_N
SMC_P1_GPIO6 IN 35
10 KOHM 5% R3C3
52 VREG_1P2_EN 402 CH 0 OHM 1 2 5% VREG_1P2_EN_R B8 SMC_P4_GPIO6
OUT AA10 PWRSW_N
C FAN_TACH 0 OHM 1
R2C27
2 5%
402 CH
FAN_TACH_SMC_R B7
SMC_P1_GPIO5 IN 38
C
36 IN SMC_P4_GPIO5 Y10 VREG_VEDRAM_EN
402 EMPTY SMC_P1_GPIO4 OUT 49
1
DB2P1 SMC_P1_GPIO3 Y9 EJECTSW_N IN 38
AV_MODE0 2 R3P4 1 AV_MODE0_R C8
37 IN SMC_P4_GPIO4
10 KOHM 5% SMC_P1_GPIO2 W10 VREG_V5P0_SEL OUT 46
402 CH
SMC_P1_GPIO1 AB9 VREG_V3P3_PWRGD IN 48
1 DB3C3
W9 EXT_PWR_ON_N_R 2 R2C5 1 EXT_PWR_ON_N
SMC_P1_GPIO0 IN 37 62 63
10 KOHM 5%
402 CH
1
DB2C1
22 V12P0_PWRGD C6 SMC_P4_GPIO3 1 DB1E2
IN
AV_MODE2 2 R3N5 1 AV_MODE2_R A9
37 IN SMC_P4_GPIO2
10 KOHM 5%
402 CH
B V_3P3STBY V_3P3STBY
B
1 R2P1 1 R2P2
1.27 KOHM 1.27 KOHM
1% 1%
CH CH
2 402 2 402
1 2 R3E6 1 GPU_RST_DONE
FTP FT2P2 Y13 GPU_RST_DONE_R
62 61 55 22 BI SMB_DATA B5 SMC_P4_GPIO1
SMC_P0_GPIO7
1 KOHM 5%
IN 4
DEBUG BUS
SMC_P0_GPIO6 AA14 CPU_RST_N OUT 2 402 CH 1 R3E7
62 61 55 22 SMB_CLK B6 SMC_P4_GPIO0 10 KOHM
BI 1 W14 SMC_P0_GPIO5 1 DB3R4 5% KSB PIN DEBUG BUS BIT
FTP FT2P3 SMC_P0_GPIO5 CH
2 402
VREG_CPU_EN A11 AB15 EXT_JTM_SEL 1 DB3R3 SMC_P1_GPIO1 13
44 OUT SMC_P3_GPIO7 SMC_P0_GPIO4 V_1P8STBY
R3C14
SB_MAIN_PWRGD 1 2 SB_MAIN_PWRGD_R C10 FAN_TACH 14
22 OUT SMC_P3_GPIO6 1 R3R12
1 KOHM 5% 10 KOHM 1 R3R10
402 CH PSU_V12P0_EN B11 5% 10 KOHM SMC_PWM0 15
42 38 OUT SMC_P3_GPIO5 PU: EXT JTM 5% 1 R3R7 1 R3R8
EMPTY
PD: KSB JTM 2 402 CH 100 KOHM 100 KOHM
1 R3C18 SB_RST_N B9 2 402 5% 5% SMC_P1_GPIO6 16
1 22 OUT SMC_P3_GPIO4
FT2P4 FTP 10 KOHM CH CH
5% 2 402 2 402
TRAY_OPEN 2 R3C19 1 TRAY_OPEN_R C11 SMC_P2_GPIO0 17
41 OUT SMC_P3_GPIO3 AB13 BORONFPM_DATA
2 CH SMC_P0_GPIO3 BI 38
402 33 OHM 5% SMC_P0_GPIO2 AB14 BORONFPM_CLK 38 SMC_P2_GPIO1 18
63 BI SMC_CPU_CHKSTOP_DETECT 402 CH C12 SMC_P3_GPIO2 BI
VREG_CPUCORE_PWRGD D12 SMC_P2_GPIO3 19
44 IN SMC_P3_GPIO1
TRAY_STATUS B10 SMC_P0_GPIO1 Y14 GPU_RST_N OUT 4 SMC_P2_GPIO4 20
A
41 IN SMC_P3_GPIO0
SMC_P0_GPIO0 AA13 CPU_PWRGD OUT 2 63 A
IR_DATA W8 SMC_P2_GPIO5 21
35 IN SMC_IR_IN
SMC_PWM1 D10 SMC_PWM1 OUT 36
D11 SMC_PWM0 SMC_P3_GPIO1 22
SMC_PWM0 OUT 23
1 1 SMC_P3_GPIO2 23
DB5B4 FTP FT3P2 X850744-001 DB3C1
PBGA404 1
SMC_P1,2,3,4 GPIOS ARE ON V3P3STBY. SMC_P0 GPIOS ARE ON 1P8VSTBY

[PAGE_TITLE=KSB, SMC] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, FLASH + USB + SPI
N: ALL PORTS ARE DIFFERENTIAL USB PAIRS ON THIS PAGE
D D
U3D1 KSB IC
6 OF 9
SPI_CLK W6 W7 SPI_MISO_R 2 R2C8 1 SPI_MISO
62 IN SPI_CLK SPI_MISO OUT 62
62 IN SPI_MOSI W4 SPI_MOSI 33 OHM 5%
62 IN SPI_SS_N W5 SPI_SS_N*<UP> 402 CH
34 63 32 BI FLSH_DATA<7..0> 7 Y6 FLSH_DATA7
6 AA6 FLSH_DATA6
5 AB6 FLSH_CLE AB4 FLSH_CLE OUT 32 34
FLSH_DATA5
4 Y7 FLSH_DATA4 2 R3R9 1
3 AA7 FLSH_CE_N* AA5 FLSH_CE_N_R FLSH_CE_N OUT 32 34 63
FLSH_DATA3
2 Y8 FLSH_DATA2 10 OHM 1%
1 AA8 FLSH_RE_N* AB3 FLSH_RE_N 402 CH OUT 34
FLSH_DATA1
0 AB8 FLSH_DATA0
FLSH_WE_N* Y5 FLSH_WE_N OUT 34
FLSH_ALE AA4 FLSH_ALE OUT 34
C C
34 32 63 OUT FLSH_WP_N AB5 FLSH_WP_N*
USBB_D4_DP U2 GAMEPORT2_DP BI 39
USBB_D4_DN U1 GAMEPORT2_DN BI V_5P0STBY
39
USBB_D3_DP N2 WAVEPORT_DP BI 39
USBB_D3_DN N1 WAVEPORT_DN BI 39
T3 GAMEPORT1_DP J1D1
USBB_D2_DP BI 39
USBB_D2_DN T2 GAMEPORT1_DN BI 39 1X5HDR
1
USBB_D1_DP P3 USBB_D1_DP 2
USBB_D1_DN P2 USBB_D1_DN 3
4
USBB_D0_DP R2 BORONFPMPORT_DP BI 38 5
USBB_D0_DN R1 BORONFPMPORT_DN BI 38
34 IN FLSH_READY AB2 FLSH_READY EMPTY
TH
B B
38 BI EXPPORT_RJ45_DP J2 USBA_D3_DP 47 V_VREG_V3P3_V5P0
38 BI EXPPORT_RJ45_DN J1 USBA_D3_DN
39 BI EXPPORT_PORT1_DP M3 USBA_D2_DP 1 1 1 1 1 1
39 BI EXPPORT_PORT1_DN M2 USBA_D2_DN C2R13 C2R11 C2R12 C2T3 C2T1 C2T2
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10%
39 BI EXPPORT_PORT3_DP K3 USBA_D1_DP 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
EXPPORT_PORT3_DN K2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
39 BI USBA_D1_DN 402 402 402 402 402 402
39 BI EXPPORT_PORT2_DP L2 USBA_D0_DP
39 BI EXPPORT_PORT2_DN L1 USBA_D0_DN
X850744-001 PBGA404 STITCHING CAPS FOR USB ON PLANE SPLIT
A A

[PAGE_TITLE=KSB, FLASH + USB + SPI] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, ETHERNET + AUDIO + SATA
D D
V_3P3STBY
1 1 1 1
C3P32 C3P35 C3P33 C3P34 V_1P2STBY
0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
STITCHING CAPS FOR I2S SIGNALS,PARTICULARLY MCLK.

C PLACE AS CLOSE AS POSSIBLE TO I2S_MCLK, I2S_BCLK, I2S_SD, AND I2S_WS.
C
U3D1
KSB IC
7 OF 9
38 BI ENET_RX_DN H2 MDIN1 MDIN0 G1 ENET_TX_DN BI 38
38 BI ENET_RX_DP H3 MDIP1 MDIP0 G2 ENET_TX_DP BI 38
B18 I2S_MCLK_R R3P14 I2S_MCLK

I2S_MCLK_OUT OUT 33
47 OHM 5%
B17 I2S_BCLK_R R3P10 402 CH I2S_BCLK
I2S_BCLK_OUT OUT 33
47 OHM 5%
A17 I2S_SD_R 402 CH R3P9 I2S_SD
I2S_SD OUT 33
47 OHM 5%
C17 I2S_WS_R R3P8 402 CH I2S_WS
I2S_WS OUT 33
47 OHM 5%
HDD_RX_DP Y2 D16 SPDIF_OUT_R 402 CH 1 R3P20 2 SPDIF_OUT
B 41
41
IN
IN HDD_RX_DN Y3
SATA1_RX_DP
SATA1_RX_DN
SPDIF_OUT
0 OHM 5%
OUT 37 39
B
402 CH
41 IN ODD_RX_DP V2 SATA0_RX_DP
41 IN ODD_RX_DN V3 SATA0_RX_DN 1 R3P12 1 R3P13 1 R3P19
10 KOHM 10 KOHM 10 KOHM
5% 5% 5%
2 CH 2 CH 2 CH
402 402 402
SATA1_TX_DP AA2 HDD_TX_DP OUT 41

SATA1_TX_DN AA1 HDD_TX_DN OUT 41
SATA0_TX_DP W2 ODD_TX_DP OUT 41

SATA0_TX_DN W1 ODD_TX_DN OUT 41
X850744-001 PBGA404
A A

[PAGE_TITLE=KSB, ETHERNET + AUDIO + SATA] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB,DECOUPLING
V_1P8
D D
1 1 1 1 1 1
C3R30 C3P31 C3R3 C3R12 C3R10 C3R13
0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF
10% 10% 10% 10% 10% 10%
16 V 16 V 16 V 16 V 16 V 16 V
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 402
V_3P3 V_3P3STBY
C 1
C2P3
1
C3P14
1
C3P18
1
C3P19
1
C3P17
1
C3P23
1
C3R40
1
C3R43
1
C3R34
1
C3P21
1
C3R41 C
0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
16 V 16 V 16 V 16 V 16 V 16 V 16 V 16 V 16 V 16 V 16 V
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 402 402 402 402 402 402
V_1P2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C3R5 C3P27 C3R6 C3R14 C3R23 C3R9 C3R18 C3R24 C3P28 C3R22 C3P30 C3R25 C3R27 C3P29 C3R29 1
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF C3R17
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 0.01 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 16 V 16 V 16 V 16 V 16 V 16 V 16 V 10%
B 2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X7R
402
2 X7R
402
2 X7R
402
2 X7R
402
2 X7R
402
2 X7R
402
2 X7R
402 2
16 V
X7R
402 B
VAA_3P3_VDAC
V_3P3STBY_ANA V_3P3_ANA
1 1
1 1 1 1 C2R10 C3R44 1 1 1 1 1 1 1 1 1 1
C3R26 C3R2 C3R46 C3P26 1 0.1 UF 0.1 UF C3R45 C2R8 C3P13 C3P15 C3R42 C3R32 C3P25 1 C3P10 C3P7 C3P16
0.1 UF 0.1 UF 0.1 UF 0.1 UF C3R50 10% 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF C3P11 0.01 UF 0.01 UF 0.01 UF
10% 10% 10% 10% 0.1 UF 6.3 V 6.3 V 10% 10% 10% 10% 10% 10% 10% 0.1 UF 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 10% 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 16 V 16 V 16 V
2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 2 X7R 2 X7R 2 X7R
402 402 402 402 2 X5R 402 402 402 402 402 402 402 2 X5R 402 402 402
402 402
V_1P2STBY V_1P8_ANA
VAA_3P3STBY_USB
A 1 1 1 1 1 1 1 1 1 1
1
C3R36 1 1 1
A
1 1 1 1 C3R20 C3R7 C3R8 C3R39 C3R15 C3P24 C3R16 C3R19 C3R37 C3P20 0.1 UF C3R31 C3P12 C3P22
C2R7 C3R28 C3R38 C3R21 1 1 1 1 1 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.01 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 10% 0.1 UF 0.1 UF 0.1 UF
0.1 UF 0.1 UF 0.1 UF 0.1 UF C3R11 C2R1 C2R4 C2R5 C2R2 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 6.3 V 10% 10% 10%
10% 10% 10% 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 16 V 16 V 16 V 16 V 16 V 16 V 6.3 V 6.3 V 6.3 V 6.3 V 2 X5R 6.3 V 6.3 V 6.3 V
10% 10% 10% 10% 10% 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X5R 2 X5R 2 X5R 2 X5R 402 2 X5R 2 X5R 2 X5R
6.3 V 6.3 V 6.3 V 6.3 V 402 402 402 402 402 402 402 402 402 402 402 402 402
2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402

[PAGE_TITLE=KSB, DECOUPLING] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, BULK DECOUPLING

D D
V_1P2
V_1P2STBY
C C
1 1 1
C3C8 C4C2 C4C6 1 1
4.7 UF 4.7 UF 4.7 UF C3P36 C3P1
10% 10% 10% 4.7 UF 4.7 UF
6.3 V 6.3 V 6.3 V 10% 10%
2 X5R 2 X5R 2 X5R 6.3 V 6.3 V
603 603 603 2 X5R 2 X5R
603 603
V_3P3 V_3P3STBY
B B
1 1 1 1 1 1 1 1 1
C2P1 C3N43 C2P2 C3N44 C3N42 C3T1 C3R53 C3T2 C3R54
4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF
10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603
A A

[PAGE_TITLE=KSB, BULK DECOUPLING] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, STANDBY POWER + GROUND

D D
U3D1 KSB IC
V_3P3STBY
A1 VSS[0]
9 OF 9 VSS[53] P11
F1 E12
V_3P3STBY_ANA
VSS[1] VSS[54]
H1 VSS[2] VSS[55] H12
K1 VSS[3] VSS[56] J12
M1 VSS[4] VSS[57] K12 FB3R1
P1 VSS[5] VSS[58] L12 1 2
T1 VSS[6] VSS[59] M12
V1 VSS[60] N12 FB 1 V_3P3STBY
VSS[7] V_5P0STBY 0.2A 603 C3R51
Y1 VSS[8] VSS[61] P12 0.5 DCR 4.7 UF
AB1 VSS[9] VSS[62] V12 10%
D2 VSS[63] AB12 2 6.3 V
VSS[10] 1 1 X5R
B3 VSS[11] VSS[64] A13 C3R52 603 IC
J4 VSS[12] VSS[65] J13 R2R4 4.7 UF U3D1 KSB V_1P2STBY
L4 10 KOHM 10%
K13
C N4
VSS[13]
VSS[14]
VSS[66]
VSS[67] L13 5% 2 6.3 V
X5R
603 H5
8 OF 9 C
R4 M13 CH AVDD_33S_BG V_1P8STBY
VSS[15] VSS[68] 402 V13 VDD_3P3_LDO18 1 R3R6 2
U4 N13 VDD_33S_LDO18
VSS[16] VSS[69] 2 P18
Y4 VSS[70] P13 AVDD_33S_JTM 5% 0 OHM
VSS[17] V6 CH 402
D5 R13 VDD_33S[0]
VSS[18] VSS[71]
VAA_3P3STBY_USB_FET_EN
F19 AVDD_33S_FAN VDD_33S[1] V7
K5 VSS[19] VSS[72] C14
VDD_33S[2] E10
M5 VSS[20] VSS[73] D14
AB20 AVDD_33S_PLLB VDD_33S[3] E11
R5 VSS[21] VSS[74] E14
VDD_33S[4] V11
T5 VSS[22] VSS[75] J14
VAA_3P3STBY_USB Y22 AVDD_33S_XTAL VDD_33S[5] V18
V5 VSS[23] VSS[76] K14
C7 VSS[24] VSS[77] L14
J3 AVDD_33S_USB[0] VDD_12S[0] J5
E7 VSS[25] VSS[78] M14
V_3P3STBY L3 AVDD_33S_USB[1] VDD_12S[1] L5
AB7 VSS[26] VSS[79] N14
1 Q2R1 N3 AVDD_33S_USB[2] VDD_12S[2] N5
H8 VSS[27] VSS[80] P14 FET
AO3414L FB2R1 R3 AVDD_33S_USB[3] VDD_12S[3] P5
L8 VSS[28] VSS[81] A15
U3 U5
N8 VSS[29] VSS[82] H15 2 3 SOT23 VAA_3P3STBY_USB_FET 1 2
K4
AVDD_33S_USB[4] VDD_12S[4]
E8
R8 VSS[83] L15 AVDD_33S_USB[5] VDD_12S[5]
VSS[30] FB M4 V8
D9 N15 0.5A 603 1 AVDD_33S_USB[6] VDD_12S[6]
VSS[31] VSS[84] C2R3 P4 E9
J9 R15 0.1DCR AVDD_33S_USB[7] VDD_12S[7] 1
VSS[32] VSS[85] 4.7 UF T4 V10
K9 C16 10% AVDD_33S_USB[8] VDD_12S[8]
VSS[33] VSS[86] 1 R2R3 2 1 M18 R3R2
L9 W16 C2R6 2 6.3 V VDD_12S[9]
VSS[34] VSS[87] X5R U18 0 OHM
M9 VSS[88] AB16 0 OHM 5% 4.7 UF 603 VDD_12S[10] 5% 1
VSS[35] 402 EMPTY 10% C3R35
B N9
P9
VSS[36] VSS[89] V17
A18 2 6.3 V
X5R VDD18S_IN V14 CH
402
0.1 UF
10% B
VSS[37] VSS[90] 603 2
AA9 L18 2 6.3 V
VSS[38] VSS[91] V15 VDD18_OUT_CAP X5R
A10 T18 LDO18_CAP 402
VSS[39] VSS[92]
J10 VSS[40] VSS[93] W18
PBGA404 1
K10 VSS[41] VSS[94] AB18 X850744-001 C3R47
L10 VSS[42] VSS[95] J19 4.7 UF
M10
10%
VSS[43] VSS[96] K19 6.3 V
N10 M19 2 X5R
VSS[44] VSS[97] 603
P10 VSS[45] VSS[98] P19
R10 VSS[46] VSS[99] N20
H11 VSS[47] VSS[100] U20
J11 VSS[48] VSS[101] T21
K11 VSS[49] VSS[102] Y21
L11 VSS[50] VSS[103] R22
M11 VSS[51] VSS[104] AB22
N11 VSS[52]
X850744-001 PBGA404
A A

[PAGE_TITLE=KSB, STANDBY POWER] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB, MAIN POWER V_2P5
V_3P3
V_3P3_ANA
D 1
D
1 FB3P2
V_1P8 C3R49 R3R3
V_1P8_ANA 0.1 UF
10%
0 OHM 1 2
5%
6.3 V FB
IC 2 X5R CH 0.5A 603
FB3P3 U3D1 KSB 402 0.1DCR 1
1 2 2 402 C3P5
3 OF 9 1 4.7 UF
FB C2R9 10%
AVDD_PEX[0] W15 4.7 UF 6.3 V
0.2A 603 1 2 X5R
0.5 DCR C3P8 AVDD_PEX[1] Y17 10%
4.7 UF 1 6.3 V 603
D13 AVDD_18_HDMI[0] AVDD_PEX[2] Y19 C3R48 VAA_3P3_HDMI_FET_EN 2 X5R
10% 4.7 UF
1 6.3 V E13 AVDD_18_HDMI[1] 603
C3R4 2 X5R 10% 1
4.7 UF 603 6.3 V 1 Q2P1
10% 2 X5R R2P6 EMPTY
6.3 V 603 0 OHM AO3414L
2 X5R VDD25_OUT_CAP 5%
603 LDO25_CAP W17 2 3 SOT23 V_5P0
CH
402
2 1 R2P8 2
AVDD_33_PLLA E16
10 KOHM 5%
D15 VAA_3P3_HDMI 402 EMPTY
AVDD_33_HDMI[0]
AVDD_33_HDMI[1] E15
1 R2P7 2 V_VREG_V3P3_V5P0 IN 47
C V_1P2
AVDD_33_ENET G5 10 KOHM
402
5%
EMPTY C
AVDD_33_SATA[0] W3
AVDD_33_SATA[1] AA3 1
AVDD_33_SATA[2] V4 VAA_3P3_VDAC
R3R1
T20
0 OHM V_3P3
AVDD_33_CLK[0] 5%
J8 VDD_12[0] AVDD_33_CLK[1] V20 CH
K8 VDD_12[1] AVDD_33_CLK[2] W21 402
M8 2 FB3P1
VDD_12[2]
P8 VDD_12[3] AVDD_33_VDAC[0] A19 1 2
H9 VDD_12[4] AVDD_33_VDAC[1] C20 300 FB
R9 VDD_12[5] AVDD_33_VDAC[2] E20 0.45 OHM 603 1
H10 B22 C3P4
VDD_12[6] AVDD_33_VDAC[3] 4.7 UF
R11 VDD_12[7] AVDD_33_LDO25 V16 VAA_3P3_LDO25 1
10%
R12 C3P6 6.3 V
VDD_12[8] 2 X5R
H13 VDD_12[9] 4.7 UF 603
10%
V_1P8 H14 VDD_12[10] 6.3 V
1 2 X5R
R14 VDD_12[11] C3R33
J15 4.7 UF 603
V_3P3 VDD_12[12] 10%
K15 VDD_12[13] 6.3 V
M15 2 X5R
VDD_12[14] D19 603
P15 VSS_VDAC[0]
B VDD_12[15]
VSS_VDAC[1] E19
B20 B
J18 VSS_VDAC[2]
VDD_18[0] F20
K18 VSS_VDAC[3]
VDD_18[1] B21
N18 VSS_VDAC[4]
VDD_18[2] C21
R18 VSS_VDAC[5]
VDD_18[3] D21
H19 VSS_VDAC[6]
VDD_18[4] A22
L19 VSS_VDAC[7]
VDD_18[5] E22
VSS_VDAC[8]
C3 VDD_33[0]
VSS_PLLA E17
E5 VDD_33[1]
VSS_PLLB AA20
F5 VDD_33[2]
VSS_PLLA
E6 VDD_33[3]
VSS_PLLB
D17 VDD_33[4]
C18 VDD_33[5]
X850744-001 PBGA404
1
1
R3P17
R3R4 0 OHM
0 OHM 0
0
CH
CH 603
603 2
2
A A

[PAGE_TITLE=KSB, MAIN POWER] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MMC + FLASH
ALL COMPONENTS ON THIS PAGE IS FOR MMC MODE. TO BE STUFFED/UNSTUFFED AT CONFIG LEVEL
V_3P3STBY V_3P3STBY
D V_3P3STBY D
1
1 1 1 1 R1E1
C1E15 C1E14 C1E9 C1E8 1 1 1 2.2 KOHM
0.1 UF 0.1 UF 0.1 UF 2.2 UF C1E16 C1E12 C2E1
10% 10% 10% 10% 4.7 UF 0.1 UF 0.1 UF 5%
6.3 V 6.3 V 6.3 V 6.3 V 10% 10% 10% U1T1 IC CH
2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 402
402 402 402 603 2 X5R 2 X5R 2 X5R
603 402 402 NAND 2 CE 2
RDY2 6
U1E3 IC RDY1 7
37 VCC1
MMC_V12 12 VCC0 NC26 48
PHISON PS8200 V1 NC25 47
39 VCC3IO FAD7 45 MMC_FLSH_DATA7 44 DATA7 NC24 46
1 1
C1E7 C1E10 18 VCCAH FAD6 46 MMC_FLSH_DATA6 43 DATA6 NC23 45
V_3P3STBY 2.2 UF
10%
0.1 UF
10%
14 VCC3IOM FAD5 1 MMC_FLSH_DATA5 42 DATA5 NC22 40
6.3 V 6.3 V FAD4 2 MMC_FLSH_DATA4 41 DATA4 NC21 39
2 X5R 2 X5R 3 4 MMC_FLSH_DATA3 32 38
1 603 402 VCCK FAD3 DATA3 NC20
FAD2 5 MMC_FLSH_DATA2 31 DATA2 NC19 35
1
R1E3 FAD1 6 MMC_FLSH_DATA1 30 DATA1 NC18 34
1 0 OHM
R1E4 7 MMC_FLSH_DATA0 29 33
C OUT 63 R1E2 0 OHM
5%
5% FAD0 DATA0 NC17
NC16 28 C
0 OHM CH 38 10 27
5% 402 FBD7 CE2_N* NC15
CH MMC_SD_SEL 29 37 9 26
402 2 MMC_SD_SEL FBD6 CE1_N* NC14
CH MMC_DV_CARD 28 36 25
402 2 DV_CARD FBD5 NC13
R1R1 2 MMC_EMBED_SEL 30 EMBED_SEL FBD4 35 8 RE_N* NC12 24
26 IN FLSH_CLE 2 1 MMC_RST_N 20 LOCK_RST_N* FBD3 41 18 WE_N* NC11 23
1 KOHM 5% FBD2 42 19 WP_N* NC10 22
402 CH MMC_ISOLT FBD1 43 17 ALE NC9 21
FBD0 44 16 CLE NC8 20
1
DB1R1 MMC_RSTCLK NC7 15
36 VSS1 NC6 14
19 VIOM 13 VSS0 NC5 11
1
FTP FT1R4 49 VDT_FLH XCLK_FCEB3 9 NC4 5
50 TEST_ISOLT XRST_FCEB2 10 NC3 4
1 47 TEST_MODE FCEB1 11 MMC_FLSH_CE1_N NC2 3
FT1R3 FTP
51 TEST_RSTCLK FCEB0 12 MMC_FLSH_CE0_N NC1 2
NC0 1
26 IN FLSH_CE_N 25 CLK
63 26 IN FLSH_WP_N 16 CMD
13 MMC_FLSH_RE_N X853492-001
FLSH_DATA<7..0> FARDB_N*
34 63 32 26 BI 7 23 33 MMC_FLSH_WE_N
DAT7 FAWRB_N*
6 24 DAT6 FAWP_N* 34 MMC_FLSH_WP_N
B 5
4
17
15
DAT5 FAALE 32 MMC_FLSH_ALE
31 MMC_FLSH_CLE B
1 DAT4 FACLE
3 26 DAT3
R1R10 2 27 DAT2
10 KOHM 1 21 DAT1 FARDY 8 MMC_FLSH_READY
1% 0 22 DAT0
EMPTY
402
2 48 NC GNDA 40
NC IN DATASHEET BUT MAYBE
PULL DOWN RESISTOR AS A PROVISION GND IN FUTURE REVISIONS
TO PREVENT CLK GLITCHES IF NEEDED X853009-001 LGA51
REMOVE IN FUTURE FAB REVISIONS
V_3P3STBY V_3P3STBY
V_3P3STBY
DECOUPLING FOR TOSHIBA NAND ONLY
1 1 1 1 1 1 1 1
1
R1R6 R1R7 R1R3 R1R8 R1R4 R1R9 R1R5 R2R2
49.9 KOHM 49.9 KOHM 49.9 KOHM 49.9 KOHM 49.9 KOHM 49.9 KOHM 49.9 KOHM 49.9 KOHM R1R2 1 1 1 1
1% 1% 1% 1% 1% 1% 1% 1% 49.9 KOHM C1E11 C1E13 C2E9 C1E6
CH CH CH CH CH CH CH CH 1% 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
402 402 402 402 402 402 402 402 CH 6.3 V 6.3 V 6.3 V 6.3 V
2 2 2 2 2 2 2 2 402 2 X5R 2 X5R 2 X5R 2 X5R
34 63 32 26 BI FLSH_DATA<7..0> 7 2 402 402 402 402
A 6 63 26 IN
FLSH_WP_N A
5
4
3
2
1
0

[PAGE_TITLE=MMC + FLASH] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB OUT, AUDIO
D D
V_3P3
R3B22
1 2 V_AUD
0 OHM %
805 CH 1 1 1
1 C3B11 C3B12 C3A7
FT3N3 FTP 2.2 UF 0.1 UF 0.1 UF 1 1
10% 10% 10% U3A1 IC C3A6 C3A5
6.3 V 6.3 V 6.3 V 2.2 UF 0.1 UF
2 X5R 2 X5R 2 X5R AUDIODAC_CSS4354_WM1824 10% 10%
603 402 402 6.3 V 6.3 V
2 X5R 2 X5R
6 VCP LINEVDD VBIAS VMID 18 V_AUD_BIAS 603 402
17 VA AVDD
3 VL DBVDD
20 1_2VRMS NC
VFILT_P NC 8 V_AUD_FILT_P
1 1 1
C C3A8
0.15 UF
C3M4
1 UF
C3M6
1 UF C
10% 10% 10%
10 V 16 V 16 V
2 X5R 2 X5R 2 X5R
402 603 603
FLYP_P NC 7 V_AUD_FLYP_P
1
C3N41
2.2 UF FB3A2
10%
6.3 V 1 2 AUD_L_OUT OUT 37
5 V_AUD_FLYP_N 2 X5R
DBPADS ON I2S TO BE PLACED AS CLOSE TO AUDIO DAC AS POSSIBLE FLYP NC 603 0.7DCR
0.2 603
1 R3A10
R3A8 2 10 KOHM
I2S_MCLK 2 15 AUD_VOUTL 1 2 AUD_VOUTL_R C3A4 1%
27 IN MCLK MCLK AOUTA LINEVOUTL 1000 PF
DB3B1 1 10% 2 CH
1.33 KOHM1% 50 V 402
27 IN I2S_BCLK 1 SCLK BCLK 402 CH 1 X7R
DB3A4 1 AOUT_REF NC 14 402
27 IN I2S_WS 23 LRCK LRCLK
DB3A2 1 R3A9 2
C3A3 1 R3A11
27 IN I2S_SD 24 SDIN DACDAT AOUTB LINEVOUTR 13 AUD_VOUTR 1 2 AUD_VOUTR_R 1000 PF 10 KOHM
DB3A3 1 1.33 KOHM1% 10% 1%
B 402 CH 1
50 V
X7R
402
2 CH
402 B
FLYN_P CPCA 9 V_AUD_FLYN_P FB3A1
1
1 2 AUD_R_OUT OUT 37
C3A9 0.7DCR
2.2 UF 0.2 603
10%
6.3 V
11 V_AUD_FLYN_N 2 X5R
FLYN CPCB 603
24 IN AUD_RST_N 19 RESET MUTE
1 R3M6
1 KOHM
5% V_AUD_FILT_N
2 CH VFILT CPVOUTN 12
402
1 1 1
C3A10 C3M2 C3M3
0.15 UF 10 UF 10 UF
10% 10% 10%
10 V 10 V 10 V
22 16 2 X5R 2 X5R 2 X5R
PS_N/LJ AIFMODE AGND AGND 402 805 805
DGND NC 4
21 DEM NC CPGND LINEGND 10
ME GNDPAD 25
X851154-002 QFN25
A A

[PAGE_TITLE=PSB OUT, AUDIO] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KSB OUT, FLASH
D D
ALL COMPONENTS ON THIS PAGE IS FOR MAMD MODE. TO BE STUFFED/UNSTUFFED AT CONFIG LEVEL
I97
V_3P3STBY
V_3P3STBY
2 I96
N: STUFFED AT CONFIG LEVEL R2R1
1 1 2.2 KOHM
1
1 1 1 5%
R2T12 R1D2 C1D1 C1E17 C2T18
R2T13 10 KOHM 10 KOHM 4.7 UF 0.1 UF 0.1 UF CH
1 10 KOHM 5% 5% 10% 10% 10% 402
FT2T12 FTP 5% 6.3 V 6.3 V 6.3 V 1
1 CH CH 2 X5R 2 X5R 2 X5R
FT2T11 FTP EMPTY
1 402 402 603 402 402 U1E2 IC
FT2T10 FTP 402 2 2
1
C FT2T8
FT2T5
FTP
FTP
1
2
NAND FLASH
7 FLSH_READY C
1 RDY OUT 26
FT2T4 FTP
1 2 R2T8 1
FT2T3 FTP NC<27> 38 FLSH_NC38
1
FT2T2 FTP 37 VCC1 NC<26> 48 0 OHM 5%
1 12 VCC0 NC<25> 47 402 EMPTY
FTP FT1R1
32 26 IN FLSH_DATA<7..0> NC<24> 46
63 7 44 DATA<7> NC<23> 45
6 43 DATA<6> NC<22> 40
5 42 DATA<5> NC<21> 39
4 41 DATA<4> NC<20> 35
3 32 DATA<3> NC<19> 34
2 31 DATA<2> NC<18> 33
1 30 DATA<1> NC<17> 28
0 29 DATA<0> NC<16> 27
NC<15> 26
26 IN FLSH_CE_N 9 CE_N* NC<14> 25
26 IN FLSH_RE_N 8 RE_N* NC<13> 24
1 1 1 1 1 1 1 1 26 IN FLSH_WE_N 18 WE_N* NC<12> 23
19 WP_N* NC<11> 22
R2T14 R2T11 R2T10 R2T9 R2T7 R2T6 R2T2 R2T1
10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 26 IN FLSH_ALE 17 ALE NC<10> 21
5% 5% 5% 5% 5% 5% 5% 5% 26 IN FLSH_CLE 16 CLE NC<9> 20
15
B CH
402
EMPTY
402
CH
402
CH
402
CH
402
CH
402
CH
402
CH
402 6 VSS/NC
NC<8>
NC<7> 14 B
2 2 2 2 2 2 2 2 36 11
VSS1 NC<6>
13 VSS0 NC<5> 10
NC<4> 5
NC<3> 4
NC<2> 3
63 26 IN FLSH_WP_N NC<1> 2
NC<0> 1
1 R1D1
10 KOHM
5%
CH
2 402 X818098-001 TSOP
NAND BOOTSTRAP FOR KSB
FLSH_DATA[1:0] FLASH CONFIGURATION

0X0 0.5KB, 16KB BLOCKS, 128MBIT RETAIL
A 0X1 0.5KB, 16KB BLOCKS, 512MBIT RETAIL A
0X2 2KB PAGES, 128KB BLOCKS, 1/2/4 GBIT XDK
0X3 4KB PAGES, 256KB BLOCKS, 2/4/8 GBIT XDK

[PAGE_TITLE=PSB OUT, FLASH] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, INFARED + SWITCHES + AUDIBLE F/B
D D
TILT SWITCH, SOLICO

V_3P3STBY
1 R2V2
SM 10 KOHM
TILT 5%
SW5G2 2 CH
SM 402
4 1 R2V3
3 2 TILTSW_N_R 2 1 TILTSW_N OUT 25
10 KOHM 5%
X800550-004 402 CH
C C
IR MODULE V_3P3STBY
U1F4
R6G1
V_IR 1 2
1
49.9 OHM 1%
402 CH TH
C6G4
1
C6G5 2 R3R11 X850477-001 POWER BUTTON 2
4.7 UF 0.1 UF 10 KOHM SWITCH
10% 10% 5%
6.3 V 6.3 V
X5R 2 X5R 1 CH
603 402 402 TH
U6G1 IC
SW3G1
IR THR
4 1 PWRSW_N_R OUT 38
VCC 3 3 2
B DATA 1
2
IR_DATA OUT 25
B
GND
ME2 5
ME1 4
X821027-001
1
FTP FT1U2
V_3P3STBY
AUDIBLE FEEDBACK 1
FTP FT1U1
U3G4 IC J1F1
1X2HDR
14 VCCO ISD2130 SPK_P 7 SPKR_DRIVE_P 1
10 VCCD_PWM1 SPK_N 9 SPKR_DRIVE_N 2
6 VCCD_PWM0 INTB/GPIO3 11
1 1 1 1 1 20 NC5 RDY/BSYB/GPIO4 12 TH
C3G13 C3V5 C3V4 C3G14 C3V6 19 15 HDR
4.7 UF 0.01 UF 1000 PF 4.7 UF 0.1 UF NC4 GPIO5
10% 10% 10% 10% 10% 2 18 NOTE: SPEAKER HEADER
SCLK/GPI1 NC3
16 V 16 V 50 V 16 V 6.3 V 4 1
2 X5R 2 X7R 2 X7R 2 X5R 2 X5R MOSI/GPIO0 MISO/GPIO2 EJECTSW_N
1206 402 402 1206 402 3 17 IN 38
SSB NC2
8 VSSD_PWM NC1 16 AUD_RDY_BSBY IN 24
5 VSSD NC0 13
21
PWRSW_N IN 38
A
GND
AUD_SPI_MISO OUT 24
A
24 IN AUD_SPI_CLK
QFN21 X851696-002
24 IN AUD_SPI_MOSI
24 IN AUD_SSB
DRAWING MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=CONN,INFRARED+SWITCHES+AUDIBLE F/B] Thu Feb 17 10:12:27 2011
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, FAN
V_3P3STBY
V_3P3 1 R5A17
D 4.75 KOHM
1%
D
2 EMPTY
402
1 R5A16
4.75 KOHM
1%
2 CH
402
V_12P0
R4A7
2 1
R5M17
5.11 KOHM 1% 1 2 FAN_TACH 24 25
402 EMPTY 3 V_12P0 OUT
0 OHM 5%
Q5A2 402 CH
FAN1_Q1_C MJD210
1
FAN_PULLUP
EMPTY
3 2
1 C6A7 1
23 IN FAN1_OUT 1 Q4A1 3 100 UF C6A8
20% 1 UF
EMPTY D4A1 16 V 10%
2 1N4148 16 V
2 EMPTY
C SOT23
1 EMPTY
RDL 2 X5R
603 C
J6A5
FAN1_Q1_E
2 1X4HDR
C4N5
2700 PF 1
10%
50 V 2
1 EMPTY 3
402 R5A9
V_FAN1 1 2 4
2 R4A1
100 OHM 0 OHM %
5% 805 EMPTY 1 HDR
C5A15
1 EMPTY 1 UF
402 10%
16 V
2 EMPTY
FAN1_FDBK_R
1 R5M5 603
30.1 KOHM
1%
2 EMPTY
402
R5M3
2 1
5.11 KOHM1% FAN1_FDBK OUT 23
402 EMPTY
1 R5M4
B 11 KOHM
1% B
2 EMPTY
402
FAN CONTROL
R5A10
25 IN SMC_PWM1 SMC_PWM1_R
33 OHM 5%
402 CH
A A

DRAWING
[PAGE_TITLE= CONN, FAN] Thu Feb 17 10:12:28 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_5P0
1
RT3A1
2
CONN, AVIP DAC STANDARD ADVANCED SDTV HDTV SCART VGA
V_AVIP OUT 39 40
01.10 A THRMSTR 1
1206 C2A8
4.7 UF
C3A12
470 PF
A N/A Y(LUMA) Y Y G G
DBPAD ON SPDIF TO BE PLACED AS CLOSE TO CONN AS POSSIBLE 10% 5% J4A2 CONN
D 27 IN 2
6.3 V
X5R
50 V
X7R XENON AVIP CONNECTOR B N/A C(CHROMA) PR PR R R D
1
603 402 29
1 EG3A6 V_AVIP
C3A13 X807267-001 27 V_AVIP_RET
22 PF ESDB-MLP7
5% C N/A N/A PB PB B B
50 V DIO 37 IN VID_DACA_OUT 4 VID_DACA_OUT
2 NPO 2
402 402 VID_DACA_RET
D CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS
2
37 IN VID_DACB_OUT 3 VID_DACB_OUT
1 VID_DACB_RET
EXT_PWR_ON 30 EXT_PWR_ON_N OUT 62 63 25 37 64
37 IN VID_DACC_OUT 8 VID_DACC_OUT
6 VID_DACC_RET DDC_CLK 21 HDMI_DDC_CLK BI 23 40 55
V_12P0 DDC_DATA 23 HDMI_DDC_DATA BI 23 40 55
37 IN VID_DACD_OUT 7 VID_DACD_OUT
5 VID_DACD_RET AV_MODE2 28 AV_MODE2 OUT 25 37 V_3P3STBY
AV_MODE1 24 AV_MODE1 OUT 25 37
VID_HSYNC_OUT 11 20 AV_MODE0
402 1% CH
37 IN VID_HSYNC_OUT AV_MODE0 OUT 25 37
1.82 KOHM
9
1
VID_HSYNC_RET
R3A5
GND<2> 26
1 R3P5 1 R2N1 1 R3N6 1 R2C3
37 IN VID_VSYNC_OUT 12 VID_VSYNC_OUT GND<1> 22 10 KOHM 10 KOHM 10 KOHM 10 KOHM
2
10 VID_VSYNC_RET GND<0> 18 5% 5% 5% 5%
DB3A1 1 2 CH 2 CH 2 CH 2 CH
R3A3 WSS_CNTL_B
SPDIF_OUT 25 34 EXT_PWR_ON_N 402 402 402 402
WSS_CNTL1 1 2 Q3A1 SPDIF SHIELD<3> 63 62 37 IN
C 24 IN
5.36 KOHM 1%
3 6
AUD_R_OUT 15
SHIELD<2> 33
32
37 IN AV_MODE2
AV_MODE1 C
402 CH 33 IN AUD_R_OUT SHIELD<1> 37 IN
5 2 13 AUD_R_RET SHIELD<0> 31 37 IN AV_MODE0
33 IN AUD_L_OUT 16 AUD_L_OUT MTGB<8-1> 1 1 1 1
R3A4 14
24 WSS_CNTL0 1 2 4 1
XSTR AUD_L_RET MTGA<8-1> C3A2
470 PF
C2M2
470 PF
C2M1
470 PF
C2C2
470 PF
IN R3A2 5% 5% 5% 5%
2 WSS_CNTL_E
4.75 KOHM 1% WSS_CNTL_OUT_R 2 1 WSS_CNTL_OUT 17 WSS_CNTL 50 V 50 V 50 V 50 V

402 CH 19 2 X7R 2 X7R 2 X7R 2 X7R
1 KOHM 5% SCART_RGB
10 KOHM 5%
402 402 402 402

301 OHM 1%
CH
402 CH
2
CH
2
R3A6
R3A1
C3A1 X856166-001 TH
75 PF LAYOUT:PLACE CLOSE TO CONNECTOR
5%
603
V_3P3 50 V
402
1
1 NPO EMI CAPS

402
SCART_RGB_OUT
R3C25 R3C24
23 IN VID_VSYNC_OUT_R 1 2 VID_VSYNC_OUT OUT 37 23 IN VID_HSYNC_OUT_R 1 2 VID_HSYNC_OUT OUT 37
R2M2 2 49.9 OHM 1% 49.9 OHM 1%
SCART_RGB 2 1 1 Q3M1
1
24 IN SCART_RGB_R 402 CH 402 CH
EG4A9 EG4A10
10 KOHM 5% XSTR X807267-001 X807267-001
402 CH 3 R3M7
B SCART_RGB_OUT_R 1 2 ESDB-MLP7
DIO
ESDB-MLP7
DIO B
402 5% CH
33 OHM 5%
1
402 402
10 KOHM
1
R3M2
402 CH
C3M1
2
0.01 UF
10%
2
16 V
2 X7R
402
VID_DACA_DP L4A4 L4A2

1 R4A11 2 VID_DACA_DP_L 1 2 VID_DACA_OUT VID_DACC_DP 1 R4A12 2 VID_DACC_DP_L 1 2 VID_DACC_OUT
23 IN OUT 37 23 IN OUT 37
4.75 OHM 1% .27 UH IND 4.75 OHM 1% BAV99 .27 UH IND
BAV99 BAV99 BAV99
3
402 CH 402 CH V_1P2 DIO
6
3
V_1P2 0.45 A 1210 V_1P2 0.45 A 1210 V_1P2
1
DIO DIO DIO
1
360 1 R4A3 EG4A6 360

1 R4A5 EG4A8 1 1
X807267-001
U4M1
X807267-001 1 1 75 OHM C4A8 C4A5
U4M1
U4A2
U4A2
75 OHM C4A10 C4A3 1% ESDB-MLP7
1% ESDB-MLP7 62 PF 33 PF
62 PF 33 PF 2 CH DIO 5% 5%
2 CH DIO 5% 5% 50 V 50 V
50 V 50 V 402 402 2 2
4
402 402 2 2 NPO NPO
2
4
NPO NPO 402 402
2
402 402
2
L4A3 L4A1
VID_DACB_DP 1 R4A10 2 VID_DACB_DP_L 1 2 VID_DACB_OUT VID_DACD_DP 1 R4A9 2 VID_DACD_DP_L 1 2 VID_DACD_OUT
23 IN OUT 37 23 IN OUT 37
4.75 OHM 1% .27 UH IND BAV99 4.75 OHM 1% BAV99 .27 UH IND BAV99
402 CH 402 CH
A
3
6
0.45 A 1210 V_1P2 V_1P2 0.45 A 1210 V_1P2
1
A BAV99 DIO DIO DIO
1
360 360
3
V_1P2 DIO EG4A5

EG4A7 1 R4A2 2 2
1 R4A4 1 V_1P2 X807267-001 C4A7 C4A4
X807267-001
U4A1
U4M2
U4A1
1 C4A6 75 OHM ESDB-MLP7
75 OHM ESDB-MLP7 C4A9 1% 62 PF 33 PF
U4M2
1% 33 PF DIO 5% 5%
DIO 62 PF 5% 2 CH 50 V 50 V
2 CH 5% 50 V 402 1 NPO 1 NPO
402 50 V 2 402
5
1
402 2 NPO 402 402
NPO
2
402
5
1 1
2
402
C4M3 C4M2
0.1 UF 0.1 UF
10% 10%
25 V 25 V
2 X5R 2 X5R
402 402

DECOUPLING FOR BAV99DW
[PAGE_TITLE=[CONN, AVIP] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, RJ45 USB AUX COMBO + BORON + PWR
V_12P0
RJ45 AUX COMBO J2A1 CONN
RT3A2 TRINITYRJ45AUX
1 2 17
V12P0_EXPPORT_RJ45 V12P0
18
D 01.50 A THRMSTR C3A14
100 UF
C2A11
470 PF
C2A12
4.7 UF
GND3
D
1812 20% 5% 10%
1 16 V 50 V 16 V
FT2M2 FTP ELEC X7R X5R
RDL 402 805
V_5P0
RT2A1 J2A1.16 HAS A DFM REQUIREMENT
2 1 FOR THIEVING PADS 16
V5P0_EXPPORT_RJ45 V5P0
1 C2B3 15 GND2
01.10 A THRMSTR 2 2
220 UF C2A14 C2A5 A DFM REQUIREMENT
1206 20% 470 PF 4.7 UF 19
1 10 V 5% 10% OF THIEVING PADS SPARE2
FT2M1 FTP 50 V 6.3 V DFM_THIEVING_PADS_REQUIREMENT3 20 SPARE3
2 ELEC
RDL 1 X7R 1 X5R
402 603 EXPPORT_RJ45_DN 13
26 BI D-
26 EXPPORT_RJ45_DP 14 D+
BI
1
EG2A3 EG2A2 12 SPARE1
X807267-001 X807267-001 1
ENET_TX_DP LED_LEFT_A
27 IN ESDB-MLP7 ESDB-MLP7 2 LED_LEFT_C
1
1 R2A2 DIO DIO
EG2A4
49.9 OHM 402 402 3
1% X807267-001 LED_RIGHT_A
4
2
ESDB-MLP7 LED_RIGHT_C
2 CH C2A7
402 ENET_TX_TERM 1 2 EMPTY
1 R2A3 402
C 49.9 OHM 0.1 UF 10%
C
2
1% 6.3 V 11 TD+
X5R 10
2 CH 402 TCT
27 IN ENET_TX_DN 402 7 TD-
27 IN ENET_RX_DP 9 RD+
1 R2A4 6
1
RCT
49.9 OHM EG2A5 EG2A6 5
1% RD-
X807267-001 X807267-001
2 CH C2A6 ESDB-MLP7 ESDB-MLP7 V_3P3
402 ENET_RX_TERM 1 2 EMPTY EMPTY FB2M1
2 1 8 GND1
1 R2A5 402 402 V_ENET_CT
49.9 OHM 0.1 UF 10%
6.3 V 1 FB 1
2
2
1% C2M6 0.5A 603 C2M5 C2M3 C2M4
X5R 4.7 UF 4.7 UF 0.1 UF 0.1 UF
2 CH 402 10% 0.1DCR 10% 10% 10%
402 6.3 V 6.3 V 6.3 V 6.3 V 21 EMI1
27 IN ENET_RX_DN X5R X5R X5R X5R 22
1
2 603 2 603 402 402 EMI2

EG2A7 23 EMI3
X807267-001 24 EMI4
ESDB-MLP7
EMPTY
402
X820106-001 TH
BORON FPM
2
B V_3P3STBY
CONN
J5G2 B
ST7A1
BORON CONN 2 1 VREG_V12P0_ISENSE_N 58
12
OUT
V_3P3STBY
1 R4G5 1 R3V6 1 R4G4 1 C5G1 SHORT
100 KOHM 100 KOHM 100 KOHM 2 C5G2
5%
2 CH
5%
CH
2 402
5%
2 CH
100 UF
20%
16 V
470 PF
5%
50 V
POWER 1
R7A1
2 2
ST7A2
1 VREG_V12P0_ISENSE_P
OUT 58
402 402 2 ELEC
RDL 1 X7R
402
10 MOHM
SHORT
1%
2512
26 BORONFPMPORT_DN 5 D- 1 CH J7A1 CONN
BI BORONFPMPORT_DP 6
DB6M2
1
V_12P0
26 BI D+ DB6M3 TRINITY PWR
1 R7A2
DB6N1
1 1 2 V_12P0_IN 5 V12P01
R4G6 4 SPARE1 FT7N1 FTP
10 MOHM 6 V12P02
25 OUT BINDSW_N 1 2 BINDSW_N_R 13 BINDSW_N 1 C7B2 1 C7A3 1 C7A2 1 C7A1 1 C7A4 7
470 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1% V12P03
10 KOHM 1% R4V1 20% 10% 10% 10% 10% 2512 8 V12P04
BRD_TEMP_N 402 CH 1 2 7 16 V 25 V 25 V 25 V 25 V
BRD_TEMP_N_R FP_TEMP_N CH
2 POLY
61 23 OUT X7R X7R X7R X7R
TH 2 603 2 603 2 603 2 603
0 OHM 5%
402 CH 1 FP_TEMP_P
R6A6
R4V2 25 IN PSU_V12P0_EN 1 2 PSU_V12P0_EN_R 9 PSU_EN
61 IN BRD_TEMP_P 1 2 BRD_TEMP_P_R 1 R6A5 100 OHM 5% 1 1
R3V2 10 KOHM 402 CH C6A2 C6A3
0 OHM 5% 8 FP_PWR 5%
35 25 PWRSW_N 402 CH 10 KOHM 1 2 5% 0.1 UF 470 PF
OUT 402 CH V_5P0STBY 2 CH 10% 5%
402 6.3 V 50 V
PWRSW_N_R 2 X5R 2 EMPTY
35 IN 402 402
EJECTSW_N R4G7
A 35 25 OUT 2 1 EJECTSW_N_R 10 ODD_EJECT FT6M1 FTP
1
DB6M1
1
1
R6B1
2 I150 10
A
10 KOHM 5% V5P0STBY_CONN VSB5P0
25 BI BORONFPM_DATA 402 CH 2 C_DATA 1 C6A5 1 C6A4 1 100 MOHM 1%
25 BI BORONFPM_CLK 3 C_CLK 100 UF 100 UF C6A1 805 CH 1 GND1
20% 20% 470 PF ST6B1 2
16 V 16 V 5% 2 1
V5P0STBY_ISENSE_P GND2
2 2 C5G4 2 C5G3 9 OUT 59 3
GND1 50 V GND3
C5G5 470 PF 470 PF 11 2 ELEC
RDL 2 ELEC
RDL 2 X7R 4
470 PF 5% 5% GND2 402 SHORT GND4
N: BORONFPMPORT_DX IS A USB DIFFERENTIAL PAIR. 5% 50 V 50 V 14 ME1 11 ME1 MTGA[9..1]
50 V X7R X7R 15 12
1 X7R 1 402 1 402 ME2 ST6B2 ME2 MTGB[9..1]
402 16 ME3 2 1 V5P0STBY_ISENSE_N 59
17
OUT
ME4 X819467-003 TH
SHORT
X819886-001 TH PROJECT NAME PAGE FAB REV
MICROSOFT
DRAWING
[PAGE_TITLE=CONN, RJ45 AUX COMBO + BORON + PWR] Thu Feb 17 10:12:28 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, USB + MEM PORTS + TOSLINK + WAVEPORT
N: ALL DIFFERENTIAL PAIRS ON THIS PAGE ARE USB DIFFERENTIAL PAIRS. TH
V_5P0DUAL J1A2 CONN
V_5P0DUAL
USB TRIPLE
D RT6G1
HORIZONTAL DUAL USB VERTICAL TRIPLE USB CONN
D
2 1 V_GAMEPORT1 RT2M1
01.10 A THRMSTR 1 C6G1 2 C6G2 2 C6G3 2 1 V_EXPPORT_DUAL1 1 V+
1206 220 UF 470 PF 4.7 UF
20% 5% 10% 01.10 A THRMSTR
10 V 50 V 6.3 V 2
1206
2 ELEC
RDL 1 X7R
402 1 X5R
603
1 C2B1
220 UF
2
C1A8
C2M7
4.7 UF
20% 470 PF 10%
10 V 5% 6.3 V
50 V 1
GAMEPORT1_DN 2 ELEC 1 X5R
26 BI RDL X7R
402
603 BOTTOM PORT
26 BI GAMEPORT1_DP
1
1
EG6G1 EG6G2
X807267-001 X807267-001
ESDB-MLP7 ESDB-MLP7
J6G1 USB
DIO DIO USBX2 26 EXPPORT_PORT1_DN 2 DATA -
V_5P0DUAL 402 402 1 VBUS BI EXPPORT_PORT1_DP 3
2 26 BI DATA +
D- 4
2
2
3 GND
D+
1
4 GND EG1A8 EG1A7
RT7V1
X807267-001 X807267-001
2 1 V_GAMEPORT2 5 VBUS ESDB-MLP7 ESDB-MLP7
1 C7G1 6 D- DIO DIO
01.10 A THRMSTR 2 C7G2 2
220 UF 470 PF C7V1 7 D+ 402 402
1206
C 20%
10 V
5% 4.7 UF
10%
8 GND V_5P0DUAL
C
2
50 V
6.3 V
2 ELEC
RDL 1 X7R
402 1 X5R 9
603 ME
10 ME
RT2M2
26 BI GAMEPORT2_DN X820108-001 TH 2 1 V_EXPPORT_DUAL2 5 V+
26 BI GAMEPORT2_DP
01.10 A THRMSTR
1
1206 1 C2A9 2 2
EG7G1 EG7G2 220 UF C1A9 C1M1
X807267-001 X807267-001 20% 470 PF 4.7 UF
ESDB-MLP7 ESDB-MLP7 10 V 5% 10%
50 V 6.3 V
DIO DIO 2 ELEC 1 1
402 402
RDL X7R
402
X5R
603 MIDDLE PORT
2
V_3P3 WAVE PORT 26

26
BI
BI
EXPPORT_PORT2_DN
EXPPORT_PORT2_DP
6
7
DATA -
DATA +
8 GND
R1A1 VCC_WAVEPORT
1
1 2 EG1A4 EG1A3
B 0 OHM 5%
402 CH 2 2
X807267-001 X807267-001
B
FB1A1 C1A7 C1A1 ESDB-MLP7 ESDB-MLP7
1 2 470 PF 4.7 UF DIO DIO
5% 10% V_5P0DUAL 402 402
EMPTY 50 V 6.3 V
0.5A 603 X7R 1 X5R 1 J1A1 CONN
2
0.1DCR 402 603 wavereceptacle
1 VCC GND1 2 RT1A1
26 BI WAVEPORT_DN 3 D- GND2 5 2 1 9
WAVEPORT_DP 4 7
V_EXPPORT_DUAL3 V+
26 BI D+ EMI1
6 TBD EMI2 8 01.10 A THRMSTR
ME1 9 1206 1 C1A3 2 2
1
EG1A1 EG1A2 220 UF C1A6 C1A2

X820104-002 TH 20% 470 PF 4.7 UF
X807267-001 X807267-001 10 V 5% 10%
ESDB-MLP7 ESDB-MLP7 50 V 6.3 V
2 ELEC
RDL 1 X7R 1 X5R
EMPTY EMPTY 402 603
402 402
TOP PORT
2
26 BI EXPPORT_PORT3_DN 10 DATA -
TOSLINK J4A1
TOSLINK
CONN 26 BI EXPPORT_PORT3_DP 11
12
DATA +
GND
1
37 IN V_AVIP 2 VCC EG1A6 EG1A5
A 27 IN SPDIF_OUT 3
1
VIN X807267-001 X807267-001
13
A
GND ESDB-MLP7 ESDB-MLP7 EMI1
1
EG4A1 DIO DIO 14 EMI2

1
C4A1 X807267-001 4 EMI1 402 402 15 EMI3
22 PF ESDB-MLP7 5 EMI2 16 EMI4
5%
2
50 V DIO
2 NPO
402 402
X802398-001 TH
2
X820107-001

DRAWING
[PAGE_TITLE=CONN, MEMORY PORTS + GAME PORTS] Thu Feb 17 10:12:28 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1
FT3M7 FTP
FT3M1 FTP
1 CONN, HDMI
23 IN HDMI_TX2_DP
23 IN HDMI_TX2_DN
1
D FT3M2 FTP
1 EG3A2
X807267-001
EG3A1
X807267-001
D
1 ESDB-MLP7 ESDB-MLP7
FT3M8 FTP DIO DIO
402 402
2
1
FT3M9 FTP
1
FT3M3 FTP
23 IN HDMI_TX1_DP
23 IN HDMI_TX1_DN
1
EG3A4 EG3A3
1 X807267-001 X807267-001
FT3M4 FTP ESDB-MLP7 ESDB-MLP7
1 DIO DIO
FT3M10 FTP 402 402
2
1
FT3M11 FTP
1
C FT3M5 FTP J3A1 HDR
C
HDMI
23 IN HDMI_TX0_DP 1 TMDS_DATA2_DP
2 TMDS_DATA2_SHD
23 IN HDMI_TX0_DN 3 TMDS_DATA2_DN
4
1
1
1 TMDS_DATA1_DP
FT4M2 FTP EG4A2 EG3A5 5 TMDS_DATA1_SHD
1 X807267-001 X807267-001 6
FT4M7 FTP TMDS_DATA1_DN
ESDB-MLP7 ESDB-MLP7 7 TMDS_DATA0_DP
DIO DIO 8 TMDS_DATA0_SHD
402 402 9 TMDS_DATA0_DN
10
2
2
TMDS_CLK_DP
11 TMDS_CLK_SHD
1 12 TMDS_CLK_DN
FT4M8 FTP
1 HDMI_CEC 13 CEC
1 DB3M1
FT4M3 FTP 14 RESERVED
15 SCL
16 SDA
23 IN HDMI_TXC_DP 17 DDC_CEC_GND
23 IN HDMI_TXC_DN 18 5VCC
19 HOT_PLUG_DET
1
1
EG4A3 23
B FT4M4 FTP
1 EG4A4
X807267-001
X807267-001 22
ME4
ME3 B
1 ESDB-MLP7 21
FT4M9 FTP ESDB-MLP7 ME2
DIO 20
DIO ME1
402
402
2
X806395-002
2
V_5P0STBY
1
FTP FT4M6
R4M6
1 R4M2 1 R4M1 HDMI_HPD_PIN 1 2 HDMI_HPD OUT 23
1 2 KOHM 2 KOHM
FT4M5 FTP 1% 1% 10 KOHM 5%
402 CH
2 CH 2 CH
402 402
1
37 23 IN HDMI_DDC_CLK 1 R4M5 EG4M5
55 37 23 HDMI_DDC_DATA 47.5 KOHM X807267-001
BI 1%
ESDB-MLP7
1
2 CH
EG4M2 EG4M1 402 DIO
1 X807267-001 X807267-001 402
FT4M1 FTP
ESDB-MLP7 ESDB-MLP7
2
DIO DIO
402 402
2
A A
37 IN V_AVIP
1
C3A11
0.1 UF
10%
6.3 V
2 X5R
402

[PAGE_TITLE=CONN, HDMI] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, ODD + HDD
C1B11
27 IN HDD_TX_DP 1 2 HDD POWER
D 0.01 UF 10% V_5P0
D
16 V
X7R
402 J1B3
HDD_TX_DP_C
RT1B2 1X4HDR
1 2 V_HDD 1
HDD_TX_DN_C
2
1
EG1B4 01.50 A THRMSTR 1 1 3
1
C1A4 C1B5
HDD_TX_DN 1
C1B10
2
EG1B3 X807267-001 HDD SATA 1206
4.7 UF
10%
0.1 UF
10%
4
27 IN X807267-001 ESDB-MLP7
6.3 V 6.3 V
ESDB-MLP7 DIO J1B2 2 X5R 2 X5R HDR
0.01 UF 10% 603 402
16 V DIO 402 1X7SATA
X7R 402 9
2
402
2
1
2
3
4
5
C1B7 6
27 HDD_RX_DN 1 2 7
OUT
0.01 UF 10% 8
16 V
C X7R
402 CONN C
HDD_RX_DN_C
HDD_RX_DP_C
1
1
C1B8 EG1B1 EG1B2
27 HDD_RX_DP 1 2
OUT X807267-001 X807267-001 1
FTP FT1N8
0.01 UF 10% ESDB-MLP7 ESDB-MLP7
16 V DIO DIO
X7R
402 402 402
2
ODD POWER DECOUPLING

B V_12P0 V_5P0 V_3P3 B
1
C5A6 C5A8 C5A11 C5A7 C4A14 C5A14
4.7 UF 0.1 UF 4.7 UF 0.1 UF 4.7 UF 0.1 UF
ODD SATA 10%
16 V
10%
25 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
2 X5R X7R X5R X5R X5R X5R
C1B4 805 603 603 402 603 402
27 ODD_TX_DP 1 2 ODD_TX_DP_C
IN
0.01 UF 10%
16 V
X7R
402
C1B3 J1B1
ODD_TX_DN 1 2
27 IN ODD_TX_DN_C
1X7SATA
9
ODD POWER AND CONTROL
0.01 UF 10%
16 V
X7R 1
402 2
3 R4A6
4 25 OUT TRAY_STATUS 1 2 TRAY_STATUS_R
C1B1
27 ODD_RX_DN 1 2 ODD_RX_DN_C 5 100 OHM 5%
OUT 6 402 CH
0.01 UF 10% 7 V_3P3
16 V J4A3
2X6HDR2
X7R 8
V_5P0 1
402 V_12P0 4 3 TRAY_OPEN
A C1B2 CONN 6 5
IN 25
A
27 ODD_RX_DP 1 2 ODD_RX_DP_C 8 7 1
OUT 10 9 C4A11
0.01 UF 10% 75 PF
16 V 12 11 5%
X7R 50 V
2 NPO
402 1 CONN 402
FTP FT1M5

[PAGE_TITLE=CONN, ODD + HDD + MU] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREG, BLEEDERS
D D
V_5P0STBY V_12P0
C V_5P0DUAL
C
1 R6M7 1 R6M5
2.2 KOHM 2.2 KOHM V_12P0 1
DB1E1
5% 5%
2 CH 2 CH
402 402 1 R1T7 1 R1T6 1 R1T3
R6M6 3 10 KOHM 20 OHM 20 OHM
1 2 BLEEDER_V12P0_B2 1 Q6A3 5% 5% 5%
2 CH 2 CH 2 CH
549 OHM 1% XSTR 402 1206 1206
402 CH 24
BLEEDER_V12P0_C1
BLEEDER_V12P0_C2
BLEEDER_V12P0_LOAD
1 R5M2 1 R5M8 1 R5M1 1 R5M7
BLEEDER_C1
BLEEDER_C2
10 OHM 10 OHM 10 OHM 10 OHM
1% 1% 1% 1%
3 2 CH 2 CH 2 CH 2 CH
Q6M2
FET 805 805 805 805
1 3
3.2 OHM
2 SOT23 1 Q1T2
3
R6A3 XSTR
25 IN PSU_V12P0_EN 2 1 BLEEDER_V12P0_B1 1 Q6M3 3 2
B 2.2 KOHM 5%
402 CH
XSTR 22 IN SMC_RST_N 2
R1T1
1 BLEEDER_B 1 Q1T1 B
2
10 KOHM 5% XSTR
R6A4 402 CH 2
22 IN V12P0_PWRGD 2 1
2.2 KOHM 5%
402 CH
V_5P0DUAL BLEEDER
V_12P0 & V_5P0 BLEEDERS
A A

DRAWING
[PAGE_TITLE= VREGS,_BLEEDERS] Thu Feb 17 10:12:29 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, INPUT + OUTPUT FILTERS
D R7P3
D
2 IN CPU_VREG_APS6 1 2 6
R7P4 0 OHM 5%
CPU_VREG_APS5 1 2 402 CH
2 IN 5 VID CODE=1.050V
0 OHM 5% R7P5
CPU_VREG_APS4 402 CH 1 2 4
2 IN
0 OHM 5% V_MEM
R7P6 402 CH
2 IN CPU_VREG_APS3 1 2 3
0 OHM 5% R7P7
CPU_VREG_APS2 402 CH 1 2 2
2 IN
0 OHM 5% 1 R7C15 1 R7C16 1 R7C17 1 R7C18 1 R7C19 1 R7C20
R7P8 402 CH 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM
2 IN CPU_VREG_APS1 1 2 1 5% 5% 5% 5% 5% 5%
0 OHM 5% 2 CH 2 EMPTY 2 CH 2 CH 2 EMPTY 2 CH
402 CH 402 402 402 402 402 402
6 5 4 3 2 1 VREG_CPU_VID<6..1> OUT 44 64
C C
V_12P0
4.2 V_CPUCORE INPUT FILTER
L6B1
V_VREG_CPU OUT 44 45
450 NH IND
9 A TH
1 C6B1 C7B3 1 1
C7B1 470 UF 470 UF C6B3 C6B5
4.7 UF 20% 20% 4.7 UF 4.7 UF
10% 16 V 16 V 10% 10%
16 V POLY POLY 16 V 16 V
2 X5R TH TH 2 X5R 2 X5R
1206 1206 1206
B B
1
DB6R2
1
DB6R1
V_CPUCORE V_CPUCORE OUTPUT FILTER 1
FTP FT6R2
OUT
C6C3 C6C1 C5C3 C6C2 C7C12 C7C13

820 UF 820 UF 820 UF 820 UF 820 UF 820 UF
20% 20% 20% 20% 20% 20%
2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
POLY POLY POLY POLY POLY POLY
RDL RDL RDL RDL RDL RDL
A A

[PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, CPU CONTROLLER
R7C11
43 IN V_VREG_CPU 1 2 VREG_CPU_VCC OUT 44
681 OHM 1%
603 CH R7B5 RRAMP R7C4 1 1
1 2 VREG_CPU_RAMPADJ_R 1 2 C7C10 C7C11 VREG_CPU_VCC3_3P3
1 4.7 UF 1 UF
D FT3P8 FTP R7C12
1 2 1 KOHM 5%
402 CH
422 KOHM 1%
402 CH
10%
16 V
10%
16 V 1
C7C9
R7C13 2 D
2 X5R 2 X5R 10 KOHM
25 VREG_CPU_EN 681 OHM 1% 2 1206 603 0.1 UF 5%
IN 603 CH C7P2 10%
1 R7C10 0.1 UF 6.3 V U7C1 IC CH 1
10% 2 X5R 402
10 KOHM 25 V 402 NCP4201
5% 1 X7R 1 40 VREG_CPUCORE_PWRGD
603 VCC3 PWRGD OUT 25
2 CH 30
402 VCC
VID7 31
11 32 6
VREG_CPU_VID<6..1> IN 43
VREG_CPU_RAMPADJ RAMPADJ VID6
VID5 33 5
6 EN/VTT VID4 34 4 VID'S HAVE INTERNAL PULL DOWNS
VID3 35 3
55 IN PMBUS_CLK 5 SCL VID2 36 2
60 59 58 57 56 55 BI PMBUS_DATA 4 SDA VID1 37 1
64 VID0 38
R7C7 1 22
VREG_CPU_PHASE2 1 2 DB7C2
VREG_CPU_SW4 SW4
45 IN 1 23 39
DB7C3
VREG_CPU_SW3 SW3 PSI_N*
0 OHM 5% R7C9 VREG_CPU_PHASE2_R 24 SW2
VREG_CPU_PHASE1 402 CH 1 2 25 26 VREG_CPU_VCC
45 IN VREG_CPU_PHASE1_R SW1 PWM4 OUT 44
0 OHM 5% PWM3 27
64 OUT VREG_CPU_CSCOMP 402 CH 18 CSCOMP PWM2 28 VREG_CPU_PWM2 OUT 45
PWM1 29 VREG_CPU_PWM1 OUT 45
64 OUT VREG_CPU_CSSUM 17 CSSUM 21 1
C VREG_CPU_CSREF 16
OD1_N*
ODN_N* 20
VREG_CPU_OD1_N
DB7C1
VREG_CPU_DRV_EN OUT 45 C
64 OUT CSREF
VREG_CPU_FB 15 FB
ALERT* 2 VREG_CPU_ALERT_N 1
DB7P1
RTH1 FAULT* 3 VREG_CPU_FAULT_N 1
VREG_CPU_COMP 14 COMP DB7P2
R6C2
1 2 IMON 8 VREG_CPU_IMON
VREG_CPU_FBRTN 13 FBRTN
RT 10 VREG_CPU_RT
603 THRMSTR 12
VREG_CPU_TRDET TRDET
VREG_CPU_CSCOMP_R
TEMP SENSOR GND 7

RCS2 VREG_CPU_IREF 9 IREF 1 R7C5
R7B1 R7C1 GND_SLUG 41 909 KOHM
1 2 1 2 VREG_CPU_ILIMITFS 19 ILIMITFS 1%
35.7 KOHM 1% 6.81 KOHM 1% 2 CH
402 CH 1 CCS2 1 CCS1 402 CH 402
RPH2 RPH1 C7C1 C7C3 X817912-001
R7B3 2 2 R7B4 RCS1 3300 PF 3300 PF NEED TO SET DURING VALIDATION
27.4 KOHM 27.4 KOHM 10% 10%
2 R7B2 50 V 50 V
1% 1% 52.3 KOHM 2 X7R 2 X7R 2 R7C6 ROSC = 909K
CH 1 1 CH 1% 402 402 121 KOHM FOSC = 250KHZ
402 402 1%
1 CH
402 1 CH
402 PARTS ARE TRIMMED AT FACTORY SUCH THAT VBOOT=1.05V
B B
I2C ADDRESS
1100 000 R/W HEX
WRITE 1100 000 0 0XC0 1 R7C8
READ 1100 000 1 0XC1 1 5.76 KOHM
V_CPUCORE C7C7
0.1 UF 1%
10% 2 CH
6.3 V 402
2 X5R
PLACE SHORT NEXT TO 402
OUTPUT OF DUAL INDUCTOR
ST6C1 VREG_CPU_FBRTN
1 2 NOTE: VALID UP TO 58A
C7P1 1
SHORT 2 1 C7C6
1000 PF
VENABLE 10%
1000 PF 10% 50 V
50 V 2 X7R
CB X7R 402
ST6D1 VREG_V_CPUCORE_S R7C14 C7C2 402
1 2 1 2 1 2 VREG_CPU_FB
0 OHM % 470 PF 5% CFB

SHORT 805 EMPTY 50 V 1
C7C4
1 X7R 10 PF
DB7C5 402 5%
50 V
1 RB RA 2 NPO
DB7C6 CA 402
R7P1 C7C5 R7P2
1 2 1 2 VREG_CPU_COMP_R 1 2
1.1 KOHM 1% 18.2 KOHM1% ST6D2
PLACE SHORT NEXT TO 402 CH 1500 PF 10% 402 CH 1 2
POINT OF LOAD 50 V
X7R
A 402 SHORT A
PLACE SHORT NEXT TO
POINT OF LOAD
R7C2 R7C3
1 2 VREG_CPU_TRDET_R 1 2
43.2 KOHM1% 10 KOHM 5%
402 CH 1 402 CH
C7B7
470 PF
5%
50 V
2 X7R
402

[PAGE_TITLE=VREGS, CPU CONTROLLER] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREG, CPU OUTPUT PHASE 1 & 2
V_VREG_CPU
D 43 IN D
D6B1
R6N1 1N4148 C6N1
1 2 VREG_CPU2_VCC 1 3 VREG_CPU_BST2 1 2 2
1
2.2 OHM 1% D Q6B2 C7B5 1
CH SOT23 0.01 UF 10% 4.7 UF C7N1
805 50 V 10% 4.7 UF
1 DIO EMPTY 16 V 10%
C6B4 805 7.5 MOHM 2 16 V
1 UF DPAK_G1D2S3 X5R 2
10% R6N2 C6N2 1 1206 EMPTY
1206 V_CPUCORE
16 V 1 2 VREG_CPU_BST2_R
G S NOM.VOLTAGE: 0.9-1.2V
2 X5R 2.2 OHM 1%
FET
603 0.1 UF 10% 3
U6B1 IC 805 CH 25 V
X7R
MOS DRIVER 603
4 VCC BST 1
44 IN VREG_CPU_PWM2 2 IN DRVH 8 VREG_CPU_DRVH2 VREG_CPU_PHASE2 OUT 44
44 IN VREG_CPU_DRV_EN 3 OD_N* SW 7
1 R6C1
6 PGND DRVL 5 1 OHM
1%
2 2 2 CH
X850497-001 805
D Q6C2 D Q6C1 V_CPUCORE
VREG_CPU_SW2_R
C X819087-001 X819087-001
VREG_CPU_DRVL2 1
DPAK_G1D2S3
1
DPAK_G1D2S3 L6C1 SM EMPTY
1
C
G S G S DUAL INDUCTOR DB7C4
FET FET
3 3
1 L1 L4 4
1
C7C8
2200 PF 3 L3 L2 2
10%
50 V
2 X7R
805
X820048-001
420NH
DCR +/-8%
V_CPUCORE
L6C2 IND
DUAL INDUCTOR
B 2 L2 L3 3
B
4 L4 L1 1
X850592-001
420NH
40 A
D5B1 0.66
1N4148 +/-4%
R5N7 C5N5
1 2 VREG_CPU1_VCC 1 3 VREG_CPU_BST1 1 2 NOTE: THRUHOLE PART IS 2%
2 1
2.2 OHM 1% 1 C6N3 IMPROVEMENT ON DCR
CH SOT23 0.01 UF 10% D Q6B1 C6B2 4.7 UF
805 1 50 V 4.7 UF 10%
C5B10 DIO EMPTY 10% 16 V
1 UF 805 7.5 MOHM 16 V 2 EMPTY
10% R5N8 C5N6 2 X5R 1206
16 V 1 2 VREG_CPU_BST1_R DPAK_G1D2S3 1206
2 1
X5R 2.2 OHM 1% S
603 0.1 UF 10% G FET
805 CH 25 V 3
U5B5 IC X7R
MOS DRIVER 603
4 VCC BST 1
44 IN VREG_CPU_PWM1 2 IN DRVH 8 VREG_CPU_DRVH1 VREG_CPU_PHASE1 OUT 44
3 OD_N* SW 7
1 R5C1
6 PGND DRVL 5 1 OHM
1%
2 2 2 CH
X850497-001 805
D Q5C3 D Q5C1
VREG_CPU_SW1_R
A X819087-001 X819087-001 A
DPAK_G1D2S3 DPAK_G1D2S3
VREG_CPU_DRVL1 1 1
G S FET G S FET
3 3
1
C5C1
2200 PF
10%
50 V
2 X7R
805

[PAGE_TITLE=VREGS, CPU OUTPUT PHASE 1,2] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V5P0 DUAL
D D
V_5P0STBY
V_5P0STBY V_12P0
2 1 C2B2
C1N4 220 UF
1 R1N2 1 R1N1 0.22 UF 20%
10 KOHM 10 KOHM 10% 10 V
6.3 V
5% 5% 1 X5R 2 ELEC
RDL
2 CH 2 CH 402 U1B1 IC
C 402 402
SI4501DY V_5P0DUAL C
R1N3 3 S2
2 1 VREG_V5P0_SEL_PGATE 4 G2
10 KOHM 1% VREG_V5P0_SEL_NGATE
402 CH D<3> 5 V_5P0DUAL
VREG_V5P0_SEL_C D<2> 8 NOM.VOLTAGE: 5.00V
2 1
Q1N1 C1N3 C1B12 D<1> 7
0.22 UF 22 UF D<0> 6 1
10% 20% V_5P0 FTP FT2N3
6.3 V 10 V 2
R1P1 1 EMPTY 2 EMPTY G1
25 IN VREG_V5P0_SEL 1 2 VREG_V5P0_SEL_B1 VREG_V5P0_SEL_B2 402 1206 1 S1 1
FTP FT1N9
4.75 KOHM1%
1 402 CH
FT2R1 FTP XSTR X801132-002
2 R1P2
4.75 KOHM
1%
1 CH
402
B VREG_5P0_SEL
VREG_5P0_SEL NGATE/PGATE V_5P0DUAL B
HIGH LOW V_5P0STBY
LOW HIGH V_5P0
A A

[PAGE_TITLE=VREGS, V5P0 DUAL] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V5P0
V_12P0
4.2
L2B1
V_VREG_V3P3_V5P0 26 31 48
OUT
D 450 NH IND D
9 A TH
VREG_V3P3_V5P0_VCCO 48
OUT
C2E8 1
330 UF 1 1
20% 2 R1T4 1 R2T3 C2F3 C2F10
16 V 10 OHM 10 KOHM 4.7 UF 4.7 UF
POLY 1% 5% 10% 10%
TH 2 U1E1 1 OF 2 IC 16 V 16 V
CIV1
1 CH 2 CH 2 X5R 2 EMPTY
805 ADP1877 402 1206 1206
3 VIN PGOOD1 27 VREG_V5P0_PWRGD 25
5
OUT
VREG_V3P3_V5P0_VDL VDL
4 VCCO RR1
R2E6
1 1 1 29 1 2 ST2G2
C2E2 C1E1 C1E2 1 R1T2 RAMP1 VREG_V5P0_RAMP
1 2 VREG_V5P0_ISENSE_P
OUT 56
1 UF 1 UF 1 UF 0 OHM 820 KOHM 5%
10% 10% 10% 5% 402 CH
16 V 16 V 16 V SHORT
2 X5R 2 X5R 2 X5R 2 CH 2
603 603 603 402 D Q2F1
7.5 MOHM ST2G3

DPAK_G1D2S3 1 2 VREG_V5P0_ISENSE_N 56
2 23 1 OUT
VREG_V3P3_V5P0_SYNC SYNC DH1 VREG_V5P0_DH
C 1 R1E12
G S
3
FET SHORT
C
0 OHM
5%
2 EMPTY
V_5P0
402 VOLTAGE: 5.09V
C2F1 V_5P0
BST1 25 VREG_V5P0_BST 2 1
R2E7
1 1 2 32 0.1 UF 10% 3.75 1
FT2R2 FTP
VREG_V5P0_TRK TRK1 25 V ST2U1 DB2G2
0 OHM 5% X7R 1 2 VREG_V5P0_SW_S L2F1 R2G1
1 603 1 2 VREG_V5P0_RSENSE 1
402 CH C2E7 2 1 FTP FT2V2
0.22 UF SHORT
10% 1.6 UH IND 10 MOHM 1%
6.3 V SW1 24 VREG_V5P0_SW 10 A TH 2512 CH 1 1 1 1 1 1 R2G2 1 C2G5
2 EMPTY C2G3 C2V1 C2G2 C2V4 C2G1 150 OHM 820 UF
402 10 UF 10 UF 10 UF 10 UF 10 UF 5% 20%
R2E3 20% 20% 20% 20% 20% 6.3 V
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 2 CH
25 IN VREG_V5P0_EN 2 1 VREG_V5P0_EN_R 1 EN1 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 1206 2 POLY
TH
422 KOHM 1% RLIM1 805 805 805 805 805
402 CH 2 R2F1 1
1 R2E2 C2E6 ILIM1 26 VREG_V5P0_ILIM 1 2 2 DB2G4
10 KOHM 0.01 UF D Q2F2
5% 10% 3.48 K 1%
16 V 402 CH
2 CH 1 X7R
B 402 402 7.5 MOHM
DPAK_G1D2S3 B
DL1 21 VREG_V5P0_DL 1
G S FET
RGCS1 3
2 R1F3 ST2G1
22.1 KOHM 1 2
RFREQ 1%
R1E17 1 CH SHORT
2 1 VREG_V3P3_V5P0_FREQ 7 FREQ 402
97.6 KOHM 1%
402 CH
VENABLE
ST2U2 1 R2F7
PGND1 22 VREG_V5P0_PGND 1 2 0 OHM
%
SHORT 2 EMPTY
805
VREG_V5P0_FB 56
OUT
RF11
1 R2E4
VREG_V5P0_COMP 30 COMP1 7.5 KOHM
1%
1 CC11 2 EMPTY
C2E3 402
3300 PF COMP2 BW=
10% FB1 31 VREG_V5P0_FB_MID 56
50 V COMP1 BW= OUT
2 X7R
1 CC12 402
C2E4 RF12
330 PF 1 R2T4
A
VREG_V5P0_COMP_C
5%
A 2
50 V
NPO VREG_V5P0_SS 28 SS1
1 KOHM
1%
402 2 EMPTY
1 CSS1 402
C2E5 6
0.047 UF AGND
RC1 10% 33 GNDSLUG
1 R2E5 10 V
2 X7R
11 KOHM 402
1%
2 CH
X817911-002 LCC32
402

DRAWING
[PAGE_TITLE=VREGS, V5P0] Thu Feb 17 10:12:30 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V3P3
47 V_VREG_V3P3_V5P0
IN
D 47 IN VREG_V3P3_V5P0_VCCO D
R1E14
1
10 KOHM
5%
U1E1 2 OF 2 IC CH
2
402
ADP1877
PGOOD2 14 VREG_V3P3_PWRGD 25
OUT
R1E22
RAMP2 12 VREG_V3P3_RAMP 1 2
422 KOHM 1%
402 CH
ST1F1
1 2 VREG_V3P3_ISENSE_P 56
OUT
SHORT
DH2 18 VREG_V3P3_DH
1
R1E15 C1U1
2 1 9 4.7 UF ST1F3
VREG_V3P3_TRK TRK2 10% 1 2 VREG_V3P3_ISENSE_N
OUT 56
0 OHM 5% 16 V
C 402 CH U1F1
7 AMP
FET
2 X5R
1206 SHORT C
1 4
V_3P3
FT3R4 FTP C1F1 ST1E1
GATE0
DRN0 5 V_3P3 VOLTAGE: 3.3V
BST2 16 VREG_V3P3_BST 2 1 1 2 3 SRC0 DRN0 6
VREG_V3P3_EN 8 0.02
25 IN EN2 1
0.1 UF 10% SHORT L1F1 FTP FT2U1
25 V R1F9
X7R 2 GATE1 DRN1 7 VREG_V3P3_SW_S 1 2 VREG_V3P3_RSENSE 1 2 1
603 DB2G1
DRN1 8 30 MOHM
1 R1E16 1 SRC1 2.3 UH IND
10 KOHM 6 A SM 2512 CH 1 1 1 1
17 1% C1F9 C1F6 C1G2 C1F3
5% SW2 VREG_V3P3_SW 4.7 UF 4.7 UF 4.7 UF 4.7 UF
2 CH X807111-001 SO-8 10% 10% 10% 10%
402 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603
1
DB2F1
R1F1
15 1 2 VENABLE
ILIM2 VREG_V3P3_ILIM
4.53 KOHM 1% R2F9 ST1F2

402 CH 1 2 1 2
0 OHM %
R1F2 805 EMPTY SHORT
DL2 20 VREG_V3P3_DL 2 1
B 22.1 KOHM
402
1%
CH B
VREG_V3P3_FB 56
OUT
ST1U1
PGND2 19 VREG_V3P3_PGND 1 2
SHORT
1 R1E20
4.53 KOHM
1%
VREG_V3P3_COMP 11 COMP2 2 EMPTY
402
1
C1E3
3300 PF
10% FB2 10 VREG_V3P3_FB_MID 56
1 50 V OUT
C1E4 2 X7R
120 PF 402
5% 1 R1E19
50 V 1 KOHM
2 NPO 1%
VREG_V3P3_COMP_C
402 VREG_V3P3_SS 13 SS2

2 EMPTY
402
A 1
A
C1E5
0.047 UF
10%
10 V
2 X7R
402 X817911-002 LCC32
1 R1E21
7.87 KOHM
1%
2 CH
402

DRAWING
[PAGE_TITLE=VREGS, V3P3] Thu Feb 17 10:12:31 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_12P0
4.2
VREGS, VEDRAM
L7B1
V_VREG_VMEM_VEDRAM OUT 50
450 NH IND
TH
9 A
D 1 1 C7B8
VREG_VMEM_VEDRAM_VCCO OUT 50 D
C3F8 470 UF
330 UF 20%
20% 16 V 1 1
16 V R3G16 2 C3F1 C3F7
POLY 2 2 POLY
TH 2 R3G2 10 KOHM 4.7 UF 4.7 UF
TH 10 OHM 5% 10% 10% CIV1
1% CH 16 V 16 V
1 CH U3G1 1 OF 2 IC 402 1 2 X5R 2 EMPTY
805 1206 1206
ADP1877
3 VIN PGOOD1 27 VREG_VEDRAM_PWRGD OUT 25
VREG_VMEM_VEDRAM_VDL 5 VDL
4 VCCO RR1
R3F10
RAMP1 29 VREG_VEDRAM_RAMP 1 2 ST4F2
1 1 1
C3G1 C3G3 C3V1 680 KOHM 5% 1 2 VREG_VEDRAM_ISENSE_P OUT 55
1 UF 1 UF 1 UF 402 CH
10% 10% 10%
16 V 16 V 16 V 2 R3F12 1 R3F14 2 SHORT
2 X5R 2 X5R 2 X5R 0 OHM 0 OHM
603 603 603 5% 5% D Q3F1 ST4F4
1 2 VREG_VEDRAM_ISENSE_N OUT 55
1 CH 2 CH
402 402 7.5 MOHM
DPAK_G1D2S3 SHORT
VREG_VMEM_VEDRAM_SYNC 2 SYNC DH1 23 VREG_VEDRAM_DH 1
SYNC HIGH=FORCED PWM MODE G S V_CPUEDRAM
C FET
SYNC LOW =PULSE SKIP MODE
1 R3F13
3
V_CPUEDRAM C
0 OHM 3.4 VOLTAGE: 1.075V 1
5% L4F1 FTP FT4T2
R4F1
2 EMPTY 1 2 VREG_VEDRAM_RSENSE 2 1 1
402 DB4E3
C3F5 1.7 UH IND 10 MOHM 1%
BST1 25 VREG_VEDRAM_BST 2 1 2512 CH C4E3 C4E6 C4F7
ST3F1 13.8 A TH 820 UF 820 UF 820 UF
0.1 UF 10% 1 2 VREG_VEDRAM_SW_S 20% 20% 20%
VREG_VEDRAM_TRK 32 TRK1 25 V 2.5 V 2.5 V 2.5 V
X7R POLY POLY EMPTY
603 SHORT RDL RDL RDL
1 SW1 24 VREG_VEDRAM_SW
FT2T9 FTP
25 IN VREG_VEDRAM_EN 1 EN1
1 R3F15 RLIM1 1 1 1 1
10 KOHM R3F7 C5T52 C5E11 C4T7 C5E10
5% ILIM1 26 VREG_VEDRAM_ILIM 1 2 2 4.7 UF 4.7 UF 4.7 UF 4.7 UF
10% 10% 10% 10%
2 CH 3.32 KOHM 1% D Q4F1 16 V 16 V 16 V 16 V
402 402 CH 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
1206 1206 1206 1206
7.5 MOHM
B 21 1
DPAK_G1D2S3 B
DL1 VREG_VEDRAM_DL
G S FET
RGCS1 3
ST5E1
2 R3V1 2 1
22.1 KOHM
RFREQ 1% 1 DB4E4 SHORT
R3G4 1 CH 1 R3F11
VENABLE
2 1 VREG_VEDRAM_FREQ 7 FREQ 402 0 OHM 1 DB4E5
97.6 KOHM 1% %
402 CH ST4U1 2 EMPTY
PGND1 22 VREG_VEDRAM_PGND 2 1 805
VREG_VEDRAM_FB OUT 55
SHORT
RF11
1 R3F8
7.87 KOHM
1%
2 EMPTY
402
VREG_VEDRAM_COMP 30 COMP1
1 CC11
C3F2
4700 PF
10% FB1 31 VREG_VEDRAM_FB_MID OUT 55
50 V
1 CC12 2 X7R
C3F3 402
62 PF
VREG_VEDRAM_COMP_C
5% RF12
A 2
50 V
NPO
402
VREG_VEDRAM_SS 28 SS1
1 R3F9
10 KOHM
A
1%
2 EMPTY
1 CSS1 6 402
C3F4 AGND
0.047 UF 33 GNDSLUG
RC1 10%
1 R3F6 10 V
43.2 KOHM 2 X7R
1% 402 X817911-002 LCC32
2 CH
RC1=120K 402

[PAGE_TITLE=[VREGS, VEDRAM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VMEM
D V_VREG_VMEM_VEDRAM
D
49 IN
VREG_VMEM_VEDRAM_VCCO 1 CIV2 1
49 IN C7F3 C7U1
2 R3G15 4.7 UF 4.7 UF
10 KOHM 10% 10%
5% 16 V 16 V
2 X5R 2 EMPTY
U3G1 2 OF 2 IC 1 CH 1206 1206
402
ADP1877
PGOOD2 14 VREG_VMEM_PWRGD 25
OUT
RR2
R3G13 ST7F2
RAMP2 12 VREG_VMEM_RAMP 1 2 1 2 VREG_VMEM_ISENSE_P OUT 55
680 KOHM 5%
402 CH SHORT
2 ST7F3
D Q7G1 1 2 VREG_VMEM_ISENSE_N OUT 55
SHORT
7.5 MOHM
DPAK_G1D2S3
V_MEM
18 VREG_VMEM_DH 1 VOLTAGE: 1.8V
DH2
C 2
R3G5
1 VREG_VMEM_TRK 9
G S
3
FET
1 C
TRK2 DB7F1
0 OHM 5% 1
V_MEM
402 CH FTP FT7U1
3.4
L7F1 R7F1
1 2 1
FT2T1 FTP C3G9 ST6V2 VREG_VMEM_RSENSE 1 2
BST2 16 VREG_VMEM_BST 2 1 2 1 VREG_VMEM_SW_S
IND 1.7 UH 10 MOHM 1%
25 IN VREG_VMEM_EN 8 EN2 TH 13.8 A 2512 CH C7F2 1 C7F1
0.1 UF 10% SHORT 820 UF
25 V 4.7 UF
1 R3G14 X7R 20% 10%
10 KOHM 603 2.5 V 6.3 V
5% POLY 2 EMPTY
RDL 603 1
2 CH 17 VREG_VMEM_SW DB7F2
402 SW2
V_MEM
RLIM2
R3G10
ILIM2 15 VREG_VMEM_ILIM 1 2 2 1 C7R1
330 UF
3.32 KOHM 1% D Q7G2 20%
402 CH 2.5 V
2 EMPTY
B 7.5 MOHM
DPAK_G1D2S3
SM
B
DL2 20 VREG_VMEM_DL 1
G S FET
3 V_MEM
1 R4G3
RGCS2 22.1 KOHM
1% 1 C4U4
330 UF
2 CH ST7F1 20%
402 2 1 2.5 V
ST6V1 1 R3G17 2 EMPTY
SM
VENABLE
PGND2 19 VREG_VMEM_PGND 2 1 0 OHM SHORT
%
SHORT 2 EMPTY
805
VREG_VMEM_FB OUT 55
RF21
1 R3G11
VREG_VMEM_COMP 11 COMP2 20 KOHM
1%
1 CC21 2 EMPTY
C3G6 402
4700 PF
10% FB2 10 VREG_VMEM_FB_MID OUT 55
50 V
2 X7R
402 RF22
1 CC22
VREG_VMEM_COMP_C
C3G7 1 R3G12
A 62 PF
5% VREG_VMEM_SS
13
10 KOHM
1% A
50 V SS2
2 NPO 2 EMPTY
402 402
1 CSS1
RC2 C3G8
1 R3V4 0.047 UF
43.2 KOHM 10%
1% 10 V
2 X7R
2 CH 402 X817911-002 LCC32
402

[PAGE_TITLE=[VREGS, VMEM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VCS
D D
V_12P0 V_5P0
ST5C1
4.2 1 2 VREG_VCS_ISENSE_P OUT 57
L4B1
V_VREG_VCS SHORT
450 NH IND 1 C5B21
9 A TH 1 1
C4N9 C4N7 C4B11 C4B12 C5N11 C4N10 C5N10 820 UF C5B20 C5B19
1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 20% 4.7 UF 4.7 UF
10% 10% 20% 20% 20% 20% 20% 6.3 V 10% 10% ST5C3
16 V 16 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R 1
C4B4
1
C4B14 X5R X5R X5R X5R X5R 2 EMPTY
TH 2 X5R 2 X5R 1 2 VREG_VCS_ISENSE_N OUT 57
603 603 4.7 UF 47 UF 805 805 805 805 805 603 603
10% 20% SHORT
6.3 V 6.3 V
C 2 X5R
603
2 X5R
1206 C
V_CPUCORE V_CPUVCS
U4B3 IC VOLTAGE: 1.25 - 1.3V
ir3638 2
4 VCC D Q5B1 V_CPUVCS
1 R4C13
1 KOHM 10 VC
5% 1 VREG_VCS_NC 14 NC 7.5 MOHM
DB4P8 DB4P6 DB4N2
1 2 EMPTY 1 1 VREG_VCS_OCP 3 NC0 R4B4 DPAK_G1D2S3
TP TP DB4C1 1
402 1 VREG_VCS_NC1 5 NC1 HDRV 9 VREG_VCS_HDRV 1 2 VREG_VCS_HDRV_R 1
DB4P7 G S FTP FT5R17
R4C14 1 VREG_VCS_NC2 11 NC2 LDRV 6 2.2 OHM 1% FET
CPU_SRVID VREG_VCS_VP DB4B1
2 1 2 2 VP 805 CH 3
IN L5C1 R5C2
0 OHM 5% 1 R4C11 1 VREG_VCS_VOUT_L 1 2 VREG_VCS_VOUT 1 2 1
402 CH 1 MOHM C4C5 DB5C1
5% 0.1 UF 1.7 UH IND 10 MOHM 1%
10% 13.8 A TH 2512 CH 1 C5C2
2 CH 6.3 V 2 1 1
402 2 X5R 3.4 C5R65 C5C6 820 UF
402 D Q5C2 4.7 UF 4.7 UF 20%
10% 10% 2.5 V
6.3 V 6.3 V
7.5 MOHM 2 X5R 2 X5R 2 POLY
RDL
DB4N3 1 13 603 603
VREG_VCS_SS_SD_N SS R4N15 DPAK_G1D2S3
TP VREG_VCS_LDRV 1 2 VREG_VCS_LDRV_R 1
2 G S
C4B7 2.2 OHM 1% FET
B 0.1 UF
10% 805 CH 3
B
6.3 V
1 X5R
402 PGND 8
VREG_VCS_COMP 12 7
COMP GND
1 R4B11
27.4 KOHM 1 FB
1% VENABLE
2 CH X811812-001
402 SSOP R4B17 R5B13 ST5D1
1 2 1 2 2 1
2
C4B6
VREG_VCS_COMP_R
11 KOHM 1% 0 OHM %
22 PF 402 EMPTY 805 EMPTY 1 DB5B3SHORT
5%
50 V 1
1 NPO DB5B2
402
R4B19 1
27.4 KOHM VREG_VCS_FB 57
1 1% OUT
C4B5 EMPTY 2
4700 PF 402
10%
50 V
2 X7R
603 VREG_VCS_FB_MID OUT 57
A A
GAIN=0.4 WITH R4B17 = 11K, R4B19 = 27.4K
OUTPUT = CPU_SRVID(1+GAIN)

[PAGE_TITLE=VREGS, VCS] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, 1P2+1P8+GPUPCIE+CPUPLL+EFUSE
V_3P3
D ST4B1
D
1 2 V1P2_ISENSE_P 60
V_GPUPCIE
1 R4B5 1 R4B13 1 R3B5 1 R4B12
OUT NOM.VOLTAGE: 1.5V
4.99 OHM 4.99 OHM 4.99 OHM 4.99 OHM SHORT
1% 1% 1% 1% ST4B2
2 CH 2 CH 2 CH 2 CH 1 2 V1P2_ISENSE_N 60
TARGET FOR VEJLE=1.5V
1206 1206 1206 1206
OUT V_3P3 V_GPUPCIE
SHORT
U4E2 IC
V_1P2 NCP1117 R4E11
V_1P2 3 IN OUT 2 V_VREG_GPUPCIE 1 2 1
FTP FT5T1
NOM.VOLTAGE: 1.204V 0 OHM %
C4B3 U3B1 IC 1 ADJUST/GND OUT/TAB 4 805 CH
MAX RECOMMENDED CURRENT: 1A 1
10 UF1 LD39100 R4B14 1 R3T5 DB4E1
20% C4E11 1 R4E8 1 R4E7
1 3 PG VOUT 4 V_VREG_1P2 1 2 1 1 UF X800501-001 1 KOHM 1 OHM 0 OHM 5%
6.3 V DB3N1 VREG_1P2_PWRGD FTP FT3P3
X5R 2 100 MOHM 1% 10% SOT223 1% 1% 402 CH
805 V_VREG_1P2_IN 6 5 805 CH 16 V 1 2 VREG_GPUPCIE_FB
VIN ADJ 1 2 X5R 1.5V 2 EMPTY 2 CH OUT 58
1 1 1 603 402 402
V_VREG_1P2_ADJUST
C3B7 DB2E1
1 2 C4B15 0.1 UF C3B8
V_3P3 EN GND 4.7 UF 10% 10 UF
MPAD 7 10% 25 V 20% VREG_PCIEX_ADJUST
6.3 V 2 X7R 6.3 V
2 X5R 603 2 X5R R4E10
1 R3B4 X854861-001 DFN6 603 805 1
C4E13
1 2 VREG_GPUPCIE_FB_MID IN 58
10 KOHM 0.1 UF 0 OHM 5%
C 1% 10%
6.3 V
402 CH
C
VREG_PCIEX_R
2 EMPTY 2 EMPTY
402 VREG_1P2_EN 1 R4B9 R4N17 402
25 IN 1 22.1 KOHM
FTP FT3P9 1% 0 OHM 5%
402 CH
C3B2 1 2 EMPTY 1 2 VREG_1P2_FB
402 OUT 60
1 R3B3
4.7 UF 10 KOHM
20% 1%
4 V 1 R4E9 1
EMPTY 2 2 CH R4B8 C4E12
402 402 1 2 VREG_1P2_FB_MID 60 191 OHM
IN 1% 4.7 UF
0 OHM 5% 10%
402 CH 2 CH 6.3 V
1 R4B7 402 2 X5R
44.2 KOHM 603
1%
2 EMPTY
402
NOTE: BOTTOM ADJUST RESISTOR
LEFT IN TO REDUCE EFFECT OF ADJUST
V_1P8 PIN CURRENT WHEN USED WITH 1K DIGIPOT
NOM.VOLTAGE: 1.83V
V_1P8 1
DB3E1
B NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES
B
R4E12
1 2 1
FTP FT3R8
0 OHM %
V_3P3 805 CH V_CPUPLL
U4E1 IC V_CPUPLL
NCP1117 R4E4
NOM.VOLTAGE: 1.83V
3 IN OUT 2 V_VREG_1P8PLL 1 2 1
FTP FT4T3
0 OHM %
1 ADJUST/GND 805 CH 1 V_5P0
DB4E2
1 R4E6 1 R4E5
1 1 KOHM 1 OHM
C4E10
1 UF X854304-001 1% 1%
10% R3F4
DPAK 2 EMPTY 2 CH 1 2 VREG_CPUPLL_1P8_FB
16 V OUT 58
2 X5R 1.8V 402 402
0 OHM 5% 2 V_EFUSE
603
402 CH C4P4
1 UF
NOM.VOLTAGE: 1.5V
10% V_EFUSE
VREG_CPUPLL_ADJUST 16 V
R4U4 1 X5R
1 2 VREG_CPUPLL_1P8_FB_MID 603 U4P2 IC
1 IN 58
C4F8 0 OHM 5%
0.1 UF 402 CH LD39015 R4P10
VREG_CPUPLL_R
10% 1 VIN VOUT 5 VREG_EFUSE_VOUT 1 2 1

6.3 V FTP FT4P9
2 EMPTY 0 OHM %
402 2 IN VREG_EFUSE_EN 3 ENABLE GND 2 805 CH 1
DB4C2
NC 4 C4P7 C4P6
1 1 UF 0.1 UF
DB4P1
10% 10%
16 V 6.3 V
VREG_EFUSE_EN HIGH 2 R4P9 X819038-001 1.5V X5R X5R
A IS 1.8V (V_MEM) 10 KOHM
5%
603 402 A
1 R4F2 1 1 CH
453 OHM C4E9 402
1% 4.7 UF
10%
2 CH 6.3 V
402 2 X5R
603
NOTE: BOTTOM ADJUST RESISTOR

LEFT IN TO REDUCE EFFECT OF ADJUST
PIN CURRENT WHEN USED WITH 1K DIGIPOT
DRAWING
[PAGE_TITLE=VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE] Thu Feb 17 10:12:32 2011 CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS,STANDBY SWITCHERS
D 2
ST5B2
1 V1P2STBY_ISENSE_P
OUT 59
D
SHORT
ST5B1
2 1 V1P2STBY_ISENSE_N 59
OUT
SHORT
V_1P2STBY
NOM.VOLTAGE: 1.2V
MAX RECOMMENDED CURRENT: 300MA
V_5P0STBY 1
V_1P2STBY
FT5M3 FTP
0.08 U5A2 IC
L5B1 L5B2 1 DB5B1
TPS62220 1 R5B7 2
1 2 V_VREG_STBY_VIN 1 IN SW 5 VREG_1P2STBY_SW 1 2 V_1P2STBY_R 1
DB3C2
2.2 UH IND 10 UH IND 100 MOHM 1%
1600 MA 1210 1 1 1
V_3P3STBY FB 4 900 MA SM 805 CH
C5M9 C5A4 C5A5
10 UF 10 UF 10 UF 1 R5A7 3 EN GND 2 R5B5 1 1 1
20% 20% 20% 10 KOHM C5B2 C5B7 C5B3
6.3 V 6.3 V 6.3 V VREG_1P2STBY_FB_CHIP 1 2 10 UF 4.7 UF 0.1 UF
1 R5A4 1%
C 2 X5R
805
2 X5R
805
2 X5R
805 10 KOHM
1% 2 CH X855078-001SOT23-5 42.2 KOHM
402
1%
CH
20%
6.3 V
10%
6.3 V
10%
25 V C
402 2 X5R 2 EMPTY 2 X7R
2 EMPTY 805 603 603
402 C5B1
1 1 2
VREG_1P2STBY_EN 1 R5A15 C5A9 1
30.1 KOHM 100 PF DB5N1
1% 5% 75 PF 5%
50 V 50 V VENABLE
2 CH 2 EMPTY NPO
1 402 402 402
C5M8 R5B4 ST3C6
10 UF 1 2 2 1
20%
6.3 V 0 OHM 5%
2 X5R 402 EMPTY SHORT
805
1
DB5M2 1 R5B2 2
VREG_1P2STBY_FB_R VREG_1P2STBY_FB 59
OUT
0 OHM 5%
1 R5A13 2 402 CH VREG_1P2STBY_FB_MID
IN 59
0 OHM 5%
402 CH
B 1
ST5A2
2 V3P3STBY_ISENSE_P B
OUT 59
SHORT
ST5A1
1 2 V3P3STBY_ISENSE_N 59
OUT
SHORT V_3P3STBY
DB5M1 1 V_3P3STBY
U5A1 IC 0.08 NOM.VOLTAGE: 3.315V
L5A1 MAX RECOMMENDED CURRENT: 1A
TPS62590 R5A11
5 IN SW 1 VREG_3P3STBY_SW 1 2V_3P3STBY_R 1 2 1
DB5A2
2.2 UH IND 100 MOHM 1%
V_1P2STBY 4 EN FB 3 1600 MA 1210 805 CH
1 R5M9
10 KOHM R5A6 1 1
2 MODE GND 6 C5A2 C5A3
1% VREG_3P3STBY_FB_CHIP 2 1 10 UF 0.1 UF
MPAD 7
1 R5M6 2 CH 100 KOHM 1% 20% 10%
10 KOHM 402 402 CH 6.3 V 25 V
1% 2 X5R 2 X7R
VREG_3P3STBY_EN X854683-001 DFN6 805 603
2 EMPTY 1
402 DB5A1
1 R5A5 C5A1
DB5M3 22.1 KOHM 1 2
TP 1%
1 1 2 CH 22 PF 5% VENABLE
C5M5 402 50 V
4.7 UF NPO
10%
A 2
6.3 V
X5R
402
1
R5A3
2 2
ST2D1
1 A
603 0 OHM 5%
402 EMPTY SHORT
1 R5A8 2 VREG_3P3STBY_FB
VREG_3P3STBY_FB_R 59
OUT
0 OHM 5%
1 R5A12 2 402 CH VREG_3P3STBY_FB_MID
IN 59
0 OHM 5%
402 CH
R5A5 SHOULD BE 182KOHM 0402, WAITING ON COMPONENT TB ADDED IN TC

[PAGE_TITLE=VREGS, STANDBY SWITCHERS] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOARD LEVEL DECOUPLING
D D
V_12P0 V_5P0
1 1 1 1 1 1 1 1
C3N40 C3M5 C7M1 C7B4 C1U3 C1P1 C1A10 C2A15
10% 10% 10% 10% 10% 10% 10% 10%
16 V 16 V 16 V 16 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X7R 2 X7R 2 X7R 2 X7R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402
V_5P0
V_5P0DUAL
C C
1 1 1 1 1 1
C4E4 C4N8 C5N3 C3T23 C2V2 C3U4 1 1
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF C2G4 C5G8
10% 10% 10% 10% 10% 10% 0.1 UF 0.1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 6.3 V 6.3 V
2 X5R 2 X5R
402 402
V_3P3
1 1 1 1 1 1 1 1 1 V_3P3STBY
C2U1 C3T6 C4M1 C3T21 C4B8 C3B1 C3E2 C3C7 C3N1
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402
1 1 1
C1T1 C4G1 C4N2
B 0.1 UF
10%
0.1 UF
10%
0.1 UF
10% B
6.3 V 6.3 V 6.3 V
V_1P2STBY 2 X5R 2 X5R 2 X5R
402 402 402
1 1 1 1
C4B10 C3B3 C3P3 C4B9
0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
V_5P0STBY
1
C3V3
0.1 UF
V_1P2 10%
6.3 V
2 X5R
402
1 1
C4C1 C4C7
0.1 UF 0.1 UF
A 10%
6.3 V
10%
6.3 V
A
2 X5R 2 X5R
402 402

[PAGE_TITLE=BOARD, DECOUPLE] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, VMEM + VEDRAM
V_5P0STBY
D R3B2
D
37 23 HDMI_DDC_CLK 1 2 PMBUS_CLK 44 55 56 57 58 59 60 64
IN OUT 2
0 OHM 5% C3G5
402 CH 2.2 UF
20% U3V1 IC
R3B1 6.3 V
HDMI_DDC_DATA 1 2 PMBUS_DATA 1 X5R
40 37 23 BI BI 44 55 56 57 58 59 60 64 402 1 9 PMBUS_CLK
VDD SCL IN 55
0 OHM 5% SDA 7 PMBUS_DATA 44 55 56 57 58 59 60
402 CH 3
BI 64
WP*
R3C2 VREG_VMEM_FB 6 12 VREG_VEDRAM_FB
SMB_CLK 1 2 50 IN A1 A3 IN 49
62 61 25 22 BI R3G8 R3F16
0 OHM 5% 50 VREG_VMEM_FB_MID 1 2 VREG_VMEM_FB_MID_R 4 W1 W3 14 VREG_VEDRAM_FB_MID_R 1 2 VREG_VEDRAM_FB_MID 49
402 EMPTY IN IN
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
R3C1
62 61 25 22 SMB_DATA 1 2
BI MARGIN_VMEM_VEDRAM_AD1 11 AD1 VSS 8
0 OHM 5% MARGIN_VMEM_VEDRAM_AD0 2 AD0 DGND 10
402 EMPTY
V_5P0STBY V_5P0STBY X819026-001 TSSOP
V_5P0STBY VALUE=10K
DEFAULT=127 (0X7F)
1 R3U3 1 R3G9 SETPOINT1=VMEM 81 (0X51)
C J5B1 1 KOHM
5%
1 KOHM
5%
SETPOINT2=VEDRAM 144 (0X90) C
2X2HDR 2 EMPTY 2 EMPTY AD5252 I2C ADDRESS
1 2 402 402 0101 1 AD1 AD0 R/W HEX
3 4 WRITE 0101 1 0 0 0 0X58
1 R3U1 1 R3G7 READ 0101 1 0 0 1 0X59
1 KOHM 1 KOHM
HDR 5% 5%
2 CH 2 CH
402 402
N: PMBUS HEADER CAN BE USED AS

A RELIABILITY INTERFACE HEADER.
V_5P0STBY
U3G3 IC
REF3333
1 IN OUT 2
1 1
C3G11 C3G10
B 2.2 UF
20%
GND 3 0.1 UF
10% B
6.3 V 6.3 V
2 X5R X820467-001 2 X5R
402 SC70 402
V_5P0 3.3V +/-0.15%
V_3P3_VREF_VMEM_VEDRAM
2 2
C3G2 C3V2
2.2 UF 2.2 UF
20% 20%
1
6.3 V U3V2 IC 1
6.3 V
X5R X5R
402 AD8213 402 U3G2 IC
8 VAA
AD7991
8 VDD
50 VREG_VMEM_ISENSE_P 2 IN2_P OUT2 4
IN VREG_VMEM_ISENSE_N 1 SCL 1 PMBUS_CLK
IN 55
50 IN IN2_N 6 2 PMBUS_DATA
5
VREG_VMEM_IOUT VIN3/VREF SDA BI 44 55 56 57 58 59 60 64
VREG_VMEM_CF2 CF2 5
VREG_VEDRAM_IOUT VIN2
4 VIN1
49 VREG_VEDRAM_ISENSE_P 9 IN1_P OUT1 7
IN VREG_VEDRAM_ISENSE_N 10 1 R3G6 1 R3G1
3 VIN0 GND 7
49 IN IN1_N
VREG_VEDRAM_CF1 6 CF1 24.3 KOHM 24.3 KOHM
GND 3 1% 1%
2 CH 2 CH X817914-001 SOT23
402 402
X817913-001 MSOP10
AD7991-0 I2C ADDRESS
2 2 0101 000 R/W HEX
C3G4 C3F6
A 0.22 UF
10%
0.22 UF
10%
WRITE 0101 000 0
READ 0101 000 1
0X50
0X51
A
6.3 V 6.3 V
X5R 1 1 X5R
402 402
PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8
50 VREG_VMEM_FB
IN
49 VREG_VEDRAM_FB
IN

[PAGE_TITLE=MARGIN, VMEM + VEDRAM] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, V3P3 + V5P0
VREG_V3P3_FB IN 48
V_5P0STBY
1
D 47 IN VREG_V5P0_FB
V_P Q1F1 1 R1U5
22.1 KOHM
D
NC3 X819034-001 1%
2.048V 0.1% 2 CH
2 V_N IC 402
1 R2U1
1
V_P Q2F3 C2F4
ADR5040A
2
35.7 KOHM ADR5043 2.2 UF U1U1 IC
1% 20%
NC3 X819033-001 6.3 V
2 CH 1 X5R 1 9 PMBUS_CLK
402 3.0V 0.1% 402 VDD SCL IN 55
V_N IC SDA 7 PMBUS_DATA 44 55 56 57 58 59 60 64
3
BI
2
WP*
VREG_V5P0_FB_A1 6 A1 A3 12 VREG_V3P3_FB_A3
R2T5 R1T19
47 IN VREG_V5P0_FB_MID 1 2 VREG_V5P0_FB_MID_R 4 W1 W3 14 VREG_V3P3_FB_MID_R 1 2 VREG_V3P3_FB_MID IN 48
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
MARGIN_V3P3_V5P0_AD1 11 AD1 VSS 8
MARGIN_V3P3_V5P0_AD0 2 AD0 DGND 10
X819026-001 TSSOP
V_5P0STBY V_5P0STBY VALUE=10K
DEFAULT=128 (0X7F)
C 1 R1U4 1 R2F3
SETPOINT1=V5P0 69 (0X45)
SETPOINT2=V3P3 123 (0X7B) C
1 KOHM 1 KOHM
5% 5%
2 EMPTY 2 CH AD5252 I2C ADDRESS
402 402 0101 1 AD1 AD0 R/W HEX
1 R1U3 WRITE 0101 1 0 1 0 0X5A
1 KOHM 1 R2F2 READ 0101 1 0 1 1 0X5B
5% 1 KOHM
5%
2 CH
402 2 EMPTY
402
V_5P0DUAL
U1F3 IC
REF3333
1 IN OUT 2
1 1
C1F10 3 C1F11
2.2 UF GND 0.1 UF
20% 10%
6.3 V 6.3 V
2 X5R X820467-001 2 X5R
402 SC70 402
3.3V +/-0.15%
V_5P0
B B
V_3P3_VREF_V5P0_V3P3
2
C1U2 2
2.2 UF C2F2
20% U2U1 IC 2.2 UF
6.3 V 20%
1 X5R 6.3 V
402 AD8213 1 X5R U1F2 IC
8 VAA 402
AD7991
8 VDD
47 IN VREG_V5P0_ISENSE_P 2 IN2_P OUT2 4
1 PMBUS_CLK
VREG_V5P0_ISENSE_N 1 SCL IN 55
47 IN IN2_N 6 2 PMBUS_DATA
5
VREG_V5P0_IOUT VIN3/VREF SDA BI 44 55 56 57 58 59 60 64
VREG_V5P0_CF2 CF2 5
VREG_V3P3_IOUT VIN2
4 VIN1
48 IN VREG_V3P3_ISENSE_P 9 IN1_P OUT1 7
3 7
VREG_V3P3_ISENSE_N 10 VIN0 GND
48 IN IN1_N
VREG_V3P3_CF1 6 CF1 1 R2F5 1 R2F8
GND 3 24.3 KOHM 24.3 KOHM
2 2 1% 1% X818998-001 SOT23
C2F6 C1F2
0.22 UF 0.22 UF 2 CH 2 CH
10% 10% X817913-001 MSOP10 402 402
6.3 V 6.3 V V_5P0
X5R 1 1 X5R AD7991-1 I2C ADDRESS
402 402 R2F4 0101 001 R/W HEX
1 2 VREG_V5P0_FB_R WRITE 0101 001 0 0X52
150 OHM 1% READ 0101 001 1 0X53
V_3P3 402 CH
R1F4 PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8

1 2
A 150 OHM 1%
VREG_V3P3_FB_R
A
402 CH
1 R1F6 1 R1F5
221 OHM 221 OHM
1% 1%
2 CH 2 CH
402 402

[PAGE_TITLE=MARGIN, V3P3 + VP50] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, VREFS + VCS 3
U4B2
VDD AD7992
IC
SCL 10 PMBUS_CLK 55
9 PMBUS_DATA IN
SDA BI 44 55 56 57 58 59
V_5P0STBY 2 60 64
C5N1
U5B6 IC 2.2 UF
20% 57 MEM_VREFS 4 VIN2/REFIN ALERT/BUSY 8
REF3333 6.3 V IN MARGIN_VIN1 5
D 1 IN OUT 2 V_3P3_VREF_VCS 1 X5R
402 1 R5B14
VIN1
D
1 1 1 KOHM
C5N8 C5N7 5% 6 AS
2.2 UF GND 3 0.1 UF
20% 10% 2 CH
6.3 V 6.3 V 402 AGND2 7
2 X5R X820467-001 2 X5R 1 R5B16 1 CONVST_N* AGND1 2
402 SC70 402 1 KOHM
3.3V +/-0.15% 5%
MARGIN_VREFS_CONVST
2 EMPTY X814249-001 MSOP10
402
MARGIN_VREFS_AS
AS=GND 0100011 R/W
VREG_VCS_FB WRITE 0100011 0 0X46
57 51 IN READ 0100011 1 0X47
1 R5B15 1 R4N10 AS=VDD 0100100 R/W HEX
V_5P0 1 KOHM 1 KOHM
5% 5%
2 CH 2 CH
402 402
2
2 C5N2
C5B15 U5B2 IC 2.2 UF
2.2 UF 20%
20% AD8213 1
6.3 V U5B1 IC
8 X5R
C 1
6.3 V
X5R
402
VAA 402 3 VDD AD7992 SCL 10 PMBUS_CLK IN 55 C
2 IN2_P OUT2 4 VREG_VCS_IOUT2 SDA 9 PMBUS_DATA BI 44 55 56 57 58 59 60 64
1 IN2_N
VREG_VCS_CF2 5 CF2
4 VIN2/REFIN ALERT/BUSY 8
51 IN VREG_VCS_ISENSE_P 9 IN1_P OUT1 7 VREG_VCS_IOUT 5 VIN1
51 IN VREG_VCS_ISENSE_N 10 IN1_N
VREG_VCS_CF1 6 CF1
GND 3 R5B12 1 1 R5N2
24.3 KOHM 24.3 KOHM 6 AS
VREG_VCS_IN
1% 1%
CH 7
X817913-001 MSOP10 402 2 2 CH AGND2
402 1 CONVST_N* AGND1 2
1 R5B6
2 2 1 KOHM
C5B4 C5B8
MARGIN_VCS_CONVST
0.22 UF 0.22 UF 1 R5B10 5% X814249-001 MSOP10
10% 10% 1 KOHM 2 CH
6.3 V 6.3 V 5% 402
X5R 1 1 X5R
402 402 2 CH
402 MARGIN_VCS_AS AD7992-1 I2C ADDRESS
AS=VDD 0100100 R/W HEX
WRITE 0100100 0 0X48
READ 0100100 1 0X49
1 R5B11 1 R5N1 AS=GND 0100011 R/W
B 1 KOHM
5%
1 KOHM
5% B
2 EMPTY 2 CH
402 402
V_5P0STBY V_MEM
2 U4B1
IC
C4N1
2.2 UF 1 VDD SCL 9 PMBUS_CLK 55
20%
7 PMBUS_DATA IN
6.3 V SDA BI 44 55 56 57 58 59 60 64
1 X5R 3
402 WP*
6 A1 A3 12 VREG_VCS_FB OUT 51 57
R4N5 R4B18
57 OUT MEM_VREFS 1 2 MEM_VREFS_R 4 W1 W3 14 VREG_VCS_FB_MID_R 1 2 VREG_VCS_FB_MID OUT 51
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
MARGIN_VREFS_AD1 11 AD1 VSS 8
MARGIN_VREFS_AD0 2 AD0 DGND 10
V_5P0STBY V_5P0STBY V_MEM X819026-001 TSSOP

VALUE=10K
DEFAULT=128 (0X7F)
A 1 R4N2
1 KOHM
1 R4N7
1 KOHM
2 R4N4
100 OHM
SETPOINT1=VREFS 63 (0X3F)
SETPOINT2=VCS 140 (0X8C)
A
5% 5% 5%
2 CH 2 CH 1 CH AD5252 I2C ADDRESS
402 402 402 0101 1 AD1 AD0 R/W
MARGIN_VMEM_VREFS_BOT WRITE 0101 1 1 1 0 0X5E
1 R4N3 1 R4N6 READ 0101 1 1 1 1 0X5F
1 KOHM 1 KOHM
5% 5%
1
2 EMPTY 2 EMPTY V_P Q4B1

402 402 ADR510
NC3 X821158-001
1.0V 0.35%
V_N IC PROJECT NAME PAGE FAB REV
MICROSOFT
2
[PAGE_TITLE=MARGIN, VREFS + VCS] DRAWING

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, VGPUPCIE,1P8, VCPUPLL, V12P0, TEMP
V_5P0STBY
V_5P0STBY
U6A1 IC
D INA219 D
4 VS 1
C3E4
1 2.2 UF U3E2
C6N5 20% IC
0.1 UF 6.3 V
10% 2 X5R 1 9 PMBUS_CLK
402 VDD SCL IN 55
6.3 V 7 PMBUS_DATA
2 X5R SDA BI 44 55 56 57 58 59 60
402 3 WP* 64
R6A10 52 IN VREG_GPUPCIE_FB 6 A1 A3 12 VREG_CPUPLL_1P8_FB IN 52

38 IN VREG_V12P0_ISENSE_P VREG_V12P0_ISENSE_P_R 1 VIN+
1 2
C6A6 52 OUT VREG_GPUPCIE_FB_MID 4 W1 W3 14 VREG_CPUPLL_1P8_FB_MID OUT 52
10 OHM 1% 1
402 CH 1 UF
10% VREG_GPUPCIE_B1 5 B1 B3 13 VREG_CPUPLL_B3
16 V V_5P0STBY
X5R
R6A11 2 603 MARGIN_GPUPCIE_CPUPLL_AD1 11 AD1 VSS 8
38 IN VREG_V12P0_ISENSE_N VREG_V12P0_ISENSE_N_R 2 VIN- MARGIN_GPUPCIE_CPUPLL_AD0 2 AD0 DGND 10 1 R3F5
1 2 0 OHM
10 OHM 1% 1 R3F2 1 R3E3 5%
402 CH 1 KOHM 1 KOHM X807129-001 TSSOP 2 CH
5% 5% VALUE=1K 402
2 CH 2 EMPTY 1 R3E1 DEFAULT=127 (0X7F)
60 59 58 57 56 55 44 BI PMBUS_DATA 6 SDA 402 402 0 OHM SETPOINT1=GPUPCIE 92(0X5C)
55 64 IN PMBUS_CLK 5 SCL 5%
SETPOINT2=CPUPLL 124(0X7C)
C 8
2 CH
402 C
MON_V12P0_A1 A1
7 1 R3F3 1 R3E2 AD5252 I2C ADDRESS
MON_V12P0_A0 A0
1 KOHM 1 KOHM 0101 1 AD1 AD0 R/W HEX
INA219 I2C ADDRESS 1 R6M4 1 R6N3 5% 5% WRITE 0101 1 1 0 0 0X5C
0 OHM 0 OHM 3 GND
1000 000 R/W HEX 5% 5% 2 EMPTY 2 CH READ 0101 1 1 0 1 0X5D
WRITE 1000 000 0 0X80 402 402
2 CH 2 CH
READ 1000 000 1 0X81 402 402 X820501-001
SOT23-8
V_5P0STBY
U3T1 IC
REF3333
1 IN OUT 2
1 1
C3T8 C3T7
B 2.2 UF
20%
GND 3 0.1 UF
10% B
6.3 V 6.3 V
2 X5R X820467-001 2 X5R
402 SC70 402
3.3V +/-0.15%
V_3P3_VREF_CPUPLL_PCIE
1
C3E5
2.2 UF
20%
6.3 V
2 X5R
402 U3E1 IC
3 VDD AD7992 SCL 10 PMBUS_CLK IN 55
SDA 9 PMBUS_DATA BI 44 55 56 57 58 59 60 64
52 IN VREG_GPUPCIE_FB 4 VIN2/REFIN ALERT/BUSY 8

52 IN VREG_CPUPLL_1P8_FB 5 VIN1
VREG_CPUPLL_PCIE_AS 6 AS
AGND2 7
VREG_CPUPLL_PCIE_CONVST_N 1 CONVST_N* AGND1 2
A 1 R3E8
1 KOHM
1 R3E4
1 KOHM
A
5% 5% X820047-001 MSOP10
2 CH 2 CH
402 402

0100 001 R/W HEX
WRITE 0100 001 0 0X42
READ 0100 001 1 0X43

[PAGE_TITLE=MARGIN, VGPUPCIE, VSBPCIE, VCPUPLL, V12P0, TEMP] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, STANDBY
V_5P0STBY
INA219 I2C ADDRESS V_5P0STBY
U5N3 IC VREG_3P3STBY_FB
D 1001
WRITE 1001
100 R/W HEX
100 0 0X98 INA219 IN 53
D
READ 1001 100 1 0X99 4 VS
V_5P0STBY 1
1 R5M15
1 C5N4
C6N6 0.1 UF 178 KOHM
0.1 UF 10% 1%
10% 1 R5A14 U5A3 IC 2
6.3 V
2 CH
6.3 V 1 KOHM X5R
2 X5R MCP4661 402 402
5% VDD 15
402 12
2 CH VREG_1P2STBY_FB 1 R5B1 2VREG_1P2STBY_FB_D 5 WP_N
402 53 IN P1B
R6N4 20 KOHM 1% P0B 10 VREG_3P3STBY_FB_D
38 IN V5P0STBY_ISENSE_P V5P0STBY_ISENSE_P_R 1 VIN+ 402 CH VREG_1P2STBY_FB_MID 6
1 2 53 OUT P1W
10 OHM 1% C6N4 P0W 9 VREG_3P3STBY_FB_MID 53
402 CH
1 1 UF OUT
10% 7 P1A
16 V P0A 8
X5R
R6N5 2 603
38 IN V5P0STBY_ISENSE_N V5P0STBY_ISENSE_N_R 2 VIN-
55 IN PMBUS_CLK 1 SCL
NC 11
1 2 60 59 58 57 56 55 44
64 BI PMBUS_DATA 2
13
SDA
VSS2 4
10 OHM 1% MARGIN_STBY_A2 A2 3
402 CH 14 VSS
MARGIN_STBY_A1 A1 17 MCP4661 I2C ADDRESS
16 MPAD
MARGIN_STBY_A0 HVC/A0 0101 AD2 AD1 AD0 R/W HEX
PMBUS_DATA 6 1 R5M14 1 R5B3 WRITE 0101 0 1 0 0 0X54
60 59 58 57 56 55 44 BI SDA
1 KOHM 1 KOHM
X854038-001 READ 0101 0 1 0 1 0X55
64 55
IN PMBUS_CLK 5 SCL 5% 5%
C 2 R5N5 1 8 2 CH 2 CH C
MON_V5P0STBY_A1 A1 402 402
3.32 KOHM 1% MON_V5P0STBY_A0 7 A0
402 CH 1 R5N3 BUGBUG: NEED TO DECIDE R VALUE
0 OHM 3 GND BUGBUG: FOR NOMINAL VOLTAGE OF 1.2V
5%
2 CH
402 X820501-001
SOT23-8
V_5P0STBY V_5P0STBY
U5M1 IC U5N2 IC
INA219 INA219
4 INA219 I2C ADDRESS 4
VS VS
1000 011 R/W HEX
B INA219 I2C ADDRESS 1
C5M6
WRITE 1000 011 0 0X86 1
C5N9 B
READ 1000 011 1 0X87
1001 000 R/W HEX 0.1 UF 0.1 UF
WRITE 1001 001 0 0X92 10% 10%
6.3 V 6.3 V
READ 1001 001 1 0X93 2 X5R 2 X5R
402 402
R5M11 R5M16
53 IN V3P3STBY_ISENSE_P V3P3STBY_ISENSE_P_R 1 VIN+ 53 IN V1P2STBY_ISENSE_P V1P2STBY_ISENSE_P_R 1 VIN+
1 2 1 2
10 OHM 1% 1 C5M7 10 OHM 1% 1 C5M10
402 CH 1 UF 402 CH 1 UF
10% 10%
16 V 16 V
X5R X5R
R5M10 2 603 R5N4 2 603
53 IN V3P3STBY_ISENSE_N V3P3STBY_ISENSE_N_R 2 VIN- 53 IN V1P2STBY_ISENSE_N V1P2STBY_ISENSE_N_R 2 VIN-
1 2 1 2
10 OHM 1% 10 OHM 1%
402 CH 402 CH
64 60 59 58 57 56 55 44 BI PMBUS_DATA 6 SDA 64 60 59 58 57 56 55 44 BI PMBUS_DATA 6 SDA

55 IN PMBUS_CLK 5 SCL 55 IN PMBUS_CLK 5 SCL
2 R5M13 1 8 8
MON_V3P3STBY_A1 A1 MON_V1P2STBY_A1 A1
3.32 KOHM 1% 7 A0 7 A0
1 R4N9 2 R4N11 1 MON_V1P2STBY_A0
V_5P0STBY 402 CH 0 OHM
3 GND 5% 3.32 KOHM 1% 3 GND
2 CH 402 CH
402
1 R5M12 2
X820501-001 X820501-001
MON_V3P3STBY_A0 SOT23-8 SOT23-8 A
A 0 OHM
402
5%
CH

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN, V1P2
V_3P3STBY
U3N1 IC
D INA219 V_5P0STBY V_5P0STBY D
4 VS
BUGBUG: NEED TO DECIDE R VALUE
1 BUGBUG: FOR NOMINAL VOLTAGE OF 1.2V
C3N2
0.1 UF
10%
6.3 V 1
2 X5R C4N3
402 0.1 UF
U4B4 IC 10%
6.3 V
2 X5R
R3N4 MCP4661
VDD 15 402
52 IN V1P2_ISENSE_P V1P2_ISENSE_P_R 1 VIN+ 1 R4N12
1 R4B10 12
1 2 1 KOHM VREG_1P2_FB 5 WP_N
C3N3 5% 1 KOHM 52 IN P1B
10 OHM 1% 1 5% P0B 10
402 CH 1 UF 2 CH
10% 2 CH
16 V 402
402 52 OUT VREG_1P2_FB_MID 6 P1W
X5R P0W 9
R3N3 2 603
52 IN V1P2_ISENSE_N V1P2_ISENSE_N_R 2 VIN- MARGIN_V1P2_FB_VSS 7 P1A 8
1 2 P0A
10 OHM 1%
402 CH 55 PMBUS_CLK 1 SCL
IN PMBUS_DATA 2 NC 11
57 56 55 44 BI SDA 4
64 60 59 58 MARGIN_V1P2_A2 13 VSS2
PMBUS_DATA 6 A2 3
60 59 58 57 56 55 44 BI SDA MARGIN_V1P2_A1 14 VSS
PMBUS_CLK A1
55 64 IN 5 SCL 16 MPAD 17
C 8
MARGIN_V1P2_A0 HVC/A0
C
2 R3N1 1
MON_V1P2_A1 A1 1 R4N16 X854038-001
1 R3N2
MON_V1P2_A0 7 A0 49.9 KOHM 1 R4N18
1% 1 KOHM
0 OHM 0 OHM 5% 5%
5% 402 CH 3 GND 2 CH
402 2 CH
2 CH 402
402
X820501-001
SOT23-8
MCP4661 I2C ADDRESS
0101 AD2 AD1 AD0 R/W HEX
WRITE 0101 0 1 1 0 0X56
INA219 I2C ADDRESS READ 0101 0 1 1 1 0X57
1000 100 R/W HEX
WRITE 1000 001 0 0X82
READ 1000 001 1 0X83
B B
A A

8 7 6 5 4 3 2 1
EXTERNAL TEMP SENSORS

ISOLATE CLOSE TO KSB
SMB_CLK 1 R3P7 2 SMB_CLK_EXTTEMP_R 1 R3R13 2 SMB_CLK_EXTTEMP

62 55 25 22 BI BI 61
0 OHM 5% 0 OHM 5%
1 R4D7 2 CPU_TEMP_P_KSB 402 CH 402 CH
OUT 23 64
SMB_DATA 1 R3P6 2 SMB_DATA_EXTTEMP_R 1 R3R14 2 SMB_DATA_EXTTEMP
0 OHM 5% CPU_TEMP_P_EXT 62 55 25 22 BI BI 61
CPU_TEMP_P 402 EMPTY 61 IN
4 OUT 1 0 OHM 5% 0 OHM 5%
1 R4R28 2 C4D3 1 402 CH 402 CH
CPU_TEMP_P_EXT
OUT 61 100 PF C4R4
5% 100 PF PLACE CLOSE ISOLATE CLOSE TO EXT TEMP
0 OHM 5% 50 V 5% TO SENSOR
402 CH 2 EMPTY 50 V
402 2 EMPTY
402
1 R4D8 2 CPU_TEMP_N_KSB
OUT 64 GPU_TEMP_P_EXT
23 61 IN
0 OHM 5%
CPU_TEMP_N 402 EMPTY 1
4 OUT ST4R1 C4R5 V_EXTTEMP
1 R4R29 2 CPU_TEMP_N_EXT 2 1 100 PF PLACE CLOSE
5% TO SENSOR
0 OHM 5% 50 V
402 CH SHORT 2 EMPTY
402
1
61 IN BRD_TEMP_P_EXT C4R2
1 R4D6 2 GPU_TEMP_P_KSB 0.1 UF
OUT 23 10%
0 OHM 5% 64
1
U4R1 IC 6.3 V
GPU_TEMP_P 2 X5R
4 OUT 402 EMPTY 1 C4R1
100 PF PLACE CLOSE
TMP423 402
1 R4R27 2 C4D2 1 DXP1 V+ 8
GPU_TEMP_P_EXT 61 100 PF 5% TO SENSOR
OUT 5% 50 V
0 OHM 5% 2 EMPTY 2 7 SMB_CLK_EXTTEMP
402 CH 50 V 402 DXP2 SCL BI 61
2 EMPTY
402 3 6 SMB_DATA_EXTTEMP
DXP3 SDA BI 61
1 R4D5 2 GPU_TEMP_N_KSB
OUT 64
0 OHM 5% 23 EXT_TEMP_N 4 DXN GND 5
GPU_TEMP_N 402 EMPTY 1
4 OUT
1 R4R26 2 GPU_TEMP_N_EXT
ST4D1 X858059-001
2 1 R4R35 SOT23-8
0 OHM
0 OHM 5% 5%
402 CH SHORT
CH
402 TMP423B I2C ADDRESS
2 1001 100 R/W HEX
1 R3R18 2 BRD_TEMP_P_KSB
OUT 23 WRITE 1001 101 0 0X9A
0 OHM 5% READ 1001 101 1 0X9B V_EXTTEMP
38 23 OUT BRD_TEMP_P 402 EMPTY 2 402
1 R3D30 2 EMPTY
BRD_TEMP_P_EXT 61 50 V
OUT 5%
0 OHM 5% 100 PF
402 CH 1 C3R56 3
Q3R1 1
EMPTY FTP FT3R18
1 1
1 R3R19 2 BRD_TEMP_N_KSB 25 EXT_TEMP_PWR_CTRL 1.1 OHM
OUT 23 IN SOT23 R4R36
0 OHM 5% 1 2 0 OHM
BRD_TEMP_N 402 EMPTY R3R20 5%
38 23 OUT ST4R2 10 KOHM CH
1 R3D31 2 BRD_TEMP_N_EXT 2 1 1% 402
2 V_3P3STBY
0 OHM 5% EMPTY
402 CH SHORT 402
2
1 R4D3 2 EDRAM_TEMP_P_KSB
OUT 23 64
0 OHM 5% V_EXTTEMP
4 OUT EDRAM_TEMP_P 402 EMPTY 1
1 R4R24 2 EDRAM_TEMP_P_EXT
C4D1
OUT 61 100 PF
0 OHM 5% 5%
402 CH 50 V EDRAM_TEMP_P_EXT 1
2 EMPTY 61 IN C3D9
402 0.1 UF V_3P3STBY
1 R4D4 2 EDRAM_TEMP_N_KSB 1 U3R1 IC 10%
OUT 64 23 C4R3 6.3 V
100 PF PLACE CLOSE 2 X5R
0 OHM 5% 5% TO SENSOR
TMP441 402
402 EMPTY 50 V 1 DXP V+ 8
4 OUT EDRAM_TEMP_N 2 EMPTY 1 1
1 R4R25 2 EDRAM_TEMP_N_EXT 402 2 7 SMB_CLK_EXTTEMP C3D10 C3D11
DXN SCL BI 61 0.1 UF 0.1 UF
0 OHM 5% V_EXTTEMP 10% 10%
402 CH 1 EXT_TMP_A1 3 6 SMB_DATA_EXTTEMP 6.3 V 6.3 V
A1 SDA BI 61 2 X5R 2 X5R
R4R34 402 402
0 OHM 4 A0 GND 5
1 R4R31
5% 0 OHM
EMPTY 5% X858003-001
402 2 CH V_EXTTEMP SOT23-8
EXT_TMP_A0
2 402 STITCHING CAPS FOR BRD_TEMP PLANE SPLIT
1 R4R30
0 OHM 1 R4R33
5% 0 OHM
5%
2 EMPTY TMP441 I2C ADDRESS
402 2 EMPTY
402 10011 AD1 AD0 R/W HEX
WRITE 10011 1 0 0 0X9C
1 R4R32 READ 10011 1 0 1 0X9D
0 OHM
5%
2 CH
402
MICROSOFT PROJECT NAME PAGE REV
CORONA_XDK_4L 61/87 1.01
CONFIDENTIAL
8 7 6 5 4 3 2 1
XDK, DEBUG CONNECTORS
D KSB DEBUG BUS

D
J2C2 EMPTY
2X13SOFTTOUCH
PHY MDIO INTERFACE
FAN_TACH_SMM_R A1 B1 WSS_CNTL1 NET NAME MDIO SIGNAL
24 IN A_D1 B_D0 IN 24
24 WSS_CNTL0 A2 A_D3 B_D2 B2 SCART_RGB 24
IN A3 B3
IN
A_GND1 B_GND0
SB_GPIO<4> A4 B4 SB_GPIO<1> SB_GPIO<1> PCIE MDC
24 IN A_D5 B_D4 IN 24
A5 A_D7 B_D6 B5 SB_GPIO<0> 24
A6 B6
IN SB_GPIO<0> PCIE MDIO
A_GND3 B_GND2
24 SB_GPIO<2> A7 A_D9 B_D8 B7 SB_GPIO<3> 24
IN AUD_SPI_CLK_R A8 B8 AUD_SPI_MOSI_R
IN SB_GPIO<2> FPHY MDIO
24 IN A_D11 B_D10 IN 24
A9 A_GND5 B_GND4 B9
AUD_RDY_BSBY_R A10 B10 SB_GPIO<5> SB_GPIO<3> FPHY MDC
24 IN A_D13 B_D12 IN 24
24 AUD_SSB_R A11 A_D15 B_D14 B11 AUD_SPI_MISO_R 24
IN A12 B12
IN SB_GPIO<5> SATA0 MDC
A_GND7 B_GND6
A13 A_NC B_CLK B13
SB_GPIO<4> SATA0 MDIO
27 MH1 MH3 29
28 30 AUD_SPI_MOSI_R SATA1 MDC
MH2 MH4
C AUD_SPI_CLK_R SATA1 MDIO C
X854421-001 WSS_CNTL0 USGBRPA MDC
WSS_CNTL1 USGBRPA MDIO
AUD_RDY_BSBY_R USGBRPB MDC
FAN_TACH USGBRPB MDIO
J2C1
2X5HDR10 V_5P0STBY
26 OUT SPI_SS_N 2 1 SPI_MOSI OUT 26
26 IN SPI_MISO 4 3 SPI_CLK OUT 26 KER_DBG_RXD
6 5 J2C3 OUT 24
8 7 V_3P3 2X7HDR14
9 KER_DBG_TXD 2 1 SMC_DBG_RXD_R OUT 62
24 IN
25 IN SMC_DBG_TXD 4 3
HDR C2C3 25 SMC_DBG_EN 6 5 SMC_RST_XDK_N 1 R2C10 2 SMC_RST_N 22
0.1 UF OUT 8 7 IN
10% 100 OHM 5%
B 6.3 V
X5R 1 C4A12
SMB_CLK_R 10
12
9
11
402 CH V_3P3STBY B
402 13
0.1 UF
10%
6.3 V
2 X5R HDR
402
C2C4 C2B4
0.1 UF 1 UF
10% 10%
PCIEX DEBUG CONNECTOR
61 55 25 22 SMB_CLK 1 R2C6 2 6.3 V 16 V
N: DEBUG BOARDS ONLY BI X5R
402
X5R
603
100 OHM 5%
402 CH V_5P0STBY
I258
SM
J3E1 EMPTY SMB_DATA_R 1 R2C7 2 SMB_DATA 22 25 55 61
PCIEX BI
100 OHM 5%
MIDBUS 1 C2C5 402 CH
2 1 PEX_GPU_SB_L0_DP 4
C2C6
IN 0.1 UF 1 UF
24 PEX_SB_GPU_L0_DP 4 3 PEX_GPU_SB_L0_DN 4 10% 10% 1 R2C4 2
IN PEX_SB_GPU_L0_DN 6 5
IN 6.3 V 16 V EXT_PWR_ON_DBG EXT_PWR_ON_N OUT 37 63 25 64
24 IN 2 X5R X5R 1 KOHM 5%
8 7 PEX_GPU_SB_L1_DP 4 402 603
PEX_SB_GPU_L1_DP 10 9 PEX_GPU_SB_L1_DN
IN 402 CH
24 IN IN 4
24 PEX_SB_GPU_L1_DN 12 11
IN 14 13
16 15
18 17 J4D2
20 19 1X3HDR
22 21 22 GPU_CLK_DN 1 1 R2C2 2
IN SMC_DBG_RXD_R SMC_DBG_RXD
A 24 23
GPU_CLK_DP
2
3
62 IN
100 OHM 5%
OUT 25
A
22 IN 402 CH
X801071-001 EMPTY 1 C2C1
0.01 UF
10%
16 V
N: FOOTPRINT PADS 13-24 REMOVED. 2 X7R
N: REMOVED PADS FREE UP NEEDED 402
BOARD SPACE FOR ROUTING.

[PAGE_TITLE=XDK. DEBUG CONN] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
XDK DEBUG
GCPU JTAG HEADER
J4C1 V_5P0DUAL
2X4HDR V_5P0DUAL
CPU_TDI 1 2 CPU_TMS U2V1 IC
63 5 OUT OUT 5 63
D 5 IN CPU_TDO
CPU_TCLK
3
5
4
6
GPU_TRST_N IN 5 SN74LVC1G14 D
63 5 OUT 5
5 CPU_TRST_N_R 7 8 GPU_TRST_ED_N 5 V_5P0 VCC R2V1 D2G1
IN IN 25 IN DBG_LED0 2 IN OUT 4 DBG_LED0_LED_R 1 2 DBG_LED0_LED 2 1
3 GND N/C 1 249 OHM 1% YELLOW
HDR 402 CH LED SM
1
DB2E4 X801189-001
1
GCPU EEPROM HEADER DB1D2
J4C3 V_3P3
2X3HDR
5 GPU_SROM_SCLK_R 1 2 GPU_SROM_SI 5
U1D1
OUT GPU_SROM_SO_R 3 4 GPU_SROM_WP_N IN DB2C51 2X8RCPT
5 OUT OUT 5
5 OUT GPU_SROM_CS_N_R 5 6 26 IN FLSH_CE_N 2 1 MMC_RST_N
IN 32
4 3 FLSH_WP_N 26 32 34
6 5
BI
HDR GND VIAS
34 32 26 FLSH_DATA<7> 8 7
DB2B11 BI FLSH_DATA<6> 10 9 FLSH_DATA<5>
34 32 26 BI BI 26 32 34
34 32 26 FLSH_DATA<4> 12 11 FLSH_DATA<3> 26 32 34
DB2B21 BI FLSH_DATA<2> 14 13 FLSH_DATA<1>
BI
34 32 26 BI BI 26 32 34
SB JTAG HEADER FLSH_DATA<0> 16 15
DB1C11 34 32 26 BI
J3E2 RCPT
C 2X3HDR DB2C31
C
24 OUT SB_TDI 1 2 SB_TMS OUT 24 DB4B21 V_3P3STBY
24 IN SB_TDO 3 4 SB_TRST OUT 24
24 OUT SB_TCLK 5 6 DB2B31
HDR DB2C41 1 C1R2 1 C1R1 1 C1R3
4.7 UF 0.1 UF 0.1 UF
DB1B11 10% 10% 10%
6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R
DB1D11 603 402 402
FTPS LOCKED FOR FUTURE REVISION DB2G51
DB3E21
DB4C31
FT5T2 FTP
1
LOCATE AT: 4935, 2845 DB3C41 PWR LEDS
1
DB4D11 V_12P0 V_5P0 V_5P0STBY V_3P3 V_3P3STBY
FT4P11 FTP
LOCATE AT: 4495, 4560
B V_3P3
B
V_5P0
1 1 1 1 1
1 C2F7 2 C2F5 R7A3 R2G8 R6A7 R4A8 R4B6
1 3.32 KOHM 1 KOHM 1 KOHM 330 OHM 330 OHM
0.1 UF 4.7 UF D4P1 1% 1% 1% 1% 1%
10% 10%
6.3 V 6.3 V GREEN CH CH CH CH CH
2 EMPTY 1 X5R SM 402 402 402 402 402
402 805 2 LED V_3P3STBY 2 2 2 2 2
R4P1
CPU_CHECKSTOP_N_LED 1 2 CPU_CHECKSTOP_N_LED_C
V_MEM 825 OHM 1% 2 R3P1
J2F1 402 CH 10 KOHM
V_12P0_LED_R
V_5P0_LED_R
V_5P0STBY_LED_R
V_3P3_LED_R
V_3P3STBY_LED_R
1X3HDR 3
R4P2 5%
R2F6 1 1 2 CPU_CHECKSTOP_N_LED_B 1 Q4C2 1 CH
25 IN CPU_PWRGD 1 2 CPU_PWRGD_R 2 1 KOHM 5% XSTR 402
5% 1 KOHM 3 402 CH 2
CH 402 SMC_CPU_CHKSTOP_DETECT 25
HDR BI
3
1 C4C4 R4C4
2 R4P8 1 2 SMC_CPU_CHKSTOP_DETECT_B 1 Q4C1
0.1 UF 10 KOHM
10% 5% 1 KOHM 5% XSTR
6.3 V 402 CH 2
R4P3 2 X5R 1 EMPTY 1 1 1 1 1
J4C2 402 402 LED LED LED LED LED
2 IN CPU_RST_V1P1_N 2 1 CPU_RST_N_2_R SM SM SM SM SM
1 KOHM 5% 2X5HDR R4C7 GREEN GREEN GREEN GREEN GREEN
402 EMPTY 2 1 CPU_CHECKSTOP_N_R 1 2 CPU_CHECKSTOP_N
IN 2 D7A1 2 D2G2 2 D6A1 2 D5A1 2 D4B1 2
63 5 OUT CPU_TMS 4 3 0 OHM 5%
A 5 OUT CPU_TRST_N
CPU_TDO
6
8
5
7
402 CH
CPU_TCLK
A
5 IN OUT 5 63
63 5 OUT CPU_TDI 10 9
EXT_PWR_ON_N OUT 37 62 25 64
1 C4C3 HDR
0.1 UF
10%
6.3 V
2 X5R
402

[PAGE_TITLE=XDK, DEBUG TITAN] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG BOARD, SPYDER CONN
D D
ALL STP POINTS SHALL BE ADDED TO TOP SIDE IN LAYOUT
V_MEM
1
STP7E1
1
C STP7E2
C
43 IN VREG_CPU_VID<1..6>
V_CPUVCS 1 1
STP7C7
61 23 IN CPU_TEMP_P_KSB 1
STP4D4 STP4D5
1 CPU_TEMP_N_KSB OUT 61 23 2 1
STP7C6
3 1
1 STP7C5
STP5D1 4 1
STP7C4
5 1
STP7C3
6 1
1 STP7C2
STP5D2
EDRAM_TEMP_P_KSB 1 STP4D1
1 EDRAM_TEMP_N_KSB OUT 61 23
61 23 IN STP3D1 VREG_CPU_CSSUM 1
44 IN STP7B1
44 IN VREG_CPU_CSCOMP 1
STP7C1
44 IN VREG_CPU_CSREF 1
STP7N1
V_CPUEDRAM
1
STP4E2
GPU_TEMP_P_KSB 1 STP4D2
1 GPU_TEMP_N_KSB OUT 61 23 63 62 37 IN EXT_PWR_ON_N 1
STP3C1
61 23 IN STP4D3
B 1
STP4E1 B
60 59 58 57 56 55 44 BI PMBUS_DATA 1
STP5B1
55 IN PMBUS_CLK 1
STP5B2
V_CPUCORE
1 GND FTS FOR TEST FIXTURES

STP6C1
1 1
FT3M12 FTP FT1R2 FTP
1 1 1
STP6C2 FT1P3 FTP FT6N1 FTP
1 1
FT1T11 FTP FT7M1 FTP
1 1
FT3N1 FTP FT2T6 FTP
1 1
FT2N2 FTP FT4V1 FTP
V_CPUPLL 1 1
FT3N4 FTP FT2T7 FTP
1 1
FT3T9 FTP FT3N2 FTP
1 1
FT2V4 FTP FT1P2 FTP
1
STP4E3 1 1
FT4R1 FTP FT2N1 FTP
1 1
FT7N2 FTP FT6V1 FTP
A A

[PAGE_TITLE=DEBUG BOARD, SPYDER CONN] DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LABELS AND MOUNTING
D D
INTELLIGENT SERIAL NUMBER TARGET.
LB2B1
LABEL
1
1375X250_TARGET
X801181-001
WEST PCB MOUNTING HOLES EAST PCB MOUNTING HOLES

EDGE EDGE EDGE
MTG1B1 MTG4G1 MTG7G1
MTG_HOLE MTG_HOLE MTG_HOLE
C NC9 9 NC9 9 NC9 9 C
EMPTY EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
EDGE
MTG1G1
MTG_HOLE
NC9 9
EMPTY
GND=1,2,3,4,5,6,7,8
B HEAT SINK MOUNTING HOLES B
STD STD
MTG4F1 MTG6F1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG4D1 MTG6D1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
A A

[PAGE_TITLE=LABELS AND MOUNTING] DRAWING
8 7 6 5 4 3 2 1
POWER ARCHITECTURE
DRAWING
TRINITY_FAB_A MICROSOFT PROJECT NAME PAGE REV
<PAGE_TITLE=POWER ARCHITECTURE> Thu Feb 17 10:11:23 2011
CONFIDENTIAL
DRAWING
<PAGE_TITLE=SYSTEM BLOCK DIAGRAM> Thu Feb 17 10:11:23 2011
CONFIDENTIAL
WAVE USB RJ45 HDMI TOSLINK POWER

CONN TRIPPLE
CONN
AUX
CONN
EXT_PWR_ON_N
CONN CONN
RESET/ENABLE DIAGRAM CONN
AVIP CONN
AUD_RST_N AUDIO
DAC
FAN
CONN
PSU_V12P0_EN
HDD ODD PWR STANDBY
SATA CONN SWITCHERS
CONN VR
HDD PWR
ODD CONN
SATA
CONN CPU
VR
VCS
VR
DEBUG VREG_V1P2_EN V1P2

CONN VR
V5P0
EXT_PWR_ON_N
DUAL
VR
SMC_DBG_EN
SMC_RST_N
MEM_RST
VREG_CPU_EN MEM
MEM_SCAN_EN
VREG_CPUCORE_PWRGD
CPU_RST_N
GCPU MEM_SCAN_TOP_EN
A & B
CPU_PWRGD CLAM
MEM_SCAN_BOT_EN
FLASH KSB GPU_RST_N
GPU_RST_DONE
VREG_EFUSE_EN
VEFUSE
VREG_V5P0_EN
V5P0 VR
V3P3
VREG_V3P3_EN
VR
VGPUPCIE
VR
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
V1P8
VR
MEM_SCAN_EN
VREG_VEDRAM_EN
MEM_RST
VEDRAM
VMEM
VREG_VMEM_EN
VR
MEM C & D CLAM
TILT
PWR EJECT
BUTTON BUTTON BORON FPM IR 2 X GAME CONN
DRAWING
<PAGE_TITLE=CLOCK DIAGRAM> Thu Feb 17 10:11:24 2011
CONFIDENTIAL
8 7 6 5 4 3 2 1
COMPONENT STUFFING TABLES GDDR MEM. REFDES TO STUFF
REFDES TOP ONLY TOP & BOT
MARGIN REF DES TO STUFF MARGIN CONTINUED... MARGIN CONTINUED... (4GB) (8GB)
REFDES DBG/XDK RETAIL REFDES DBG/XDK RETAIL REFDES DBG/XDK RETAIL
C5F1 STUFF STUFF
D C1F2 STUFF NO-STUFF R1U5 STUFF NO-STUFF R6A11 STUFF NO-STUFF
C5U9 STUFF STUFF
D
C1F10 STUFF NO-STUFF R2B1 STUFF NO-STUFF R6M3 STUFF NO-STUFF
C6F3 STUFF STUFF
C1F11 STUFF NO-STUFF R2B3 STUFF NO-STUFF R6M4 STUFF NO-STUFF
C6U7 STUFF STUFF
C1G7 STUFF NO-STUFF R2F2 STUFF NO-STUFF U1F2 STUFF NO-STUFF
C7D12 STUFF STUFF
C1G8 STUFF NO-STUFF R2F3 STUFF NO-STUFF U1F3 STUFF NO-STUFF
C7E9 STUFF STUFF
C1G9 STUFF NO-STUFF R2F4 STUFF NO-STUFF U1G2 STUFF NO-STUFF
C7R6 STUFF STUFF
C1G10 STUFF NO-STUFF R2F5 STUFF NO-STUFF U1U1 STUFF NO-STUFF
C7T7 STUFF STUFF
C1G11 STUFF NO-STUFF R2F8 STUFF NO-STUFF U2U1 STUFF NO-STUFF
R5F5 STUFF STUFF
C1G12 STUFF NO-STUFF R2T5 STUFF NO-STUFF U3E1 STUFF NO-STUFF
R5T6 STUFF STUFF
C1G13 STUFF NO-STUFF R2U1 STUFF NO-STUFF U3E2 STUFF NO-STUFF
R5T7 STUFF STUFF
C1U2 STUFF NO-STUFF R3E1 STUFF NO-STUFF U3G2 STUFF NO-STUFF
R5U1 NO-STUFF STUFF
C2F2 STUFF NO-STUFF R3E2 STUFF NO-STUFF U3G3 STUFF NO-STUFF
R5U6 STUFF STUFF
C C2F4 STUFF NO-STUFF R3E3 STUFF NO-STUFF U3T1 STUFF NO-STUFF
C
R6F5 STUFF STUFF
C2F6 STUFF NO-STUFF R3E4 STUFF NO-STUFF U3V1 STUFF NO-STUFF
R6R1 STUFF STUFF
C2E4 STUFF NO-STUFF R3F16 STUFF NO-STUFF U4B1 STUFF NO-STUFF
R6R2 STUFF STUFF
C2E5 STUFF NO-STUFF R3F2 STUFF NO-STUFF U4B2 STUFF NO-STUFF
R6T7 STUFF STUFF
C2F6 STUFF NO-STUFF R3F3 STUFF NO-STUFF U5B2 STUFF NO-STUFF
R6T8 STUFF STUFF
C3G11 STUFF NO-STUFF R3F5 STUFF NO-STUFF U5B6 STUFF NO-STUFF
R6T9 STUFF STUFF
C3G2 STUFF NO-STUFF R3G1 STUFF NO-STUFF U5N1 STUFF NO-STUFF
R6U1 NO-STUFF STUFF
C3G4 STUFF NO-STUFF R3G6 STUFF NO-STUFF U6A1 STUFF NO-STUFF
R7E1 STUFF STUFF
C3U2 STUFF NO-STUFF R3G7 STUFF NO-STUFF
PLEASE SEE BOM VARIANTS FOR STUFFING INSTUCTIONS R7E8 STUFF STUFF
C3U3 STUFF NO-STUFF R3G8 STUFF NO-STUFF ON V1P2 AND STBY MARGINING
R7T1 NO-STUFF STUFF
C3V2 STUFF NO-STUFF R3G9 STUFF NO-STUFF
R7T6 NO-STUFF STUFF
B C4B1 STUFF NO-STUFF R3N6 STUFF NO-STUFF
U5F1 STUFF STUFF B
C4N1 STUFF NO-STUFF R3U1 STUFF NO-STUFF
U5U1 NO-STUFF STUFF
C4N4 STUFF NO-STUFF R3U2 STUFF NO-STUFF
U5U2 NO-STUFF STUFF
C5B15 STUFF NO-STUFF R3U3 STUFF NO-STUFF
U6F1 STUFF STUFF
C5B5 STUFF NO-STUFF R4B1 STUFF NO-STUFF
U6U1 NO-STUFF STUFF
C5B8 STUFF NO-STUFF R4B18 STUFF NO-STUFF
U7D1 STUFF STUFF
C5N7 STUFF NO-STUFF R4B2 STUFF NO-STUFF
U7E1 STUFF STUFF
C5N8 STUFF NO-STUFF R4B3 STUFF NO-STUFF
U7T1 NO-STUFF STUFF
C6A6 STUFF NO-STUFF R4N1 STUFF NO-STUFF
U7T1 NO-STUFF STUFF
C6M5 STUFF NO-STUFF R4N10 STUFF NO-STUFF
J1G3 STUFF NO-STUFF R4N13 STUFF NO-STUFF
Q1F1 STUFF NO-STUFF R4N14 STUFF NO-STUFF

SROM MEMORY REFDES TO STUFF
Q2F3 STUFF NO-STUFF R4N2 STUFF NO-STUFF
REFDES DEBUG CPU DBG XDK RETAIL
Q4B1 STUFF NO-STUFF R4N3 STUFF NO-STUFF
C4R4 STUFF STUFF STUFF NO-STUFF
R1F4 STUFF NO-STUFF R4N4 STUFF NO-STUFF
A R4R7 STUFF STUFF STUFF NO-STUFF
A
R4R9 STUFF STUFF STUFF NO-STUFF
R4R10 NO-STUFF NO-STUFF NO-STUFF NO-STUFF
R1G1 STUFF NO-STUFF R4N8 STUFF NO-STUFF
R1T19 STUFF NO-STUFF R5B6 STUFF NO-STUFF
R1U3 STUFF NO-STUFF R5N2 STUFF NO-STUFF
R1U4 STUFF NO-STUFF R6A10 STUFF NO-STUFF

DRAWING MICROSOFT PROJECT NAME PAGE FAB REV
[PAGE_TITLE=COMPONENT STUFFING TABLES] Thu Feb 17 10:11:24 2011
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2C REFERENCE TABLES

D D
DIGITAL POTENTIOMETERS
VOLTAGE RAIL STEPS STEP SIZE I2C R/W ADDRESS
VMEM 256 0.007031V W: 01011000 0X58, R: 01011001 0X59
VEDRAM 256 0.004199V W: 01011000 0X58, R: 01011001 0X59
V5P0 256 0.011719V W: 01011010 0X5A, R: 01011011 0X5B
V3P3 256 0.008V W: 01011010 0X5A, R: 01011011 0X5B
VREF 256 0.007031V W: 01011110 0X5E, R: 01011111 0X5F
VCS 256 ?V W: 01011110 0X5E, R: 01011111 0X5F
GPUPCIE 256 0.005859V W: 01011100 0X5C, R: 01011101 0X5D
CPUPLL_1P8 256 0.007148V W: 01011100 0X5C, R: 01011101 0X5D
C V1P2STBY ? ?V W: 01010100 0X54, R: 01010101 0X55

C
V3P3STBY ? ?V W: 01010100 0X54, R: 01010101 0X55
V1P2 ? ?V W: 01010110 0X56, R: 01010111 0X57
STEPS/STEPSIZE TB UPDATED
ANALOG TO DIGITAL CONVERTERS

B VOLTAGE RAIL STEPS STEP SIZE I2C R/W ADDRESS B
VMEM 4096 0.001221V W: 01010000 0X50, R: 01010001 0X51
VEDRAM 4096 0.001221V W: 01010000 0X50, R: 01010001 0X51
V5P0 4096 0.000806V W: 01010010 0X52, R: 01010011 0X53
V3P3 4096 0.000806V W: 01010010 0X52, R: 01010011 0X53
VCS 4096 0.000806V W: 01001000 0X48, R: 01001001 0X49
MEM_VREF 4096 0.000806V W: 01000110 0X46, R: 01000111 0X47
GPUPCIE 4096 0.000806V W: 01000010 0X42, R: 01000011 0X43
CPUPLL_1P8 4096 0.000806V W: 01000010 0X42, R: 01000011 0X43

V12P0 ? ?V W: 10000000 0X80, R: 10000001 0X81
TEMP SENSOR ? ?V W: 10011100 0X9C, R: 10011101 0X9D
V5P0STBY ? ?V W: 10011000 0X98, R: 10011001 0X99
V1P2STBY ? ?V W: 10000110 0X86, R: 10000111 0X87
V3P3STBY ? ?V W: 10010010 0X92, R: 10010011 0X93
A
V1P2 ? ?V W: 10000010 0X82, R: 10000011 0X83
A
STEPS/STEPSIZE TB UPDATED

CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CORONA DOC TRACKER
D D
C C
B B
A A

[PAGE_TITLE=DOC TRACKER] CONFIDENTIAL
8 7 6 5 4 3 2 1
Title: Basenet Report CAL_TEMP_N 23A1 23A8 CPU_TMS 5C8 63A8 63D6 FAN1_OUT 23A2 36C6
Design: corona CAL_TEMP_P 23A4 CPU_TRST_N 5C8 63A8 FAN1_Q1_C 36C5
Date: Feb 17 21:27:51 2011 CORE_HF_BGR_PLL 2A1 CPU_TRST_N_R 5C8 63D8 FAN1_Q1_E 36C5
CPU_CHECKSTOP_N 2D1 63A4 CPU_VDDS0_DN 6D8 FAN_OP1_DP 23A7
Base nets and synonyms for CPU_CHECKSTOP_N_LED 63B6 CPU_VDDS0_DP 6D8 FAN_PULLUP 36C2
corona_lib.CORONA(@corona_lib.corona(sch_ CPU_CHECKSTOP_N_LED_B 63A5 CPU_VDDS1_DN 6D8 FAN_TACH 36C1 24B1 25C8
1)) CPU_CHECKSTOP_N_LED_C 63B5 CPU_VDDS1_DP 6D8 FAN_TACH_SMC_R 25C6
Base Signal CPU_CHECKSTOP_N_R 63A6 CPU_VGATE 2B7 FAN_TACH_SMM_R 24B3 62D8
Location([Zone][dir]) CPU_CLK_DN 22B1 2C7 CPU_VREG_APS1 2C1 43C7 FLSH_ALE 26C2 34B5
CPU_CLK_DN_R 22C4 CPU_VREG_APS2 2C1 43D7 FLSH_CE_N 26C2 32B6 34B5 63C3
AUD_L_OUT 33C1 37C7 CPU_CLK_DN_R2 2C7 CPU_VREG_APS3 2C1 43D7 FLSH_CE_N_R 26C4
AUD_RDY_BSBY 24A6 35A3 CPU_CLK_DP 22B1 2C7 CPU_VREG_APS4 2C1 43D7 FLSH_CLE 26C2 32C8 34B5
AUD_RDY_BSBY_R 24B2 24A8 62C8 CPU_CLK_DP_R 22C4 CPU_VREG_APS5 2C1 43D7 FLSH_DATA<0> 63C3
AUD_RST_N 24B2 33B6 CPU_CLK_DP_R2 2C7 CPU_VREG_APS6 2C1 43D7 FLSH_DATA<7..0> 26D7 32A8 32B6 34C8
AUD_R_OUT 33B1 37C7 CPU_CORE_HF_CLKOUT_DN 6D1 DAC_RSET 23C6 FLSH_DATA<1> 63C1
AUD_SPI_CLK 24A6 35A7 CPU_CORE_HF_CLKOUT_DP 6D1 DBG_LED0 25D1 63D3 FLSH_DATA<2> 63C3
AUD_SPI_CLK_R 24B2 24A8 62C8 CPU_DBG0_POST0 3A5 DBG_LED0_LED 63D1 FLSH_DATA<3> 63C1
AUD_SPI_MISO 35A3 24B6 CPU_DBG1_POST1 3A5 DBG_LED0_LED_R 63D2 FLSH_DATA<4> 63C3
AUD_SPI_MISO_R 24B8 24B2 62C5 CPU_DBG2_POST2 3A5 DFM_THIEVING_PADS_REQUIREMENT3 38D5 FLSH_DATA<5> 63C1
AUD_SPI_MOSI 24C6 35A7 CPU_DBG3_POST3 3A5 EDRAM_PSRO_DOUT 2B7 FLSH_DATA<6> 63C3
AUD_SPI_MOSI_R 24B2 24C8 62C5 CPU_DBG4_POST4 3A5 EDRAM_TEMP_N 4B8 61A8 FLSH_DATA<7> 63C3
AUD_SSB 24A3 35A7 CPU_DBG5_POST5 3A5 EDRAM_TEMP_N_EXT 61A7 FLSH_NC38 34C2
AUD_SSB_R 24B2 24A5 62C8 CPU_DBG6_POST6 3A5 EDRAM_TEMP_N_KSB 61A5 64B3 23A8 FLSH_READY 34C1 26B7
AUD_VOUTL 33B4 CPU_DBG7_POST7 3A5 EDRAM_TEMP_P 61B8 4B8 FLSH_RE_N 26C2 34B5
AUD_VOUTL_R 33B3 CPU_DBG8_RST0 3A5 EDRAM_TEMP_P_EXT 61A6 61A5 FLSH_WE_N 26C2 34B5
AUD_VOUTR 33B4 CPU_DBG9_RST1 3A5 EDRAM_TEMP_P_KSB 23A1 61B5 64B6 FLSH_WP_N 26C7 63C1 32A3 32B6
AUD_VOUTR_R 33B3 CPU_DBG10_RST2 3A5 EJECTSW_N 38A8 25C2 35A3 34B5
AV_MODE0 37C3 25C8 37C3 CPU_DBG11_GPU_HB 3A5 EJECTSW_N_R 38A6 GAMEPORT1_DN 26B2 39D8
AV_MODE0_R 25C6 CPU_DBG12_CPUCLK0 3A5 ENET_RX_DN 27C8 38B8 GAMEPORT1_DP 26B2 39D8
AV_MODE1 37C3 25C8 37C3 CPU_DBG13_CPUCLK1 3A5 ENET_RX_DP 27C8 38C8 GAMEPORT2_DN 26C2 39C8
AV_MODE1_R 25C6 CPU_DBG14_GPUCLK0 3A5 ENET_RX_TERM 38C7 GAMEPORT2_DP 26C2 39C8
AV_MODE2 37C3 25B8 37C3 CPU_DBG15_GPUCLK1 3A5 ENET_TX_DN 27C2 38C8 GPU_CLK_DN 22B1 4D8 62A6
AV_MODE2_R 25B6 CPU_DBG_RST_EN 2B7 ENET_TX_DP 27C2 38C8 GPU_CLK_DN_C 4C8
BINDSW_N 38A8 25D2 CPU_DBG_TBCLK0 3D7 ENET_TX_TERM 38C7 GPU_CLK_DN_R 22C4
BINDSW_N_R 38A6 CPU_DBG_TBCLK1 3D7 EXPPORT_PORT1_DN 26B6 39C4 GPU_CLK_DN_R2 4D6
BLEEDER_B 42B2 CPU_DLL_SNIF_OUT 3D7 EXPPORT_PORT1_DP 26B6 39C4 GPU_CLK_DP 22B1 4D8 62A6
BLEEDER_C1 42B2 CPU_EXT_CLK_EN 2B7 EXPPORT_PORT2_DN 26A6 39B4 GPU_CLK_DP_C 4D8
BLEEDER_C2 42B2 CPU_LIMIT_BYPASS 2B1 EXPPORT_PORT2_DP 26B6 39B4 GPU_CLK_DP_R 22C4
BLEEDER_V12P0_B1 42B7 CPU_PLL_BYPASS 2B1 EXPPORT_PORT3_DN 26B6 39A4 GPU_CLK_DP_R2 4D6
BLEEDER_V12P0_B2 42C5 CPU_PSRO0_OUT 2B7 EXPPORT_PORT3_DP 26B6 39A4 GPU_DBG_RST_EN 2B7
BLEEDER_V12P0_C1 42B6 CPU_PWRGD 25A2 2D7 63A8 EXPPORT_RJ45_DN 26B6 38C5 GPU_HSYNC_OUT 4B1 23C6
BLEEDER_V12P0_C2 42B6 CPU_PWRGD_R 63A7 EXPPORT_RJ45_DP 26B6 38C5 GPU_PIX_CLK_1X 4C2 23D7
BLEEDER_V12P0_LOAD 42B5 CPU_RST_N 25B3 2D7 EXT_CLK48_IN 22B6 GPU_RST_DONE 4D2 25B2
BORONFPMPORT_DN 26B2 38B8 CPU_RST_N_2_R 63A7 EXT_CLK48_SEL 22B6 GPU_RST_DONE_R 25B4
BORONFPMPORT_DP 26B2 38B8 CPU_RST_V1P1_N 2D1 63A8 EXT_JTM_SEL 25A4 GPU_RST_N 25A2 4C8
BORONFPM_CLK 25A2 38A8 CPU_SRVID 2B1 51B8 EXT_PCIEX_CLK_DN 22B4 GPU_SROM_CS 5C4
BORONFPM_DATA 25A2 38A8 CPU_TCLK 5C8 63A4 63D8 EXT_PCIEX_CLK_DP 22B4 GPU_SROM_CS_N_R 63C8 5B1
BRD_TEMP_N 23B8 38A8 61B8 CPU_TDI 5C8 63A8 63D8 EXT_PWR_ON_DBG 62A3 GPU_SROM_EN 5C4
BRD_TEMP_N_DIODE 23B7 CPU_TDO 5C8 63A8 63D8 EXT_PWR_ON_N 37D3 62A1 63A4 25C2 GPU_SROM_SCLK 5C4
BRD_TEMP_N_EXT 61B7 CPU_TE 2A6 37C3 64B2 GPU_SROM_SCLK_R 63C8 5B1
BRD_TEMP_N_KSB 61B5 23A8 CPU_TEMP_N 4B8 61C8 EXT_PWR_ON_N_R 25C4 GPU_SROM_SI 5B1 63C6
BRD_TEMP_N_R 38A6 CPU_TEMP_N_EXT 61C7 EXT_TEMP_N 61C4 GPU_SROM_SO 5C4
BRD_TEMP_P 61B8 23C8 38A8 CPU_TEMP_N_KSB 61C5 64C3 23A8 EXT_TEMP_PWR_CTRL 25D2 61B3 GPU_SROM_SO_R 63C8 5B1
BRD_TEMP_P_DIODE 23C7 CPU_TEMP_P 61D8 4B8 EXT_TMP_A0 61A4 GPU_SROM_WP_N 63C6 5B1
BRD_TEMP_P_EXT 61B6 61C5 CPU_TEMP_P_EXT 61D6 61D5 EXT_TMP_A1 61A4 GPU_TEMP_N 4B8 61C8
BRD_TEMP_P_KSB 23A1 61B5 CPU_TEMP_P_KSB 23A1 61D5 64C6 FAN1_FDBK 36B4 23A6 GPU_TEMP_N_EXT 61C7
BRD_TEMP_P_R 38A6 CPU_TINIT 2A6 FAN1_FDBK_R 36B6 GPU_TEMP_N_KSB 61C5 64B3 23A8
CONFIDENTIAL
GPU_TEMP_P 61C8 4C8 MARGIN_VCS_AS 57B5 MA_RDQS0 14B4 15B5 12B8 MB_DQ31 12D4 16D5 17C5
GPU_TEMP_P_EXT 61C6 61C5 MARGIN_VCS_CONVST 57B4 MA_RDQS1 14B4 15B5 12C8 MB_RAS_N 12B1 16B8 17B8
GPU_TEMP_P_KSB 23A1 61C5 64B6 MARGIN_VIN1 57D4 MA_RDQS2 14C4 15C5 12C8 MB_RDQS0 16B5 17B5 12B4
GPU_TRST_ED_N 5B8 63D6 MARGIN_VMEM_VEDRAM_AD0 55C4 MA_RDQS3 14C4 15C5 12D8 MB_RDQS1 16B5 17B5 12C4
GPU_TRST_N 5B8 63D6 MARGIN_VMEM_VEDRAM_AD1 55C4 MA_VREF0 12A7 MB_RDQS2 16C5 17C5 12C4
GPU_VSYNC_OUT 4B1 23C6 MARGIN_VMEM_VREFS_BOT 57A6 MA_WDQS0 12A6 12B8 14B4 15B5 MB_RDQS3 16C5 17C5 12D4
HDD_RX_DN 41C8 27B8 MARGIN_VREFS_AD0 57A6 MA_WDQS1 12B6 12C8 14B4 15B5 MB_VREF0 12A3
HDD_RX_DN_C 41C6 MARGIN_VREFS_AD1 57A6 MA_WDQS2 12C8 14C4 15C5 MB_WDQS0 12A2 12B4 16B5 17B5
HDD_RX_DP 41C8 27B8 MARGIN_VREFS_AS 57D4 MA_WDQS3 12D8 14C4 15C5 MB_WDQS1 12B2 12C4 16B5 17B5
HDD_RX_DP_C 41C6 MARGIN_VREFS_CONVST 57C4 MA_WE_N 12B5 14B8 15B8 MB_WDQS2 12C4 16C5 17C5
HDD_TX_DN 27A1 41D8 MA_A<11..0> 12C5 14C8 15C8 MA_ZQ_BOT 15B5 MB_WDQS3 12D4 16C5 17C5
HDD_TX_DN_C 41D6 MA_BA<2..0> 12C5 14C8 15C8 MA_ZQ_TOP 14B5 MB_WE_N 12B1 16B8 17B8
HDD_TX_DP 27A1 41D8 MA_CAS_N 12B5 14B8 15B8 MB_A<11..0> 12C1 16C8 17C8 MB_ZQ_BOT 17A5
HDD_TX_DP_C 41D6 MA_CKE 12B5 14B8 15B8 MB_BA<2..0> 12C1 16B8 17B8 MB_ZQ_TOP 16A5
HDMI_CEC 40B3 MA_CLK0_DN 12C5 14D8 MB_CAS_N 12B1 16B8 17B8 MC_A<11..0> 13C5 18C8 19C8
HDMI_DDC_CLK 23A2 37D3 40A8 55D8 MA_CLK0_DP 12C5 14D8 MB_CKE 12B1 16B8 17B8 MC_BA<2..0> 13C5 18B8 19B8
HDMI_DDC_DATA 23A2 37C3 40A8 55D8 MA_CLK1_DN 12C5 15D8 MB_CLK0_DN 12C1 16C8 MC_CAS_N 13B5 18B8 19B8
HDMI_HPD 40A1 23B6 MA_CLK1_DP 12C5 15D8 MB_CLK0_DP 12C1 16D8 MC_CKE 13C5 18B8 19B8
HDMI_HPD_PIN 40A3 MA_CS0_N 12B5 14B8 MB_CLK1_DN 12C1 17C8 MC_CLK0_DN 13C5 18D8
HDMI_TX0_DN 23A1 40C8 MA_CS1_N 12B5 14B8 15B8 MB_CLK1_DP 12C1 17D8 MC_CLK0_DP 13C5 18D8
HDMI_TX0_DP 23B1 40C8 MA_DM0 12B8 14B4 15B5 MB_CS0_N 12B1 16B8 MC_CLK1_DN 13C5 19D8
HDMI_TX0_DP_R 23B2 MA_DM1 12C8 14B4 15B5 MB_CS1_N 12B1 16B8 17B8 MC_CLK1_DP 13D5 19D8
HDMI_TX1_DN 23B1 40C8 MA_DM2 12C8 14C4 15C5 MB_DM0 12B4 16B5 17B5 MC_CS0_N 13B5 18B8
HDMI_TX1_DP 23B1 40D8 MA_DM3 12D8 14C4 15C5 MB_DM1 12C4 16B5 17B5 MC_CS1_N 13B5 18B8 19B8
HDMI_TX1_DP_R 23B2 MA_DQ0 12B8 14B4 15B5 MB_DM2 12C4 16C5 17C5 MC_DM0 13B8 18B4 19B4
HDMI_TX2_DN 23B1 40D8 MA_DQ1 12B8 14B4 15B5 MB_DM3 12D4 16C5 17C5 MC_DM1 13C8 18B4 19B4
HDMI_TX2_DP 23B1 40D8 MA_DQ2 12B8 14B4 15B5 MB_DQ0 12B4 16B5 17B5 MC_DM2 13C8 18C4 19C4
HDMI_TX2_DP_R 23B2 MA_DQ3 12B8 14B4 15B5 MB_DQ1 12B4 16B5 17B5 MC_DM3 13D8 18C4 19C4
HDMI_TXC_DN 23C1 40B8 MA_DQ4 12B6 12B8 14B4 15B5 MB_DQ2 12B4 16B5 17B5 MC_DQ0 13B8 18B4 19B4
HDMI_TXC_DP 23C1 40B8 MA_DQ5 12B8 14B4 15C5 MB_DQ3 12B4 16B5 17B5 MC_DQ1 13B8 18B4 19B4
HDMI_TXC_DP_R 23C2 MA_DQ6 12B8 14B4 15C5 MB_DQ4 12B2 12B4 16B5 17B5 MC_DQ2 13B8 18B4 19B4
I2S_BCLK 27B1 33B7 MA_DQ7 12B8 14B4 15C5 MB_DQ5 12B4 16B5 17B5 MC_DQ3 13B8 18B4 19B4
I2S_BCLK_R 27B4 MA_DQ8 12C8 14B4 15B5 MB_DQ6 12B4 16B5 17B5 MC_DQ4 13B6 13B8 18B4 19B4
I2S_MCLK 27B1 33B7 MA_DQ9 12C8 14B4 15B5 MB_DQ7 12B4 16B5 17B5 MC_DQ5 13B8 18B4 19B4
I2S_MCLK_R 27B4 MA_DQ10 12C8 14B4 15B5 MB_DQ8 12C4 16B5 17B5 MC_DQ6 13B8 18B4 19B4
I2S_SD 27B1 33B7 MA_DQ11 12C8 14B4 15B5 MB_DQ9 12C4 16B5 17B5 MC_DQ7 13B8 18B4 19C4
I2S_SD_R 27B4 MA_DQ12 12B6 12C8 14B4 15B5 MB_DQ10 12C4 16B5 17B5 MC_DQ8 13C8 18B4 19B4
I2S_WS 27B1 33B7 MA_DQ13 12C8 14B4 15B5 MB_DQ11 12C4 16B5 17B5 MC_DQ9 13C8 18B4 19B4
I2S_WS_R 27B4 MA_DQ14 12C8 14C4 15B5 MB_DQ12 12B2 12C4 16B5 17B5 MC_DQ10 13C8 18B4 19B4
IR_DATA 35B5 25A7 MA_DQ15 12C8 14C4 15B5 MB_DQ13 12C4 16B5 17B5 MC_DQ11 13C8 18B4 19B4
KER_DBG_RXD 62B1 24C6 MA_DQ16 12C8 14C4 15C5 MB_DQ14 12C4 16B5 17B5 MC_DQ12 13B6 13C8 18B4 19B4
KER_DBG_TXD 24C1 62B5 MA_DQ17 12C8 14C4 15C5 MB_DQ15 12C4 16B5 17B5 MC_DQ13 13C8 18B4 19B4
KER_DBG_TXD_R 24C3 MA_DQ18 12C8 14C4 15C5 MB_DQ16 12C4 16C5 17C5 MC_DQ14 13C8 18C4 19B4
KSB_DEBUG 24B3 MA_DQ19 12C8 14C4 15C5 MB_DQ17 12C4 16C5 17C5 MC_DQ15 13C8 18C4 19B4
KSB_RSET 23B5 MA_DQ20 12C8 14C4 15D5 MB_DQ18 12C4 16C5 17C5 MC_DQ16 13C8 18C4 19C4
LVLCNT 37C7 MA_DQ21 12C8 14C4 15D5 MB_DQ19 12C4 16C5 17C5 MC_DQ17 13C8 18C4 19C4
MARGIN_GPUPCIE_CPUPLL_AD0 58C4 MA_DQ22 12C8 14C4 15D5 MB_DQ20 12C4 16C5 17C5 MC_DQ18 13C8 18C4 19C4
MARGIN_GPUPCIE_CPUPLL_AD1 58C4 MA_DQ23 12C8 14C4 15D5 MB_DQ21 12C4 16C5 17C5 MC_DQ19 13C8 18C4 19C4
MARGIN_STBY_A0 59C4 MA_DQ24 12D8 14C4 15C5 MB_DQ22 12C4 16C5 17C5 MC_DQ20 13C8 18C4 19C4
MARGIN_STBY_A1 59C4 MA_DQ25 12D8 14C4 15C5 MB_DQ23 12C4 16C5 17D5 MC_DQ21 13C8 18C4 19C4
MARGIN_STBY_A2 59C4 MA_DQ26 12D8 14C4 15C5 MB_DQ24 12D4 16C5 17C5 MC_DQ22 13C8 18C4 19D4
MARGIN_V1P2_A0 60C4 MA_DQ27 12D8 14C4 15C5 MB_DQ25 12D4 16C5 17C5 MC_DQ23 13D8 18C4 19D4
MARGIN_V1P2_A1 60C4 MA_DQ28 12D8 14C4 15C5 MB_DQ26 12D4 16C5 17C5 MC_DQ24 13D8 18C4 19C4
MARGIN_V1P2_A2 60C4 MA_DQ29 12D8 14D4 15C5 MB_DQ27 12D4 16C5 17C5 MC_DQ25 13D8 18C4 19C4
MARGIN_V1P2_FB_VSS 60C4 MA_DQ30 12D8 14D4 15C5 MB_DQ28 12D4 16C5 17C5 MC_DQ26 13D8 18C4 19C4
MARGIN_V3P3_V5P0_AD0 56C6 MA_DQ31 12D8 14D4 15C5 MB_DQ29 12D4 16C5 17C5 MC_DQ27 13D8 18C4 19C4
MARGIN_V3P3_V5P0_AD1 56C6 MA_RAS_N 12B5 14B8 15B8 MB_DQ30 12D4 16C5 17C5 MC_DQ28 13D8 18C4 19C4
CONFIDENTIAL
MC_DQ29 13D8 18D4 19C4 MD_DQ27 13D4 20D4 21C5 MMC_ISOLT 32C5 RESISTOR0_DN 2B7
MC_DQ30 13D8 18D4 19C4 MD_DQ28 13D4 20D4 21C5 MMC_RSTCLK 32C5 RESISTOR0_DP 2B7
MC_DQ31 13D8 18D4 19C4 MD_DQ29 13D4 20D4 21C5 MMC_RST_N 32C7 63C1 SB_GPIO<0> 24A2 62D5
MC_RAS_N 13B5 18B8 19B8 MD_DQ30 13D4 20D4 21C5 MMC_SD_SEL 32C5 SB_GPIO<0..15> 24D5
MC_RDQS0 18B4 19B4 13B8 MD_DQ31 13D4 20D4 21C5 MMC_V12 32C6 SB_GPIO<1> 24A2 62D5
MC_RDQS1 18B4 19B4 13C8 MD_RAS_N 13B1 20B8 21B8 MON_V1P2STBY_A0 59A2 SB_GPIO<2> 24A2 62C8
MC_RDQS2 18C4 19C4 13C8 MD_RDQS0 20B4 21B5 13B4 MON_V1P2STBY_A1 59A2 SB_GPIO<3> 24A2 62C5
MC_RDQS3 18C4 19C4 13D8 MD_RDQS1 20B4 21B5 13C4 MON_V1P2_A0 60C6 SB_GPIO<4> 24A2 62D8
MC_VREF0 13A7 MD_RDQS2 20C4 21C5 13C4 MON_V1P2_A1 60C6 SB_GPIO<5> 24B2 62C5
MC_WDQS0 13B5 13B8 18B4 19B4 MD_RDQS3 20C4 21C5 13D4 MON_V3P3STBY_A0 59A6 SB_MAIN_PWRGD 25A8 22C2
MC_WDQS1 13B5 13C8 18B4 19B4 MD_VREF0 13A3 MON_V3P3STBY_A1 59A6 SB_MAIN_PWRGD_R 25A6
MC_WDQS2 13C8 18C4 19C4 MD_WDQS0 13B4 20B4 21B5 MON_V5P0STBY_A0 59C6 SB_RST_N 25A7 22C1
MC_WDQS3 13D8 18C4 19C4 MD_WDQS1 13B2 13C4 20B4 21B5 MON_V5P0STBY_A1 59C6 SB_RST_N_R 22C4
MC_WE_N 13B5 18B8 19B8 MD_WDQS2 13C4 20C4 21C5 MON_V12P0_A0 58C6 SB_TCLK 63C8 24A6
MC_ZQ_BOT 19B5 MD_WDQS3 13D4 20C4 21C5 MON_V12P0_A1 58C6 SB_TDI 63C8 24A6
MC_ZQ_TOP 18B5 MD_WE_N 13B1 20B8 21B8 ODD_RX_DN 41A8 27B8 SB_TDO 24A6 63C8
MD_A<11..0> 13C1 20C8 21C8 MD_ZQ_BOT 21B5 ODD_RX_DN_C 41A7 SB_TMS 63C6 24A6
MD_BA<2..0> 13C1 20C8 21B8 MD_ZQ_TOP 20B5 ODD_RX_DP 41A8 27B8 SB_TRST 63C6 24A6
MD_CAS_N 13B1 20B8 21B8 MEM_A_VREF0 15A6 14B8 15B8 ODD_RX_DP_C 41A7 SCART_RGB 24B2 37B8 62D5
MD_CKE 13C1 20B8 21B8 MEM_A_VREF1 14A6 14B8 15B8 ODD_TX_DN 27A1 41A8 SCART_RGB_OUT 37B6
MD_CLK0_DN 13C1 20D8 MEM_B_VREF0 17A6 16B8 17B8 ODD_TX_DN_C 41A7 SCART_RGB_OUT_R 37B7
MD_CLK0_DP 13C1 20D8 MEM_B_VREF1 16A6 16B8 17B8 ODD_TX_DP 27A1 41B8 SCART_RGB_R 37B7
MD_CLK1_DN 13C1 21D8 MEM_CALA 4A6 ODD_TX_DP_C 41B7 SMB_CLK 22B8 25B8 55D8 61D3
MD_CLK1_DP 13D1 21D8 MEM_CALB 4A6 PEX_GPU_SB_L0_DN 4C2 24C7 62A6 62B5
MD_CS0_N 13B1 20B8 MEM_C_VREF0 19A6 18B8 19B8 PEX_GPU_SB_L0_DN_C 4C4 SMB_CLK_EXTTEMP 61A2 61C2 61D1
MD_CS1_N 13B1 20B8 21B8 MEM_C_VREF1 18A6 18B8 19B8 PEX_GPU_SB_L0_DP 4C2 24C7 62A6 SMB_CLK_EXTTEMP_R 61D2
MD_DM0 13B4 20B4 21B5 MEM_D_VREF0 21A6 20B8 21B8 PEX_GPU_SB_L0_DP_C 4C4 SMB_CLK_R 62B4
MD_DM1 13C4 20B4 21B5 MEM_D_VREF1 20A6 20B8 21B8 PEX_GPU_SB_L1_DN 4C2 24C7 62A6 SMB_DATA 22B8 25B8 55C8 61D3
MD_DM2 13C4 20C4 21C5 MEM_RST 4B1 14D8 15D8 16C8 PEX_GPU_SB_L1_DN_C 4C4 62A1
MD_DM3 13D4 20C4 21C5 17C8 18D8 19C8 20D8 21D8 PEX_GPU_SB_L1_DP 4D2 24C7 62A6 SMB_DATA_EXTTEMP 61A2 61C2 61D1
MD_DQ0 13B4 20B4 21B5 MEM_SCAN_BOT_EN 4A1 15B8 17B8 19B8 PEX_GPU_SB_L1_DP_C 4D4 SMB_DATA_EXTTEMP_R 61D2
MD_DQ1 13B4 20B4 21B5 21B8 PEX_RCAL 4C6 SMB_DATA_R 62A3
MD_DQ2 13B4 20B4 21B5 MEM_SCAN_BOT_EN_N 4A4 PEX_SB_GPU_L0_DN 24C1 4C8 62A8 SMC_CPU_CHKSTOP_DETECT 25A7 63A3
MD_DQ3 13B4 20B4 21B5 MEM_SCAN_EN 4A1 14B8 15B8 16B8 PEX_SB_GPU_L0_DN_C 24C3 SMC_CPU_CHKSTOP_DETECT_B 63A5
MD_DQ4 13B4 20B4 21B5 17B8 18B8 19B8 20B8 21B8 PEX_SB_GPU_L0_DP 24C1 4C8 62A8 SMC_DBG_EN 62B5 25C8
MD_DQ5 13B4 20B4 21B5 MEM_SCAN_TOP_EN 4A1 14B8 16B8 18B8 PEX_SB_GPU_L0_DP_C 24C3 SMC_DBG_RXD 62A2 25C8
MD_DQ6 13B4 20B4 21C5 20B8 PEX_SB_GPU_L1_DN 24D1 4C8 62A8 SMC_DBG_RXD_R 62B1 62A5
MD_DQ7 13B4 20B4 21C5 MEM_VREFS 57A6 57D4 PEX_SB_GPU_L1_DN_C 24D3 SMC_DBG_TXD 25D2 62B5
MD_DQ8 13C4 20B4 21B5 MEM_VREFS_R 57A6 PEX_SB_GPU_L1_DP 24D1 4C8 62A8 SMC_DBG_TXD_R 25D4
MD_DQ9 13C4 20B4 21B5 MMC_DV_CARD 32C5 PEX_SB_GPU_L1_DP_C 24D3 SMC_P0_GPIO5 25B4
MD_DQ10 13C4 20B4 21B5 MMC_EMBED_SEL 32C5 PIX_CLK_2X_DN 22A1 4C8 SMC_PWM0 25A2 23A8
MD_DQ11 13C4 20B4 21B5 MMC_FLSH_ALE 32B3 PIX_CLK_2X_DN_R 22B4 SMC_PWM1 25A2 36A6
MD_DQ12 13B2 13C4 20C4 21B5 MMC_FLSH_CE0_N 32B3 PIX_CLK_2X_DP 22A1 4C8 SMC_PWM1_R 36A3
MD_DQ13 13C4 20C4 21B5 MMC_FLSH_CE1_N 32B3 PIX_CLK_2X_DP_R 22B4 SMC_RST_N 22C1 25D8 42B3 62B1
MD_DQ14 13C4 20C4 21B5 MMC_FLSH_CLE 32B3 PIX_DATA<14..0> 4C2 23D7 SMC_RST_N_R 22C4
MD_DQ15 13C4 20C4 21B5 MMC_FLSH_DATA0 32C3 PMBUS_CLK 55D6 44C8 55A2 55D1 SMC_RST_XDK_N 62B3
MD_DQ16 13C4 20C4 21C5 MMC_FLSH_DATA1 32C3 56B1 56D4 57B2 57C2 57D1 58A5 58C8 58D1 SPDIF_OUT 27B1 37D8 39A8
MD_DQ17 13C4 20C4 21C5 MMC_FLSH_DATA2 32C3 59A4 59A7 59C5 59C8 60C4 60C8 64B2 SPDIF_OUT_R 27B4
MD_DQ18 13C4 20C4 21C5 MMC_FLSH_DATA3 32C3 PMBUS_DATA 44C8 55A2 55D1 55D6 SPI_CLK 62B6 26D7
MD_DQ19 13C4 20C4 21C5 MMC_FLSH_DATA4 32C3 56B1 56D3 57A2 57C2 57D1 58A5 58C8 58D1 SPI_MISO 26D2 62B8
MD_DQ20 13C4 20C4 21C5 MMC_FLSH_DATA5 32C3 59A4 59A7 59C5 59C8 60C4 60C8 64B2 SPI_MISO_R 26D4
MD_DQ21 13C4 20C4 21D5 MMC_FLSH_DATA6 32C3 POR_BYPASS 22C6 SPI_MOSI 62B6 26D7
MD_DQ22 13C4 20C4 21D5 MMC_FLSH_DATA7 32C3 POST_IN<0..4> 3C4 SPI_SS_N 62B8 26D7
MD_DQ23 13D4 20C4 21D5 MMC_FLSH_READY 32B3 PSU_V12P0_EN 25A7 38A4 42B8 SPKR_DRIVE_N 35A3
MD_DQ24 13D4 20C4 21C5 MMC_FLSH_RE_N 32B3 PSU_V12P0_EN_R 38A2 SPKR_DRIVE_P 35A3
MD_DQ25 13D4 20C4 21C5 MMC_FLSH_WE_N 32B3 PWRSW_N 38A8 25C2 35A3 TILTSW_N 35C3 25C2
MD_DQ26 13D4 20C4 21C5 MMC_FLSH_WP_N 32B3 PWRSW_N_R 35B3 38A8 TILTSW_N_R 35C5
CONFIDENTIAL
TRAY_OPEN 25A7 41A1 VREG_1P2STBY_SW 53C5 VREG_CPU_SW2_R 45C3 VREG_V5P0_IOUT 56B5
TRAY_OPEN_R 25A6 VREG_1P2_EN 25C8 52C8 VREG_CPU_SW3 44C4 VREG_V5P0_ISENSE_N 47C1 56B7
TRAY_STATUS 41A4 25A7 VREG_1P2_EN_R 25C6 VREG_CPU_SW4 44C4 VREG_V5P0_ISENSE_P 47C1 56B7
TRAY_STATUS_R 41A3 VREG_1P2_FB 52C4 60D4 VREG_CPU_TRDET 44C4 VREG_V5P0_PGND 47B5
USBB_D1_DN 26B4 VREG_1P2_FB_MID 60C4 52C4 VREG_CPU_TRDET_R 44A6 VREG_V5P0_PWRGD 47D1 25C2
USBB_D1_DP 26B4 VREG_1P2_PWRGD 52C8 VREG_CPU_VCC 44C1 44D1 VREG_V5P0_RAMP 47C5
V1P2STBY_ISENSE_N 53D2 59A4 VREG_3P3STBY_EN 53A7 VREG_CPU_VCC3_3P3 44D3 VREG_V5P0_RSENSE 47C3
V1P2STBY_ISENSE_N_R 59A3 VREG_3P3STBY_FB 53A1 59D1 VREG_CPU_VID<6..1> 43C2 44D1 64C2 VREG_V5P0_SEL 25C2 46C7
V1P2STBY_ISENSE_P 53D2 59B4 VREG_3P3STBY_FB_CHIP 53A4 VREG_EFUSE_EN 2B1 52A4 VREG_V5P0_SEL_B1 46C6
V1P2STBY_ISENSE_P_R 59B3 VREG_3P3STBY_FB_D 59D3 VREG_EFUSE_VOUT 52A2 VREG_V5P0_SEL_B2 46C5
V1P2_ISENSE_N 52D4 60C8 VREG_3P3STBY_FB_MID 59C1 53A1 VREG_GPUPCIE_B1 58C4 VREG_V5P0_SEL_C 46C6
V1P2_ISENSE_N_R 60C6 VREG_3P3STBY_FB_R 53A3 VREG_GPUPCIE_FB 52C1 58A8 58D5 VREG_V5P0_SEL_NGATE 46C5
V1P2_ISENSE_P 52D4 60D8 VREG_3P3STBY_SW 53A5 VREG_GPUPCIE_FB_MID 58D5 52C1 VREG_V5P0_SEL_PGATE 46C5
V1P2_ISENSE_P_R 60D6 VREG_CPU1_VCC 45B7 VREG_PCIEX_ADJUST 52C3 VREG_V5P0_SS 47A7
V3P3STBY_ISENSE_N 53B1 59A7 VREG_CPU2_VCC 45D7 VREG_PCIEX_R 52C2 VREG_V5P0_SW 47B5
V3P3STBY_ISENSE_N_R 59A6 VREG_CPUCORE_PWRGD 44D1 25A7 VREG_V3P3_BST 48C5 VREG_V5P0_SW_S 47C4
V3P3STBY_ISENSE_P 53B1 59B7 VREG_CPUPLL_1P8_FB 52A5 58A8 58D1 VREG_V3P3_CF1 56A6 VREG_V5P0_TRK 47C7
V3P3STBY_ISENSE_P_R 59B6 VREG_CPUPLL_1P8_FB_MID 58D1 52A5 VREG_V3P3_COMP 48A8 VREG_V12P0_ISENSE_N 38B1 58C8
V5P0STBY_CONN 38A2 VREG_CPUPLL_ADJUST 52A8 VREG_V3P3_COMP_C 48A7 VREG_V12P0_ISENSE_N_R 58C6
V5P0STBY_ISENSE_N 38A2 59C8 VREG_CPUPLL_B3 58C2 VREG_V3P3_DH 48C5 VREG_V12P0_ISENSE_P 38B1 58D8
V5P0STBY_ISENSE_N_R 59C6 VREG_CPUPLL_PCIE_AS 58A7 VREG_V3P3_DL 48B5 VREG_V12P0_ISENSE_P_R 58D6
V5P0STBY_ISENSE_P 38A2 59D8 VREG_CPUPLL_PCIE_CONVST_N 58A7 VREG_V3P3_EN 25C2 48C8 VREG_VCS_CF1 57C7
V5P0STBY_ISENSE_P_R 59D6 VREG_CPUPLL_R 52A7 VREG_V3P3_FB 48B1 56D1 VREG_VCS_CF2 57C7
V5P0_EXPPORT_RJ45 38D5 VREG_CPU_ALERT_N 44C2 VREG_V3P3_FB_A3 56D4 VREG_VCS_COMP 51B6
V12P0_EXPPORT_RJ45 38D5 VREG_CPU_BST1 45B5 VREG_V3P3_FB_MID 48A1 56C1 VREG_VCS_COMP_R 51A6
V12P0_PWRGD 22D3 25B8 42B8 VREG_CPU_BST1_R 45A5 VREG_V3P3_FB_MID_R 56C4 VREG_VCS_FB 51A1 57A2 57C8
VAA_3P3STBY_USB_FET 30B5 VREG_CPU_BST2 45D5 VREG_V3P3_FB_R 56A4 VREG_VCS_FB_MID 51A1 57A2
VAA_3P3STBY_USB_FET_EN 30B5 VREG_CPU_BST2_R 45D5 VREG_V3P3_ILIM 48B5 VREG_VCS_FB_MID_R 57A4
VAA_3P3_HDMI 31C4 VREG_CPU_COMP 44C4 VREG_V3P3_IOUT 56A5 VREG_VCS_HDRV 51C5
VAA_3P3_HDMI_FET_EN 31D2 VREG_CPU_COMP_R 44A6 VREG_V3P3_ISENSE_N 48C1 56A7 VREG_VCS_HDRV_R 51C4
VAA_3P3_LDO25 31B4 VREG_CPU_CSCOMP 44C8 64B2 VREG_V3P3_ISENSE_P 48C1 56A7 VREG_VCS_IN 57B7
VCC_WAVEPORT 39B6 VREG_CPU_CSCOMP_R 44B6 VREG_V3P3_PGND 48B5 VREG_VCS_IOUT 57C6
VDD18_OUT_CAP 30B2 VREG_CPU_CSREF 44C8 64B2 VREG_V3P3_PWRGD 48D1 25C1 VREG_VCS_IOUT2 57C6
VDD25_OUT_CAP 31C4 VREG_CPU_CSSUM 44C8 64B2 VREG_V3P3_RAMP 48D5 VREG_VCS_ISENSE_N 51C1 57C8
VDD_3P3_LDO18 30C2 VREG_CPU_DRVH1 45A5 VREG_V3P3_RSENSE 48C3 VREG_VCS_ISENSE_P 51C1 57C8
VID_DACA_DP 23D2 37B8 VREG_CPU_DRVH2 45C5 VREG_V3P3_SS 48A7 VREG_VCS_LDRV 51B5
VID_DACA_DP_L 37B7 VREG_CPU_DRVL1 45A5 VREG_V3P3_SW 48C5 VREG_VCS_LDRV_R 51B4
VID_DACA_OUT 37B4 37D7 VREG_CPU_DRVL2 45C5 VREG_V3P3_SW_S 48C3 VREG_VCS_NC 51C6
VID_DACB_DP 23D2 37A8 VREG_CPU_DRV_EN 44C1 45C8 VREG_V3P3_TRK 48C7 VREG_VCS_NC1 51C6
VID_DACB_DP_L 37A7 VREG_CPU_EN 25A8 44D8 VREG_V3P3_V5P0_FREQ 47B7 VREG_VCS_NC2 51C6
VID_DACB_OUT 37A4 37D7 VREG_CPU_FAULT_N 44C2 VREG_V3P3_V5P0_SYNC 47C7 VREG_VCS_OCP 51C6
VID_DACC_DP 23D2 37B4 VREG_CPU_FB 44A6 44C4 VREG_V3P3_V5P0_VCCO 47D1 48D8 VREG_VCS_SS_SD_N 51B6
VID_DACC_DP_L 37B3 VREG_CPU_FBRTN 44B3 44C4 VREG_V3P3_V5P0_VDL 47D7 VREG_VCS_VOUT 51B3
VID_DACC_OUT 37B1 37D7 VREG_CPU_ILIMITFS 44B4 VREG_V5P0_BST 47C5 VREG_VCS_VOUT_L 51B3
VID_DACD_DP 23D2 37A4 VREG_CPU_IMON 44C2 VREG_V5P0_CF2 56A6 VREG_VCS_VP 51C6
VID_DACD_DP_L 37A3 VREG_CPU_IREF 44C4 VREG_V5P0_COMP 47A8 VREG_VEDRAM_BST 49C5
VID_DACD_OUT 37A1 37C7 VREG_CPU_OD1_N 44C2 VREG_V5P0_COMP_C 47A8 VREG_VEDRAM_CF1 55A6
VID_HSYNC_OUT 37B1 37C7 VREG_CPU_PHASE1 45A1 44C8 VREG_V5P0_DH 47C5 VREG_VEDRAM_COMP 49A7
VID_HSYNC_OUT_R 23C3 37B3 VREG_CPU_PHASE1_R 44C4 VREG_V5P0_DL 47B5 VREG_VEDRAM_COMP_C 49A7
VID_VSYNC_OUT 37B3 37C7 VREG_CPU_PHASE2 45C1 44C8 VREG_V5P0_EN 25D2 47B8 VREG_VEDRAM_DH 49C5
VID_VSYNC_OUT_R 23C3 37B5 VREG_CPU_PHASE2_R 44C4 VREG_V5P0_EN_R 47B7 VREG_VEDRAM_DL 49B5
VREG_1P2STBY_EN 53C6 VREG_CPU_PWM1 44C1 45A8 VREG_V5P0_FB 47A1 56D8 VREG_VEDRAM_EN 25C2 49B8
VREG_1P2STBY_FB 53B1 59D5 VREG_CPU_PWM2 44C1 45C8 VREG_V5P0_FB_A1 56D6 VREG_VEDRAM_FB 49B1 55A7 55D1
VREG_1P2STBY_FB_CHIP 53C5 VREG_CPU_RAMPADJ 44D4 VREG_V5P0_FB_MID 47A1 56C8 VREG_VEDRAM_FB_MID 49A1 55C1
VREG_1P2STBY_FB_D 59D4 VREG_CPU_RAMPADJ_R 44D5 VREG_V5P0_FB_MID_R 56C6 VREG_VEDRAM_FB_MID_R 55C3
VREG_1P2STBY_FB_MID 59D5 53B1 VREG_CPU_RT 44C2 VREG_V5P0_FB_R 56A4 VREG_VEDRAM_FREQ 49B7
VREG_1P2STBY_FB_R 53B3 VREG_CPU_SW1_R 45A2 VREG_V5P0_ILIM 47B5 VREG_VEDRAM_ILIM 49B5
CONFIDENTIAL
VREG_VEDRAM_IOUT 55A5 V_AUD_FLYN_P 33B4
VREG_VEDRAM_ISENSE_N 49C1 55A7 V_AUD_FLYP_N 33C4
VREG_VEDRAM_ISENSE_P 49C1 55A7 V_AUD_FLYP_P 33C4
VREG_VEDRAM_PGND 49B5 V_AVIP 37D3 39A8 40A8
VREG_VEDRAM_PWRGD 49D1 25C2 V_CPU_CORE_HF_GNDA_PLL 6A4
VREG_VEDRAM_RAMP 49C5 V_CPU_CORE_HF_VDDA_PLL 6B4
VREG_VEDRAM_RSENSE 49C3 V_CPU_GNDA_RNG 6B4
VREG_VEDRAM_SS 49A7 V_CPU_PVDDA_ED 6B4
VREG_VEDRAM_SW 49B5 V_CPU_PVDDA_HS 6C4
VREG_VEDRAM_SW_S 49C4 V_CPU_PVDDA_MEM 6D4
VREG_VEDRAM_TRK 49C7 V_CPU_PVDDA_PEX 6C4
VREG_VMEM_BST 50C5 V_CPU_PVSSA_ED 6B4
VREG_VMEM_CF2 55A6 V_CPU_PVSSA_HS 6C4
VREG_VMEM_COMP 50A8 V_CPU_PVSSA_MEM 6C4
VREG_VMEM_COMP_C 50A7 V_CPU_PVSSA_PEX 6C4
VREG_VMEM_DH 50C5 V_CPU_VDDA_RNG 6B4
VREG_VMEM_DL 50B5 V_CPU_VDD_VTTA 6A4
VREG_VMEM_EN 25D2 50C8 V_ENET_CT 38C4
VREG_VMEM_FB 50A1 55A7 55D6 V_EXPPORT_DUAL1 39D2
VREG_VMEM_FB_MID 50A1 55C6 V_EXPPORT_DUAL2 39C2
VREG_VMEM_FB_MID_R 55C4 V_EXPPORT_DUAL3 39B2
VREG_VMEM_ILIM 50B5 V_FAN1 36C5
VREG_VMEM_IOUT 55A5 V_GAMEPORT1 39D6
VREG_VMEM_ISENSE_N 50C1 55A7 V_GAMEPORT2 39C6
VREG_VMEM_ISENSE_P 50C1 55A7 V_GPU_GNDA_PLL 6A4
VREG_VMEM_PGND 50B5 V_GPU_VDDA_PLL 6A4
VREG_VMEM_PWRGD 50D1 25D2 V_HDD 41D2
VREG_VMEM_RAMP 50C5 V_IR 35C6
VREG_VMEM_RSENSE 50C3 V_RST_OK 22D3
VREG_VMEM_SS 50A7 V_VREG_1P2 52C7
VREG_VMEM_SW 50B5 V_VREG_1P2_ADJUST 52C7
VREG_VMEM_SW_S 50C4 V_VREG_1P2_IN 52C8
VREG_VMEM_TRK 50C7 V_VREG_1P8PLL 52B7
VREG_VMEM_VEDRAM_SYNC 49C7 V_VREG_CPU 43B2 44D8 45D8
VREG_VMEM_VEDRAM_VCCO 49D1 50D8 V_VREG_GPUPCIE 52D3
VREG_VMEM_VEDRAM_VDL 49D7 V_VREG_STBY_VIN 53C7
VREG_V_CPUCORE_S 44A8 V_VREG_V3P3_V5P0 47D1 26B3 31C1 48D8
VSS_PLLA 31B4 V_VREG_VCS 51C5
VSS_PLLB 31B4 V_VREG_VMEM_VEDRAM 49D1 50D8
V_1P2STBY_R 53C4 WAVEPORT_DN 26C2 39B8
V_3P3STBY_LED_R 63A1 WAVEPORT_DP 26C2 39B8
V_3P3STBY_R 53A4 WSS_CNTL0 24B2 37C8 62D8
V_3P3_LED_R 63A1 WSS_CNTL1 24B2 37C8 62D5
V_3P3_VREF_CPUPLL_PCIE 58B7 WSS_CNTL_B 37C7
V_3P3_VREF_V5P0_V3P3 56B3 WSS_CNTL_E 37C7
V_3P3_VREF_VCS 57D5 WSS_CNTL_OUT 37C6
V_3P3_VREF_VMEM_VEDRAM 55B3 WSS_CNTL_OUT_R 37C7
V_5P0STBY_LED_R 63A2 XTAL_IN 22C6
V_5P0_LED_R 63A2 XTAL_OUT 22C6
V_12P0_DET 22C6
V_12P0_IN 38A2
V_12P0_LED_R 63A2
V_AUD 33D6
V_AUD_BIAS 33C4
V_AUD_FILT_N 33A4
V_AUD_FILT_P 33C4
V_AUD_FLYN_N 33B4
CONFIDENTIAL
Title: Cref Part Report C1T1 CAPN_402 [54] C2R3 CAPN_603 [30] C3E2 CAPN_402 [54]
Design: corona C1U1 CAPN_1206 [48] C2R4 CAPN_402 [28] C3E4 CAPN_402 [58]
Date: Feb 17 21:27:51 2011 C1U2 CAPN_402 [56] C2R5 CAPN_402 [28] C3E5 CAPN_402 [58]
C1U3 CAPN_402 [54] C2R6 CAPN_603 [30] C3F1 CAPN_1206 [49]
C2A5 CAPN_603 [38] C2R7 CAPN_402 [28] C3F2 CAPN_402 [49]
C1A1 CAPN_603 [39] C2A6 CAPN_402 [38] C2R8 CAPN_402 [28] C3F3 CAPN_402 [49]
C1A3 CAP_P_RDL [39] C2A8 CAPN_603 [37] C2R10 CAPN_402 [28] C3F5 CAPN_603 [49]
C1A4 CAPN_603 [41] C2A9 CAP_P_RDL [39] C2R11 CAPN_402 [26] C3F6 CAPN_402 [55]
C1A7 CAPN_402 [39] C2A12 CAPN_805 [38] C2R13 CAPN_402 [26] C3F8 CAP_P_TH [49]
C1A8 CAPN_402 [39] C2A14 CAPN_402 [38] C2T1 CAPN_402 [26] C3G1 CAPN_603 [49]
C1A9 CAPN_402 [39] C2A15 CAPN_402 [54] C2T2 CAPN_402 [26] C3G2 CAPN_402 [55]
C1A10 CAPN_402 [54] C2B1 CAP_P_RDL [39] C2T3 CAPN_402 [26] C3G3 CAPN_603 [49]
C1B1 CAPN_402 [41] C2B2 CAP_P_RDL [46] C2T18 CAPN_402 [34] C3G4 CAPN_402 [55]
C1B2 CAPN_402 [41] C2B3 CAP_P_RDL [38] C2U1 CAPN_402 [54] C3G5 CAPN_402 [55]
C1B3 CAPN_402 [41] C2B4 CAPN_603 [62] C2V1 CAPN_805 [47] C3G6 CAPN_402 [50]
C1B4 CAPN_402 [41] C2C1 CAPN_402 [62] C2V2 CAPN_402 [54] C3G7 CAPN_402 [50]
C1B5 CAPN_402 [41] C2C2 CAPN_402 [37] C2V4 CAPN_805 [47] C3G8 CAPN_402 [50]
C1B7 CAPN_402 [41] C2C3 CAPN_402 [62] C3A1 CAPN_402 [37] C3G9 CAPN_603 [50]
C1B12 CAPN_1206 [46] C2E1 CAPN_402 [32] C3A5 CAPN_402 [33] C3G14 CAPN_1206 [35]
C1D1 CAPN_603 [34] C2E2 CAPN_603 [47] C3A6 CAPN_603 [33] C3M1 CAPN_402 [37]
C1E1 CAPN_603 [47] C2E3 CAPN_402 [47] C3A7 CAPN_402 [33] C3M2 CAPN_805 [33]
C1E6 CAPN_402 [32] C2E8 CAP_P_TH [47] C3A12 CAPN_402 [37] C3N1 CAPN_402 [54]
C1E7 CAPN_603 [32] C2E9 CAPN_402 [32] C3A13 CAPN_402 [37] C3N2 CAPN_402 [60]
C1E8 CAPN_603 [32] C2F1 CAPN_603 [47] C3A14 CAP_P_RDL [38] C3N3 CAPN_603 [60]
C1E9 CAPN_402 [32] C2F2 CAPN_402 [56] C3B1 CAPN_402 [54] C3N40 CAPN_402 [54]
C1E14 CAPN_402 [32] C2F7 CAPN_402 [63] C3B11 CAPN_603 [33] C3P1 CAPN_603 [29]
C1E15 CAPN_402 [32] C2F10 CAPN_1206 [47] C3B12 CAPN_402 [33] C3P2 CAPN_402 [23]
C1E16 CAPN_603 [32] C2G1 CAPN_805 [47] C3C1 CAPN_402 [23] C3P3 CAPN_402 [54]
C1E17 CAPN_402 [34] C2G2 CAPN_805 [47] C3C2 CAPN_402 [23] C3P4 CAPN_603 [31]
C1F1 CAPN_603 [48] C2G3 CAPN_805 [47] C3C3 CAPN_402 [23] C3P5 CAPN_603 [31]
C1F2 CAPN_402 [56] C2G4 CAPN_402 [54] C3C4 CAPN_402 [23] C3P6 CAPN_603 [31]
C1F3 CAPN_603 [48] C2G5 CAP_P_TH [47] C3C5 CAPN_402 [5] C3P7 CAPN_402 [28]
C1F6 CAPN_603 [48] C2M1 CAPN_402 [37] C3C7 CAPN_402 [54] C3P8 CAPN_603 [31]
C1F9 CAPN_603 [48] C2M2 CAPN_402 [37] C3C8 CAPN_603 [29] C3P9 CAPN_603 [25]
C1F10 CAPN_402 [56] C2M3 CAPN_402 [38] C3D1 CAPN_402 [22] C3P10 CAPN_402 [28]
C1F11 CAPN_402 [56] C2M4 CAPN_402 [38] C3D3 CAPN_402 [24] C3P11 CAPN_402 [28]
C1G2 CAPN_603 [48] C2M5 CAPN_603 [38] C3D4 CAPN_402 [24] C3P12 CAPN_402 [28]
C1M1 CAPN_603 [39] C2M6 CAPN_603 [38] C3D5 CAPN_402 [24] C3P13 CAPN_402 [28]
C1N3 CAPN_402 [46] C2M7 CAPN_603 [39] C3D6 CAPN_402 [24] C3P14 CAPN_402 [28]
C1N4 CAPN_402 [46] C2P1 CAPN_603 [29] C3D7 CAPN_402 [22] C3P15 CAPN_402 [28]
C1P1 CAPN_402 [54] C2P2 CAPN_603 [29] C3D8 CAPN_402 [22] C3P16 CAPN_402 [28]
C1R1 CAPN_402 [63] C2P3 CAPN_402 [28] C3D9 CAPN_402 [61] C3P17 CAPN_402 [28]
C1R2 CAPN_603 [63] C2R1 CAPN_402 [28] C3D10 CAPN_402 [61] C3P18 CAPN_402 [28]
C1R3 CAPN_402 [63] C2R2 CAPN_402 [28] C3D11 CAPN_402 [61] C3P19 CAPN_402 [28]
CONFIDENTIAL
C3P20 CAPN_402 [28] C3R41 CAPN_402 [28] C4C4 CAPN_402 [63] C5B2 CAPN_805 [53]
C3P24 CAPN_402 [28] C3R45 CAPN_402 [28] C4D1 CAPN_402 [61] C5B8 CAPN_402 [57]
C3P27 CAPN_402 [28] C3R48 CAPN_603 [31] C4E1 CAPN_402 [4] C5B19 CAPN_603 [51]
C3P28 CAPN_402 [28] C3R49 CAPN_402 [31] C4E2 CAPN_402 [4] C5B20 CAPN_603 [51]
C3P29 CAPN_402 [28] C3R50 CAPN_402 [28] C4E3 CAP_P_RDL [49] C5B21 CAP_P_TH [51]
C3P30 CAPN_402 [28] C3R51 CAPN_603 [30] C4E4 CAPN_402 [54] C5C1 CAPN_805 [45]
C3P31 CAPN_402 [28] C3R52 CAPN_603 [30] C4E6 CAP_P_RDL [49] C5C2 CAP_P_RDL [51]
C3P32 CAPN_402 [27] C3R53 CAPN_603 [29] C4E9 CAPN_603 [52] C5C3 CAP_P_RDL [43]
C3P33 CAPN_402 [27] C3R54 CAPN_603 [29] C4E10 CAPN_603 [52] C5C6 CAPN_603 [51]
C3P34 CAPN_402 [27] C3R55 CAPN_402 [22] C4E11 CAPN_603 [52] C5D1 CAPN_603 [9]
C3P35 CAPN_402 [27] C3R56 CAPN_402 [61] C4E12 CAPN_603 [52] C5D2 CAPN_603 [9]
C3P36 CAPN_603 [29] C3T1 CAPN_603 [29] C4E13 CAPN_402 [52] C5D3 CAPN_603 [9]
C3R1 CAPN_402 [23] C3T2 CAPN_603 [29] C4F7 CAP_P_RDL [49] C5D4 CAPN_603 [9]
C3R2 CAPN_402 [28] C3T6 CAPN_402 [54] C4F8 CAPN_402 [52] C5D5 CAPN_603 [9]
C3R3 CAPN_402 [28] C3T7 CAPN_402 [58] C4G1 CAPN_402 [54] C5D6 CAPN_603 [9]
C3R4 CAPN_603 [31] C3T8 CAPN_402 [58] C4M1 CAPN_402 [54] C5D7 CAPN_603 [9]
C3R7 CAPN_402 [28] C3U4 CAPN_402 [54] C4N1 CAPN_402 [57] C5D10 CAPN_603 [9]
C3R8 CAPN_402 [28] C3V1 CAPN_603 [49] C4N2 CAPN_402 [54] C5D11 CAPN_603 [9]
C3R12 CAPN_402 [28] C3V5 CAPN_402 [35] C4N8 CAPN_402 [54] C5E1 CAPN_402 [4]
C3R13 CAPN_402 [28] C3V6 CAPN_402 [35] C4N9 CAPN_603 [51] C5E2 CAPN_402 [4]
C3R14 CAPN_402 [28] C4A1 CAPN_402 [39] C4N10 CAPN_805 [51] C5E3 CAPN_402 [4]
C3R15 CAPN_402 [28] C4A3 CAPN_402 [37] C4P4 CAPN_603 [52] C5E4 CAPN_402 [4]
C3R19 CAPN_402 [28] C4A7 CAPN_402 [37] C4R1 CAPN_402 [61] C5E8 CAPN_603 [9]
C3R23 CAPN_402 [28] C4A11 CAPN_402 [41] C4R5 CAPN_402 [61] C5F1 CAPN_402 [19]
C3R24 CAPN_402 [28] C4A12 CAPN_402 [62] C4T3 CAPN_603 [9] C5F2 CAPN_402 [20]
C3R25 CAPN_402 [28] C4A14 CAPN_603 [41] C4T4 CAPN_603 [9] C5F3 CAPN_402 [20]
C3R26 CAPN_402 [28] C4B3 CAPN_805 [52] C4T7 CAPN_1206 [49] C5F4 CAPN_402 [20]
C3R27 CAPN_402 [28] C4B4 CAPN_603 [51] C4U4 CAP_P_SM [50] C5F5 CAPN_402 [20]
C3R28 CAPN_402 [28] C4B5 CAPN_603 [51] C5A1 CAPN_402 [53] C5F6 CAPN_402 [20]
C3R33 CAPN_603 [31] C4B10 CAPN_402 [54] C5A6 CAPN_805 [41] C5G1 CAP_P_RDL [38]
C3R34 CAPN_402 [28] C4B11 CAPN_805 [51] C5A7 CAPN_402 [41] C5G2 CAPN_402 [38]
C3R38 CAPN_402 [28] C4C1 CAPN_402 [54] C5A14 CAPN_402 [41] C5G8 CAPN_402 [54]
C3R39 CAPN_402 [28] C4C2 CAPN_603 [29] C5A15 CAPN_603 [36] C5M5 CAPN_603 [53]
C3R40 CAPN_402 [28] C4C3 CAPN_402 [63] C5B1 CAPN_402 [53] C5M6 CAPN_402 [59]
CONFIDENTIAL
C5M7 CAPN_603 [59] C5R43 CAPN_402 [9] C5T34 CAPN_603 [9] C6F7 CAPN_402 [18]
C5N1 CAPN_402 [57] C5R47 CAPN_402 [11] C5T38 CAPN_402 [13] C6F11 CAPN_603 [20]
C5N2 CAPN_402 [57] C5R48 CAPN_402 [11] C5T39 CAPN_402 [13] C6G1 CAP_P_RDL [39]
C5N3 CAPN_402 [54] C5R49 CAPN_402 [10] C5T41 CAPN_402 [13] C6G2 CAPN_402 [39]
C5N7 CAPN_402 [57] C5R53 CAPN_402 [11] C5T45 CAPN_402 [13] C6N1 CAPN_805 [45]
C5R1 CAPN_603 [9] C5R58 CAPN_402 [9] C5T50 CAPN_402 [13] C6N6 CAPN_402 [59]
C5R2 CAPN_603 [9] C5R59 CAPN_402 [10] C5T52 CAPN_1206 [49] C6R1 CAPN_603 [9]
C5R3 CAPN_603 [9] C5R60 CAPN_402 [10] C5U1 CAPN_402 [18] C6R2 CAPN_603 [9]
C5R10 CAPN_603 [9] C5T1 CAPN_402 [9] C5U8 CAPN_402 [21] C6R9 CAPN_402 [11]
C5R15 CAPN_603 [9] C5T6 CAPN_402 [6] C6A1 CAPN_402 [38] C6R14 CAPN_402 [11]
C5R18 CAPN_603 [9] C5T9 CAPN_805 [6] C6A4 CAP_P_RDL [38] C6R17 CAPN_402 [10]
C5R23 CAPN_402 [11] C5T14 CAPN_402 [11] C6B1 CAP_P_TH [43] C6R22 CAPN_402 [11]
C5R24 CAPN_402 [11] C5T15 CAPN_402 [11] C6B2 CAPN_1206 [45] C6R23 CAPN_402 [12]
C5R28 CAPN_402 [10] C5T19 CAPN_402 [11] C6C1 CAP_P_RDL [43] C6R27 CAPN_402 [12]
C5R31 CAPN_805 [6] C5T22 CAPN_402 [9] C6D1 CAPN_603 [9] C6R30 CAPN_402 [11]
C5R37 CAPN_402 [10] C5T28 CAPN_402 [11] C6F1 CAPN_402 [18] C6R36 CAPN_402 [10]
CONFIDENTIAL
C6R42 CAPN_402 [10] C7C1 CAPN_402 [44] C7T4 CAPN_402 [15] DB3D1 DBPAD_TP [22]
C6R45 CAPN_402 [10] C7C4 CAPN_402 [44] C7T7 CAPN_402 [14] DB3E1 DBPAD_TP [52]
C6R46 CAPN_402 [12] C7C5 CAPN_402 [44] C7T8 CAPN_402 [15] DB3E2 DBPAD_LARGE-TP [63]
C6T2 CAPN_402 [11] C7C6 CAPN_402 [44] C7T9 CAPN_402 [15] DB3M1 DBPAD_TP [40]
C6T3 CAPN_402 [11] C7C7 CAPN_402 [44] C7T10 CAPN_402 [21] DB3N1 DBPAD_TP [52]
C6T4 CAPN_402 [11] C7C8 CAPN_805 [45] C7T11 CAPN_402 [15] DB3P1 DBPAD_LARGE-TP [23]
C6T5 CAPN_402 [11] C7C9 CAPN_402 [44] C7T12 CAPN_402 [15] DB3P2 DBPAD_LARGE-TP [23]
C6T6 CAPN_402 [10] C7C10 CAPN_1206 [44] C7U1 CAPN_1206 [50] DB3P3 DBPAD_TP [24]
C6T7 CAPN_402 [10] C7C11 CAPN_603 [44] C7V1 CAPN_603 [39] DB3R1 DBPAD_LARGE-TP [23]
C6T8 CAPN_402 [10] C7C12 CAP_P_RDL [43] D2G1 LED_SM [63] DB3R2 DBPAD_LARGE-TP [23]
C6T9 CAPN_402 [11] C7C13 CAP_P_RDL [43] D2G2 LED_SM [63] DB3R3 DBPAD_TP [25]
C6T10 CAPN_402 [12] C7D7 CAPN_402 [16] D4A1 DIODE_SOT23 [36] DB3R4 DBPAD_TP [25]
C6T11 CAPN_402 [10] C7D8 CAPN_402 [16] D4B1 LED_SM [63] DB3R5 DBPAD_TP [25]
C6T12 CAPN_402 [10] C7D9 CAPN_402 [16] D4P1 LED_SM [63] DB3R6 DBPAD_TP [22]
C6T13 CAPN_402 [11] C7D10 CAPN_402 [16] D5A1 LED_SM [63] DB3R7 DBPAD_TP [22]
C6T14 CAPN_402 [10] C7D11 CAPN_603 [16] D5B1 DIODE_SOT23 [45] DB4B1 DBPAD_TP [51]
C6T15 CAPN_402 [11] C7D12 CAPN_402 [17] D6A1 LED_SM [63] DB4B2 DBPAD_LARGE-TP [63]
C6T16 CAPN_402 [11] C7D13 CAPN_402 [16] D6B1 DIODE_SOT23 [45] DB4C1 DBPAD_TP [51]
C6T17 CAPN_402 [11] C7D14 CAPN_402 [16] D7A1 LED_SM [63] DB4C2 DBPAD_TP [52]
C6T18 CAPN_402 [11] C7D15 CAPN_402 [21] DB1B1 DBPAD_LARGE-TP [63] DB4C3 DBPAD_LARGE-TP [63]
C6T19 CAPN_402 [11] C7E1 CAPN_402 [21] DB1C1 DBPAD_LARGE-TP [63] DB4D1 DBPAD_LARGE-TP [63]
C6T20 CAPN_402 [10] C7E2 CAPN_402 [16] DB1D1 DBPAD_LARGE-TP [63] DB4E1 DBPAD_TP [52]
C6T22 CAPN_603 [9] C7E3 CAPN_402 [16] DB1D2 DBPAD_LARGE-TP [63] DB4E2 DBPAD_TP [52]
C6T23 CAPN_603 [9] C7E4 CAPN_402 [14] DB1E1 DBPAD_TP [42] DB4E3 DBPAD_TP [49]
C6T24 CAPN_402 [11] C7E5 CAPN_402 [14] DB1E2 DBPAD_TP [25] DB4E4 DBPAD_TP [49]
C6T25 CAPN_402 [11] C7E6 CAPN_402 [14] DB1R1 DBPAD_TP [32] DB4E5 DBPAD_TP [49]
C6T26 CAPN_402 [13] C7E7 CAPN_402 [14] DB2B1 DBPAD_LARGE-TP [63] DB4N2 DBPAD_TP [51]
C6T27 CAPN_402 [12] C7E8 CAPN_603 [14] DB2B2 DBPAD_LARGE-TP [63] DB4N3 DBPAD_TP [51]
C6T28 CAPN_402 [13] C7E9 CAPN_402 [15] DB2B3 DBPAD_LARGE-TP [63] DB4P1 DBPAD_TP [52]
C6T29 CAPN_402 [12] C7E10 CAPN_402 [14] DB2C1 DBPAD_TP [25] DB4P6 DBPAD_TP [51]
C6T30 CAPN_603 [12] C7E11 CAPN_402 [14] DB2C2 DBPAD_TP [22] DB4P7 DBPAD_TP [51]
C6T31 CAPN_402 [13] C7E12 CAPN_402 [21] DB2C3 DBPAD_LARGE-TP [63] DB4P8 DBPAD_TP [51]
C6T32 CAPN_402 [12] C7E13 CAPN_402 [14] DB2C4 DBPAD_LARGE-TP [63] DB4R1 DBPAD_TP [5]
C6T33 CAPN_402 [13] C7E14 CAPN_402 [14] DB2C5 DBPAD_LARGE-TP [63] DB4R2 DBPAD_TP [2]
C6U1 CAPN_402 [19] C7F1 CAPN_603 [50] DB2D1 DBPAD_TP [25] DB4R3 DBPAD_TP [2]
C6U2 CAPN_402 [19] C7F2 CAP_P_RDL [50] DB2E1 DBPAD_TP [52] DB5A1 DBPAD_TP [53]
C6U3 CAPN_402 [19] C7F3 CAPN_1206 [50] DB2E2 DBPAD_TP [25] DB5A2 DBPAD_TP [53]
C6U4 CAPN_402 [19] C7G1 CAP_P_RDL [39] DB2E3 DBPAD_TP [25] DB5B1 DBPAD_TP [53]
C6U5 CAPN_402 [19] C7G2 CAPN_402 [39] DB2E4 DBPAD_LARGE-TP [63] DB5B2 DBPAD_TP [51]
C6U6 CAPN_402 [19] C7M1 CAPN_402 [54] DB2F1 DBPAD_TP [48] DB5B3 DBPAD_TP [51]
C6U7 CAPN_402 [20] C7N1 CAPN_1206 [45] DB2G1 DBPAD_TP [48] DB5B4 DBPAD_TP [25]
C6U8 CAPN_402 [19] C7P1 CAPN_402 [44] DB2G2 DBPAD_TP [47] DB5C1 DBPAD_TP [51]
C6U9 CAPN_402 [19] C7P2 CAPN_603 [44] DB2G3 DBPAD_TP [25] DB5M1 DBPAD_TP [53]
C6U10 CAPN_402 [21] C7R1 CAP_P_SM [50] DB2G4 DBPAD_TP [47] DB5M2 DBPAD_TP [53]
C7A1 CAPN_603 [38] C7R2 CAPN_402 [17] DB2G5 DBPAD_LARGE-TP [63] DB5M3 DBPAD_TP [53]
C7A2 CAPN_603 [38] C7R3 CAPN_402 [17] DB2P1 DBPAD_TP [25] DB5N1 DBPAD_TP [53]
C7A3 CAPN_603 [38] C7R4 CAPN_402 [17] DB3A1 DBPAD_TP [37] DB5R5 DBPAD_TP [6]
C7A4 CAPN_603 [38] C7R5 CAPN_402 [17] DB3A2 DBPAD_TP [33] DB6M1 DBPAD_TP [38]
C7B1 CAPN_1206 [43] C7R6 CAPN_402 [16] DB3A3 DBPAD_TP [33] DB6M2 DBPAD_TP [38]
C7B2 CAP_P_TH [38] C7R7 CAPN_402 [17] DB3A4 DBPAD_TP [33] DB6M3 DBPAD_TP [38]
C7B3 CAP_P_TH [43] C7R8 CAPN_402 [17] DB3B1 DBPAD_TP [33] DB6N1 DBPAD_TP [38]
C7B4 CAPN_402 [54] C7R9 CAPN_402 [21] DB3C1 DBPAD_TP [25] DB6R1 DBPAD_TP [43]
C7B5 CAPN_1206 [45] C7T1 CAPN_402 [17] DB3C2 DBPAD_TP [53] DB6R2 DBPAD_TP [43]
C7B7 CAPN_402 [44] C7T2 CAPN_402 [17] DB3C3 DBPAD_TP [25] DB7C1 DBPAD_TP [44]
C7B8 CAP_P_TH [49] C7T3 CAPN_402 [15] DB3C4 DBPAD_LARGE-TP [63] DB7C2 DBPAD_TP [44]
CONFIDENTIAL
DB7C3 DBPAD_TP [44] FB3R1 FERRITE_603 [30] FT3M11 FTPAD_TP [40] FT5P2 FTPAD_TP [3]
DB7C4 DBPAD_TP [45] FB5R1 FERRITE_603 [6] FT3M12 FTPAD_TP [64] FT5R1 FTPAD_TP [3]
DB7C5 DBPAD_TP [44] FB5R2 FERRITE_603 [6] FT3N1 FTPAD_TP [64] FT5R2 FTPAD_TP [3]
DB7C6 DBPAD_TP [44] FB5R3 FERRITE_603 [6] FT3N2 FTPAD_TP [64] FT5R3 FTPAD_TP [3]
DB7F1 DBPAD_TP [50] FB5R4 FERRITE_603 [6] FT3N3 FTPAD_TP [33] FT5R4 FTPAD_TP [3]
DB7F2 DBPAD_TP [50] FB5R5 FERRITE_603 [6] FT3N4 FTPAD_TP [64] FT5R5 FTPAD_TP [3]
DB7P1 DBPAD_TP [44] FB5T1 FERRITE_603 [6] FT3P1 FTPAD_TP [23] FT5R6 FTPAD_TP [3]
DB7P2 DBPAD_TP [44] FB5T2 FERRITE_603 [6] FT3P2 FTPAD_TP [25] FT5R7 FTPAD_TP [3]
EG1A1 ESDGUARD_402 [39] FB5T3 FERRITE_603 [6] FT3P3 FTPAD_TP [52] FT5R8 FTPAD_TP [3]
EG1A2 ESDGUARD_402 [39] FT1M5 FTPAD_TP [41] FT3P5 FTPAD_TP [22] FT5R9 FTPAD_TP [3]
EG1A3 ESDGUARD_402 [39] FT1N8 FTPAD_TP [41] FT3P8 FTPAD_TP [44] FT5R10 FTPAD_TP [3]
EG1A4 ESDGUARD_402 [39] FT1N9 FTPAD_TP [46] FT3P9 FTPAD_TP [52] FT5R11 FTPAD_TP [3]
EG1A5 ESDGUARD_402 [39] FT1P2 FTPAD_TP [64] FT3R2 FTPAD_TP [22] FT5R12 FTPAD_TP [3]
EG1A6 ESDGUARD_402 [39] FT1P3 FTPAD_TP [64] FT3R3 FTPAD_TP [22] FT5R13 FTPAD_TP [3]
EG1A7 ESDGUARD_402 [39] FT1R1 FTPAD_TP [34] FT3R4 FTPAD_TP [48] FT5R14 FTPAD_TP [3]
EG1A8 ESDGUARD_402 [39] FT1R2 FTPAD_TP [64] FT3R7 FTPAD_TP [22] FT5R15 FTPAD_TP [3]
EG1B1 ESDGUARD_402 [41] FT1R3 FTPAD_TP [32] FT3R8 FTPAD_TP [52] FT5R16 FTPAD_TP [3]
EG1B2 ESDGUARD_402 [41] FT1R4 FTPAD_TP [32] FT3R17 FTPAD_TP [4] FT5R17 FTPAD_TP [51]
EG1B3 ESDGUARD_402 [41] FT1T11 FTPAD_TP [64] FT3R18 FTPAD_TP [61] FT5T1 FTPAD_TP [52]
EG1B4 ESDGUARD_402 [41] FT1U1 FTPAD_TP [35] FT3T2 FTPAD_TP [4] FT5T2 FTPAD_TP [63]
EG2A2 ESDGUARD_402 [38] FT1U2 FTPAD_TP [35] FT3T4 FTPAD_TP [24] FT6M1 FTPAD_TP [38]
EG2A3 ESDGUARD_402 [38] FT2M1 FTPAD_TP [38] FT3T5 FTPAD_TP [24] FT6N1 FTPAD_TP [64]
EG2A4 ESDGUARD_402 [38] FT2M2 FTPAD_TP [38] FT3T6 FTPAD_TP [24] FT6R2 FTPAD_TP [43]
EG2A5 ESDGUARD_402 [38] FT2N1 FTPAD_TP [64] FT3T7 FTPAD_TP [24] FT6V1 FTPAD_TP [64]
EG2A6 ESDGUARD_402 [38] FT2N2 FTPAD_TP [64] FT3T8 FTPAD_TP [24] FT7M1 FTPAD_TP [64]
EG2A7 ESDGUARD_402 [38] FT2N3 FTPAD_TP [46] FT3T9 FTPAD_TP [64] FT7N1 FTPAD_TP [38]
EG3A1 ESDGUARD_402 [40] FT2P1 FTPAD_TP [25] FT3T10 FTPAD_TP [2] FT7N2 FTPAD_TP [64]
EG3A2 ESDGUARD_402 [40] FT2P2 FTPAD_TP [25] FT3T11 FTPAD_TP [2] FT7P3 FTPAD_TP [2]
EG3A3 ESDGUARD_402 [40] FT2P3 FTPAD_TP [25] FT4M1 FTPAD_TP [40] FT7P4 FTPAD_TP [2]
EG3A6 ESDGUARD_402 [37] FT2R1 FTPAD_TP [46] FT4M4 FTPAD_TP [40] FT7P7 FTPAD_TP [2]
EG4A1 ESDGUARD_402 [39] FT2R2 FTPAD_TP [47] FT4M5 FTPAD_TP [40] FT7P8 FTPAD_TP [2]
EG4A2 ESDGUARD_402 [40] FT2T1 FTPAD_TP [50] FT4M6 FTPAD_TP [40] FT7U1 FTPAD_TP [50]
EG4A3 ESDGUARD_402 [40] FT2T2 FTPAD_TP [34] FT4M7 FTPAD_TP [40] J1A1 WAVERECEPTACLE_TH [39]
EG4A4 ESDGUARD_402 [40] FT2T3 FTPAD_TP [34] FT4M8 FTPAD_TP [40] J1A2 USBTRIPLE_TH [39]
EG4A5 ESDGUARD_402 [37] FT2T4 FTPAD_TP [34] FT4M9 FTPAD_TP [40] J1B1 1X7SATA_TH [41]
EG4A6 ESDGUARD_402 [37] FT2T5 FTPAD_TP [34] FT4P4 FTPAD_TP [5] J1B2 1X7SATA_TH [41]
EG4A7 ESDGUARD_402 [37] FT2T6 FTPAD_TP [64] FT4P5 FTPAD_TP [5] J1B3 1X4HDR_TH [41]
EG4A8 ESDGUARD_402 [37] FT2T7 FTPAD_TP [64] FT4P6 FTPAD_TP [5] J1D1 1X5HDR_TH [26]
EG4A9 ESDGUARD_402 [37] FT2T8 FTPAD_TP [34] FT4P7 FTPAD_TP [5] J1F1 1X2HDR_TH [35]
EG4A10 ESDGUARD_402 [37] FT2T9 FTPAD_TP [49] FT4P8 FTPAD_TP [5] J2A1 TRINITYRJ45AUX_TH [38]
EG4M1 ESDGUARD_402 [40] FT2T10 FTPAD_TP [34] FT4P9 FTPAD_TP [52] J2C1 2X5HDR10_TH [62]
EG4M2 ESDGUARD_402 [40] FT2T11 FTPAD_TP [34] FT4P10 FTPAD_TP [5] J2C2 2X13SOFTTOUCH_SM [62]
EG4M5 ESDGUARD_402 [40] FT2T12 FTPAD_TP [34] FT4P11 FTPAD_TP [63] J2C3 2X7HDR14_TH [62]
EG6G1 ESDGUARD_402 [39] FT2U1 FTPAD_TP [48] FT4R1 FTPAD_TP [64] J2F1 1X3HDR_TH [63]
EG6G2 ESDGUARD_402 [39] FT2V2 FTPAD_TP [47] FT4R4 FTPAD_TP [3] J3A1 HDMI_1X19HDR [40]
EG7G1 ESDGUARD_402 [39] FT2V4 FTPAD_TP [64] FT4R6 FTPAD_TP [3] J3E1 PCIEXMIDBUS_SM [62]
EG7G2 ESDGUARD_402 [39] FT3M1 FTPAD_TP [40] FT4R7 FTPAD_TP [3] J3E2 2X3HDR_TH [63]
FB1A1 FERRITE_603 [39] FT3M2 FTPAD_TP [40] FT4R8 FTPAD_TP [3] J4A1 TOSLINK_TX_TH [39]
FB2M1 FERRITE_603 [38] FT3M3 FTPAD_TP [40] FT4R9 FTPAD_TP [3] J4A2 XENONAVIP_TH [37]
FB2R1 FERRITE_603 [30] FT3M4 FTPAD_TP [40] FT4R11 FTPAD_TP [5] J4A3 2X6HDR2_TH [41]
FB3A1 FERRITE_603 [33] FT3M5 FTPAD_TP [40] FT4T2 FTPAD_TP [49] J4C1 2X4HDR_TH [63]
FB3A2 FERRITE_603 [33] FT3M7 FTPAD_TP [40] FT4T3 FTPAD_TP [52] J4C2 2X5HDR_TH [63]
FB3P1 FERRITE_603 [31] FT3M8 FTPAD_TP [40] FT4V1 FTPAD_TP [64] J4C3 2X3HDR_TH [63]
FB3P2 FERRITE_603 [31] FT3M9 FTPAD_TP [40] FT5M3 FTPAD_TP [53] J4D2 1X3HDR_SM [62]
FB3P3 FERRITE_603 [31] FT3M10 FTPAD_TP [40] FT5P1 FTPAD_TP [3] J5B1 2X2HDR_TH [55]
CONFIDENTIAL
J5G2 XENONRF_BORON_TH [38] S3 R1R8 RESN_402 [32] R2F8 RESN_402 [56]
J6A5 1X4HDR_TH [36] Q5C1 FET_VREG_DPAK_G1D2 [45] R1R9 RESN_402 [32] R2F9 RESN_805 [48]
J6G1 USBDUALHORIZONTAL_ [39] S3 R1R10 RESN_402 [32] R2G1 RESN_2512 [47]
TH Q5C2 FET_VREG_DPAK_G1D2 [51] R1T1 RESN_402 [42] R2G2 RESN_1206 [47]
J7A1 TRINITYPWR_TH [38] S3 R1T2 RESN_402 [47] R2G3 RESN_402 [25]
L1F1 INDUCTOR_SM [48] Q5C3 FET_VREG_DPAK_G1D2 [45] R1T3 RESN_1206 [42] R2G4 RESN_402 [25]
L2B1 INDUCTOR_TH [47] S3 R1T4 RESN_805 [47] R2G5 RESN_402 [24]
L2F1 INDUCTOR_TH [47] Q6A3 PNP_2C_SOT223 [42] R1T6 RESN_1206 [42] R2G6 RESN_402 [24]
L4A1 INDUCTOR_1210 [37] Q6B1 FET_VREG_DPAK_G1D2 [45] R1T7 RESN_402 [42] R2G7 RESN_402 [24]
L4A2 INDUCTOR_1210 [37] S3 R1T19 RESN_402 [56] R2G8 RESN_402 [63]
L4A3 INDUCTOR_1210 [37] Q6B2 FET_VREG_DPAK_G1D2 [45] R1U3 RESN_402 [56] R2M1 RESN_402 [25]
L4A4 INDUCTOR_1210 [37] S3 R1U4 RESN_402 [56] R2M2 RESN_402 [37]
L4B1 INDUCTOR_TH [51] Q6C1 FET_VREG_DPAK_G1D2 [45] R1U5 RESN_402 [56] R2N1 RESN_402 [37]
L4F1 INDUCTOR_TH [49] S3 R2A2 RESN_402 [38] R2P1 RESN_402 [25]
L5A1 INDUCTOR_1210 [53] Q6C2 FET_VREG_DPAK_G1D2 [45] R2A3 RESN_402 [38] R2P2 RESN_402 [25]
L5B1 INDUCTOR_1210 [53] S3 R2A4 RESN_402 [38] R2P3 RESN_402 [22]
L5B2 INDUCTOR_SM [53] Q6M2 FET_SOT23 [42] R2A5 RESN_402 [38] R2P4 RESN_402 [23]
L5C1 INDUCTOR_TH [51] Q6M3 NPN_SOT23 [42] R2C1 RESN_402 [24] R2P5 RESN_402 [24]
L6B1 INDUCTOR_TH [43] Q7G1 FET_VREG_DPAK_G1D2 [50] R2C2 RESN_402 [62] R2P6 RESN_402 [31]
L6C1 IND_2MODE_SM [45] S3 R2C3 RESN_402 [37] R2P7 RESN_402 [31]
L6C2 IND_2MODE_TH [45] Q7G2 FET_VREG_DPAK_G1D2 [50] R2C4 RESN_402 [62] R2P8 RESN_402 [31]
L7B1 INDUCTOR_TH [49] S3 R2C5 RESN_402 [25] R2P9 RESN_402 [24]
L7F1 INDUCTOR_TH [50] R1A1 RESN_402 [39] R2C6 RESN_402 [62] R2R1 RESN_402 [34]
LB2B1 LABEL_SM [65] R1D1 RESN_402 [34] R2C7 RESN_402 [62] R2R2 RESN_402 [32]
MTG1B1 STD_MTG_HOLE_TH [65] R1D2 RESN_402 [34] R2C8 RESN_402 [26] R2R3 RESN_402 [30]
MTG1G1 STD_MTG_HOLE_TH [65] R1E1 RESN_402 [32] R2C9 RESN_402 [24] R2R4 RESN_402 [30]
MTG4D1 STD_MTG_HOLE_TH [65] R1E2 RESN_402 [32] R2C10 RESN_402 [62] R2T1 RESN_402 [34]
MTG4F1 STD_MTG_HOLE_TH [65] R1E3 RESN_402 [32] R2C11 RESN_402 [24] R2T2 RESN_402 [34]
MTG4G1 STD_MTG_HOLE_TH [65] R1E4 RESN_402 [32] R2C12 RESN_402 [24] R2T3 RESN_402 [47]
MTG6D1 STD_MTG_HOLE_TH [65] R1E12 RESN_402 [47] R2C13 RESN_402 [24] R2T4 RESN_402 [47]
MTG6F1 STD_MTG_HOLE_TH [65] R1E14 RESN_402 [48] R2C14 RESN_402 [24] R2T5 RESN_402 [56]
MTG7G1 STD_MTG_HOLE_TH [65] R1E15 RESN_402 [48] R2C15 RESN_402 [24] R2T6 RESN_402 [34]
Q1F1 SHUNT_3PIN_SOT23 [56] R1E16 RESN_402 [48] R2C16 RESN_402 [24] R2T7 RESN_402 [34]
Q1N1 MBT3904DUAL_SOT [46] R1E17 RESN_402 [47] R2C17 RESN_402 [24] R2T8 RESN_402 [34]
Q1T1 NPN_SOT23 [42] R1E19 RESN_402 [48] R2C18 RESN_402 [24] R2T9 RESN_402 [34]
Q1T2 NPN_SOT23 [42] R1E20 RESN_402 [48] R2C19 RESN_402 [24] R2T10 RESN_402 [34]
Q2F1 FET_VREG_DPAK_G1D2 [47] R1E21 RESN_402 [48] R2C20 RESN_402 [24] R2T11 RESN_402 [34]
S3 R1E22 RESN_402 [48] R2C21 RESN_402 [24] R2T12 RESN_402 [34]
Q2F2 FET_VREG_DPAK_G1D2 [47] R1F1 RESN_402 [48] R2C22 RESN_402 [24] R2T13 RESN_402 [34]
S3 R1F2 RESN_402 [48] R2C23 RESN_402 [24] R2T14 RESN_402 [34]
Q2F3 SHUNT_3PIN_SOT23 [56] R1F3 RESN_402 [47] R2C24 RESN_402 [24] R2U1 RESN_402 [56]
Q2P1 FET_SOT23 [31] R1F4 RESN_402 [56] R2C25 RESN_402 [24] R2V1 RESN_402 [63]
Q2R1 FET_SOT23 [30] R1F5 RESN_402 [56] R2C26 RESN_402 [24] R2V2 RESN_402 [35]
Q3A1 MBT3904DUAL_SOT [37] R1F6 RESN_402 [56] R2C27 RESN_402 [25] R2V3 RESN_402 [35]
Q3F1 FET_VREG_DPAK_G1D2 [49] R1F9 RESN_2512 [48] R2E2 RESN_402 [47] R3A1 RESN_402 [37]
S3 R1N1 RESN_402 [46] R2E3 RESN_402 [47] R3A2 RESN_402 [37]
Q3M1 PNP_SOT23 [37] R1N2 RESN_402 [46] R2E4 RESN_402 [47] R3A3 RESN_402 [37]
Q3R1 FET_ZGATE_P_SOT23 [61] R1N3 RESN_402 [46] R2E5 RESN_402 [47] R3A4 RESN_402 [37]
Q4A1 NPN_SOT23 [36] R1P1 RESN_402 [46] R2E6 RESN_402 [47] R3A5 RESN_402 [37]
Q4B1 ADR510_SOT23 [57] R1P2 RESN_402 [46] R2E7 RESN_402 [47] R3A6 RESN_603 [37]
Q4C1 NPN_SOT23 [63] R1R1 RESN_402 [32] R2F1 RESN_402 [47] R3A8 RESN_402 [33]
Q4C2 NPN_SOT23 [63] R1R2 RESN_402 [32] R2F2 RESN_402 [56] R3A9 RESN_402 [33]
Q4F1 FET_VREG_DPAK_G1D2 [49] R1R3 RESN_402 [32] R2F3 RESN_402 [56] R3A10 RESN_402 [33]
S3 R1R4 RESN_402 [32] R2F4 RESN_402 [56] R3A11 RESN_402 [33]
Q4G1 PNP_SOT23 [23] R1R5 RESN_402 [32] R2F5 RESN_402 [56] R3B1 RESN_402 [55]
Q5A2 PNP_DPAK369C [36] R1R6 RESN_402 [32] R2F6 RESN_402 [63] R3B2 RESN_402 [55]
Q5B1 FET_VREG_DPAK_G1D2 [51] R1R7 RESN_402 [32] R2F7 RESN_805 [47] R3B3 RESN_402 [52]
CONFIDENTIAL
R3B4 RESN_402 [52] R3F14 RESN_402 [49] R3R7 RESN_402 [25] R4D6 RESN_402 [61]
R3C1 RESN_402 [55] R3G1 RESN_402 [55] R3R10 RESN_402 [25] R4E1 RESN_402 [4]
R3C21 RESN_603 [23] R3G10 RESN_402 [50] R3T5 RESN_402 [52] R4E11 RESN_805 [52]
R3C22 RESN_603 [23] R3G11 RESN_402 [50] R3U1 RESN_402 [55] R4E12 RESN_805 [52]
R3C23 RESN_603 [23] R3G12 RESN_402 [50] R3U3 RESN_402 [55] R4F1 RESN_2512 [49]
R3C24 RESN_402 [37] R3G13 RESN_402 [50] R3V1 RESN_402 [49] R4F2 RESN_402 [52]
R3C25 RESN_402 [37] R3G14 RESN_402 [50] R3V2 RESN_402 [38] R4G1 RESN_402 [23]
R3C26 RESN_402 [5] R3G15 RESN_402 [50] R3V4 RESN_402 [50] R4G2 RESN_402 [23]
R3D3 RESN_402 [22] R3G16 RESN_402 [49] R3V6 RESN_402 [38] R4G3 RESN_402 [50]
R3D4 RESN_402 [22] R3G17 RESN_805 [50] R4A1 RESN_402 [36] R4G4 RESN_402 [38]
R3D8 RESN_402 [22] R3M2 RESN_402 [37] R4A5 RESN_402 [37] R4M1 RESN_402 [40]
R3D11 RESN_402 [22] R3N1 RESN_402 [60] R4A8 RESN_402 [63] R4M6 RESN_402 [40]
R3D12 RESN_402 [22] R3N2 RESN_402 [60] R4A9 RESN_402 [37] R4N2 RESN_402 [57]
R3D19 RESN_402 [22] R3N6 RESN_402 [37] R4B4 RESN_805 [51] R4N6 RESN_402 [57]
R3D26 RESN_402 [22] R3P1 RESN_402 [63] R4B5 RESN_1206 [52] R4N7 RESN_402 [57]
R3E1 RESN_402 [58] R3P6 RESN_402 [61] R4B10 RESN_402 [60] R4N15 RESN_805 [51]
R3E6 RESN_402 [25] R3P10 RESN_402 [27] R4B14 RESN_805 [52] R4P1 RESN_402 [63]
R3F2 RESN_402 [58] R3P14 RESN_402 [27] R4C3 RESN_402 [5] R4P5 RESN_402 [2]
R3F7 RESN_402 [49] R3P20 RESN_402 [27] R4C13 RESN_402 [51] R4R2 RESN_402 [5]
R3F8 RESN_402 [49] R3R1 RESN_402 [31] R4C14 RESN_402 [51] R4R3 RESN_402 [3]
R3F9 RESN_402 [49] R3R2 RESN_402 [30] R4D1 RESN_402 [2] R4R5 RESN_402 [3]
CONFIDENTIAL
R4R11 RESN_402 [5] R5F4 RESN_402 [18] R6G1 RESN_402 [35] R7D4 RESN_402 [17]
R4R12 RESN_402 [5] R5F5 RESN_402 [18] R6M4 RESN_402 [58] R7D5 RESN_402 [17]
R4R13 RESN_402 [3] R5M1 RESN_805 [42] R6M5 RESN_402 [42] R7E1 RESN_402 [16]
R4R22 RESN_402 [2] R5M4 RESN_402 [36] R6N1 RESN_805 [45] R7E5 RESN_402 [14]
R4R26 RESN_402 [61] R5M8 RESN_805 [42] R6N5 RESN_402 [59] R7F1 RESN_2512 [50]
R4R27 RESN_402 [61] R5M9 RESN_402 [53] R6R1 RESN_402 [12] R7P1 RESN_402 [44]
R4R28 RESN_402 [61] R5M10 RESN_402 [59] R6R2 RESN_402 [12] R7P2 RESN_402 [44]
R4R29 RESN_402 [61] R5M11 RESN_402 [59] R6T1 RESN_402 [12] R7P3 RESN_402 [43]
R4R35 RESN_402 [61] R5M17 RESN_402 [36] R6T7 RESN_402 [12] R7R1 RESN_402 [17]
R4R36 RESN_402 [61] R5N1 RESN_402 [57] R6T8 RESN_402 [12] R7R2 RESN_402 [16]
R4U4 RESN_402 [52] R5N2 RESN_402 [57] R6T9 RESN_402 [13] R7R3 RESN_402 [17]
R4V1 RESN_402 [38] R5N3 RESN_402 [59] R6U1 RESN_402 [21] R7R4 RESN_402 [16]
R4V2 RESN_402 [38] R5N4 RESN_402 [59] R6U2 RESN_402 [21] R7R6 RESN_402 [4]
R5A3 RESN_402 [53] R5N5 RESN_402 [59] R6U3 RESN_402 [21] R7T1 RESN_402 [17]
R5A6 RESN_402 [53] R5T1 RESN_402 [4] R6U6 RESN_402 [4] R7T4 RESN_402 [14]
R5A7 RESN_402 [53] R5T2 RESN_402 [13] R7A1 RESN_2512 [38] R7T5 RESN_402 [14]
R5A10 RESN_402 [36] R5T5 RESN_402 [13] R7B1 RESN_402 [44] RT1A1 THERMISTOR_1206 [39]
R5A11 RESN_805 [53] R5T6 RESN_402 [13] R7B2 RESN_402 [44] RT1B2 THERMISTOR_1206 [41]
R5A12 RESN_402 [53] R5T7 RESN_402 [13] R7B3 RESN_402 [44] RT2A1 THERMISTOR_1206 [38]
R5A13 RESN_402 [53] R5T8 RESN_402 [2] R7B4 RESN_402 [44] RT2M1 THERMISTOR_1206 [39]
R5A14 RESN_402 [59] R5T9 RESN_402 [2] R7B5 RESN_402 [44] RT2M2 THERMISTOR_1206 [39]
R5A15 RESN_402 [53] R5U1 RESN_402 [19] R7C1 RESN_402 [44] RT3A1 THERMISTOR_1206 [37]
R5A16 RESN_402 [36] R5U2 RESN_402 [19] R7C2 RESN_402 [44] RT3A2 THERMISTOR_1812 [38]
R5A17 RESN_402 [36] R5U3 RESN_402 [19] R7C3 RESN_402 [44] RT6G1 THERMISTOR_1206 [39]
R5B1 RESN_402 [59] R5U4 RESN_402 [18] R7C4 RESN_402 [44] RT7V1 THERMISTOR_1206 [39]
R5B2 RESN_402 [53] R5U5 RESN_402 [18] R7C5 RESN_402 [44] ST1E1 SHORT_TRACE [48]
R5B3 RESN_402 [59] R5U6 RESN_402 [4] R7C6 RESN_402 [44] ST1F1 SHORT_TRACE [48]
R5B4 RESN_402 [53] R6A3 RESN_402 [42] R7C7 RESN_402 [44] ST1F2 SHORT_TRACE [48]
R5B5 RESN_402 [53] R6A4 RESN_402 [42] R7C8 RESN_402 [44] ST1F3 SHORT_TRACE [48]
R5B6 RESN_402 [57] R6A5 RESN_402 [38] R7C9 RESN_402 [44] ST1U1 SHORT_TRACE [48]
R5B7 RESN_805 [53] R6A6 RESN_402 [38] R7C10 RESN_402 [44] ST2D1 SHORT_TRACE [53]
R5B10 RESN_402 [57] R6A7 RESN_402 [63] R7C11 RESN_603 [44] ST2G1 SHORT_TRACE [47]
R5B13 RESN_805 [51] R6B1 RESN_805 [38] R7C14 RESN_805 [44] ST2U1 SHORT_TRACE [47]
R5B14 RESN_402 [57] R6C1 RESN_805 [45] R7C15 RESN_402 [43] ST2U2 SHORT_TRACE [47]
R5B15 RESN_402 [57] R6C2 THERMISTOR_603 [44] R7C16 RESN_402 [43] ST3C1 SHORT_SM [23]
R5B16 RESN_402 [57] R6F1 RESN_402 [21] R7C17 RESN_402 [43] ST3C2 SHORT_SM [23]
R5C1 RESN_805 [45] R6F2 RESN_402 [21] R7C18 RESN_402 [43] ST3C3 SHORT_SM [23]
R5C2 RESN_2512 [51] R6F3 RESN_402 [20] R7C19 RESN_402 [43] ST3C4 SHORT_SM [23]
R5F1 RESN_402 [19] R6F4 RESN_402 [20] R7C20 RESN_402 [43] ST3C5 SHORT_SM [23]
R5F2 RESN_402 [19] R6F5 RESN_402 [20] R7D2 RESN_402 [16] ST3C6 SHORT_TRACE [53]
R5F3 RESN_402 [18] R6F6 RESN_402 [4] R7D3 RESN_402 [16] ST3F1 SHORT_TRACE [49]
CONFIDENTIAL
ST4B1 SHORT_TRACE [52] STP7C6 STP_TP [64] U5A2 TPS62220_SOT23-5 [53]
ST4B2 SHORT_TRACE [52] STP7C7 STP_TP [64] U5A3 MCP4661_QFN16 [59]
ST4D1 SHORT_SM [61] STP7E1 STP_TP [64] U5B1 AD7992_MSOP10 [57]
ST4F2 SHORT_TRACE [49] STP7E2 STP_TP [64] U5B2 AD8213_MSOP10 [57]
ST4F4 SHORT_TRACE [49] STP7N1 STP_TP [64] U5B5 MOSDRIVER_SOI8 [45]
ST4R1 SHORT_SM [61] U1B1 SI4501DY_SO8 [46] U5B6 REF3333_SC70 [57]
ST4R2 SHORT_SM [61] U1D1 2X8RCPT_SM [63] U5E1 VALHALLA_1_BGA_2 [2]
ST4U1 SHORT_TRACE [49] U1E1 ADP1877_LCC32 [47] U5E1 VALHALLA_1_BGA_2 [3]
ST5A1 SHORT_TRACE [53] U1E1 ADP1877_LCC32 [48] U5E1 VALHALLA_1_BGA_2 [4]
ST5A2 SHORT_TRACE [53] U1E2 NAND_TSOP [34] U5E1 VALHALLA_1_BGA_2 [5]
ST5B1 SHORT_TRACE [53] U1E3 PS8200_LGA51 [32] U5E1 VALHALLA_1_BGA_2 [6]
ST5B2 SHORT_TRACE [53] U1F1 FET_VREG_DUAL_1_SO [48] U5E1 VALHALLA_1_BGA_2 [7 7 7 7 7]
ST5C1 SHORT_TRACE [51] -8 U5E1 VALHALLA_1_BGA_2 [8 8 8]
ST5C3 SHORT_TRACE [51] U1F2 AD7991_SOT23 [56] U5E1 VALHALLA_1_BGA_2 [12 12]
ST5D1 SHORT_TRACE [51] U1F3 REF3333_SC70 [56] U5E1 VALHALLA_1_BGA_2 [13 13]
ST5E1 SHORT_TRACE [49] U1F4 TRSET_9920_TH [35] U5F1 GDDR136_1GBIT_BGA1 [18 18]
ST5R1 SHORT_SM [6] U1T1 NAND_2CE_TSOP48 [32] 36
ST5R2 SHORT_SM [6] U1U1 AD5252_TSSOP [56] U5M1 INA219_SOT23-8 [59]
ST5R3 SHORT_SM [6] U2U1 AD8213_MSOP10 [56] U5N2 INA219_SOT23-8 [59]
ST5R4 SHORT_SM [6] U2V1 SN74LVC1G14_SC70 [63] U5N3 INA219_SOT23-8 [59]
ST5R5 SHORT_SM [6] U3A1 AUDIODAC_CSS4354_W [33] U5U1 GDDR136_1GBIT_BGA1 [19 19]
ST5T1 SHORT_SM [6] M1824_QFN25 36
ST5T2 SHORT_SM [6] U3B1 LD39100_DFN6 [52] U5U2 74LVC1G06_SC70 [4]
ST6B1 SHORT_TRACE [38] U3D1 KSB_PBGA404 [22] U6A1 INA219_SOT23-8 [58]
ST6B2 SHORT_TRACE [38] U3D1 KSB_PBGA404 [23] U6B1 MOSDRIVER_SOI8 [45]
ST6C1 SHORT_TRACE [44] U3D1 KSB_PBGA404 [24] U6F1 GDDR136_1GBIT_BGA1 [20 20]
ST6D1 SHORT_TRACE [44] U3D1 KSB_PBGA404 [25] 36
ST6D2 SHORT_SM [44] U3D1 KSB_PBGA404 [26] U6G1 IR_WHOLDER_TH [35]
ST6V1 SHORT_TRACE [50] U3D1 KSB_PBGA404 [27] U6U1 GDDR136_1GBIT_BGA1 [21 21]
ST6V2 SHORT_TRACE [50] U3D1 KSB_PBGA404 [30 30] 36
ST7A1 SHORT_TRACE [38] U3D1 KSB_PBGA404 [31] U7C1 NCP4201_LCC40 [44]
ST7A2 SHORT_TRACE [38] U3E1 AD7992_MSOP10 [58] U7D1 GDDR136_1GBIT_BGA1 [16 16]
ST7F1 SHORT_SM [50] U3E2 AD5252_TSSOP [58] 36
ST7F2 SHORT_TRACE [50] U3G1 ADP1877_LCC32 [49] U7E1 GDDR136_1GBIT_BGA1 [14 14]
ST7F3 SHORT_TRACE [50] U3G1 ADP1877_LCC32 [50] 36
STP3C1 STP_TP [64] U3G2 AD7991_SOT23 [55] U7R1 GDDR136_1GBIT_BGA1 [17 17]
STP3D1 STP_TP [64] U3G3 REF3333_SC70 [55] 36
STP4D1 STP_TP [64] U3G4 ISD2130_QFN21 [35] U7T1 GDDR136_1GBIT_BGA1 [15 15]
STP4D2 STP_TP [64] U3N1 INA219_SOT23-8 [60] 36
STP4D3 STP_TP [64] U3R1 tmp441_SOT23-8 [61] Y3D1 CRYSTAL_SM [22]
STP4D4 STP_TP [64] U3T1 REF3333_SC70 [58]
STP4D5 STP_TP [64] U3V1 AD5252_TSSOP [55]
STP4E1 STP_TP [64] U3V2 AD8213_MSOP10 [55]
STP4E2 STP_TP [64] U4A1 BAV99DUAL_SOT363 [37 37]
STP4E3 STP_TP [64] U4A2 BAV99DUAL_SOT363 [37 37]
STP5B1 STP_TP [64] U4B1 AD5252_TSSOP [57]
STP5B2 STP_TP [64] U4B2 AD7992_MSOP10 [57]
STP5D1 STP_TP [64] U4B3 IR3638_SSOP [51]
STP5D2 STP_TP [64] U4B4 MCP4661_QFN16 [60]
STP6C1 STP_TP [64] U4E1 NCP1117_DPAK [52]
STP6C2 STP_TP [64] U4E2 NCP1117_SOT223 [52]
STP7B1 STP_TP [64] U4M1 BAV99DUAL_SOT363 [37 37]
STP7C1 STP_TP [64] U4M2 BAV99DUAL_SOT363 [37 37]
STP7C2 STP_TP [64] U4P1 AT25020A_SOI8 [5]
STP7C3 STP_TP [64] U4P2 LD39015_SOT23-5 [52]
STP7C4 STP_TP [64] U4R1 tmp423_SOT23-8 [61]
STP7C5 STP_TP [64] U5A1 TPS62590_DFN6 [53]
CONFIDENTIAL

Corona: H103358 Rev A

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CR-1 : @CORONA_LIB.

PAGE CONTENTS PAGE CONTENTS

[17] MEMORY PARTITION B, BOTTOM [52] VREGS, LINEARS

R4D2 VID6 C24 CPU_VREG_APS6 OUT 43

OUT EDRAM_PSRO_DOUT N6 PSRO_DOUT

OUT CPU_EXT_CLK_EN F7 EXT_CLK_EN<DN>

CORE_HF_BGR_PLL 6 LAYER ONLY; TP ONLY

MICROSOFT PROJECT NAME PAGE FAB REV

GCPU, VIDEO + PCIEX

VSYNC_OUT M1 GPU_VSYNC_OUT OUT 23

61 OUT CPU_TEMP_N L5 CPU_THERMD_N

MEM_RST AD27 MEM_RST OUT 14 15 16 17 18 19 20 21

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

OUT CPU_VDDS0_DP P7 VDDS0_DP

V_CPUVCS V_CPUVCS V_MEM V_MEM V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

C6R4 C5D13 C5R8 C5R9 C5T26 C5E6 C5R35 C5D1

C5R15 C5D14 C6D3 C5D7 C5T32 C5E5 C5R58 C5R4

C6R2 C5R5 C6R1 C5R18 C5T22 C5T43 C5T1

C6D5 C5R16 C6R7 C5D11 C5T20 C5E9

C6D1 C6D2 C6D6 C5T33 C5T25 C4T3

MICROSOFT PROJECT NAME PAGE FAB REV

C5R33 C6R25 C6T11 C5T8 C5R63

C5R39 C5R60 C6R42 C6R45 C5R28

C6T7 C6T20 C6R37 C6R33 C5R27

C5R38 C5R32 C5R57 C6T8 C5R62

C6R31 C6R28 C5R46 C6R21 C5R51

C6R38 C5R36 C5R45 C6R20 C6R18

C6R43 C5T11 C6T14 C6R44 C6R17

MICROSOFT PROJECT NAME PAGE FAB REV

C5R25 C6R8 C6R39 C5R30 C6T5 C5T14

C6T15 C6R34 C6T3 C5R52 C5R21 C6T9

C5T19 C6R19 C6R35 C5T15 C5T16 C5T3

C6T18 C5R53 C6R22 C5T28 C6T19 C6R13

C6R9 C5T30 C5R44 C5R41 C6T25 C5R34

C6R10 C5T29 C5R47 C6R24 C6R12 C6R14

C5R20 C5R24 C5R48 C6T2 C5T2 C5T5

C5R19 C5R56 C6R26 C6T16 C6T17 C6T13

C5R22 C6T4 C6R32 C5T18 C6R40 C6T24

C5R23 C5R29 C6R29 C6R30 C6R41

MICROSOFT PROJECT NAME PAGE FAB REV

TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE

A 402 402 402 402 A

MEM VREF RESISTOR VALUE

MICROSOFT PROJECT NAME PAGE FAB REV

1 R7E7 C7T12 C7T9 C7T5 C7T4 C7T11 C7T8 C7T3 C7T6

MICROSOFT PROJECT NAME PAGE FAB REV

1 R7D3 1 R7D2 V_MEM

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

C6U9 C6U6 C6U3 C6U1 C6U2 C6U4 C6U5 C6U8

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

MICROSOFT PROJECT NAME PAGE FAB REV

KSB, CLOCKS + STRAPPING + POR

MICROSOFT PROJECT NAME PAGE FAB REV

4 IN GPU_HSYNC_OUT M22 HSYNC_IN

0.1 UF 10% 301 OHM 1%

TMDS_TX2_DP B13 HDMI_TX2_DP 0.1 UF 10% 301 OHM 1%

0.1 UF 10% 301 OHM 1%