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PAGE CONTENTS
[1]
[2]
COVER PAGE
SOC: PCIEX,CLOCKS
[48]
[49]
CONN: HDMI OUT
HDMI LOAD SWITCHES
CACTUS
[3] SOC: VIDEO [50] CONN: ODD & HDD
D
[4]
[5]
SOC: POWER: MEMIO,CPUCORE,NBCORE,MISC
SOC: POWER: V_GFXCORE
[51]
[52]
CONN: FRONT PANEL, FAN, AUDIO
CONN: POWER
REV 0.991 D
[6]
[7]
SOC: POWER: VSS
SOC: POWER: VSS
[53]
[54]
VREGS: INPUT FILTERS
VREGS: CPUCORE & GFXCORE
FAB G RETAIL
[8] SOC: MEMORY PARTITION F1 & F0 [55] VREGS: GFXCORE OUTPUT PHASE 1 & 2
[9] SOC: MEMORY PARTITION E1 & E0 [56] VREGS: GFXCORE OUTPUT PHASE 3 & 4
[10] SOC: MEMORY PARTITION D1 & D0 [57] VREGS: CPUCORE OUTPUT PHASE
[11] SOC: MEMORY PARTITION C1 & C0 [58] VREGS: MEMIO & MEMPHY
[12] SOC: MEMORY PARTITION B1 & B0 [59] VREGS: MEMPHY OUTPUT
[13] SOC: MEMORY PARTITION A1 & A0 [60] VREGS: MEMIO OUTPUT
[14] SOC: DEBUG, SB SIGNALS, V_BAT [61] VREGS: NBCORE
C [15] SOC: DECOUPLING [62] VREGS: V5P0 C
[16] SOC: DECOUPLING [63] VREGS: V3P3, VSOC1P8
[17] SOC: DECOUPLING [64] VREGS: VSOCPHY/VFUSE
[18] MEMORY: CHANNEL A0 [65] VREGS: V_SB1P8, V_SB1P1
[19] MEMORY: CHANNEL A1 [66] VREGS: V3P3 STANDBY
[20] MEMORY: CHANNEL B0 [67] VREGS: V1P1 STANDBY, V1P8 STANDBY
[21] MEMORY: CHANNEL B1 [68] STANDBY GATES
[22] MEMORY: CHANNEL A/B DECOUPLING [69] IR BLASTER
[23] MEMORY: CHANNEL C0 [70] I2C
[24] MEMORY: CHANNEL C1 [71] MARGIN: SOCPHY,SOC1P8,MEMIO,NBCORE
[25] MEMORY: CHANNEL D0 [72] MONITOR: VSOC1P8, VSOCPHY, V12P0
B [26] MEMORY: CHANNEL D1 [73] CONN: FACET BOARD
B
[27] MEMORY: CHANNEL C/D DECOUPLING [74] CONN: SWITCHES
[28] MEMORY: CHANNEL E0 [75] CONN: HDT
[29] MEMORY: CHANNEL E1 [76] CONN: M.2
[30] MEMORY: CHANNEL F0 [77] CLOCK BUFFER
[31] MEMORY: CHANNEL F1 [78] PREMIUM SPEAKER (SE/LE)
[32] MEMORY: CHANNEL E/F DECOUPLING [79] DEBUG: VR HEADERS, TEST POINTS, CONNECTORS
[33] MEMORY: ADDITIONAL DECOUPLING [80] LABELS AND MOUNTING
[34] KIC: USB [81] FRONT PANEL USB - NESTED PCB
[35] KIC: PCIEX, SATA, VIDEO [82] BOM DEFINITIONS
[36] KIC: SMC
[37] KIC: FACET
[38] KIC: POWER
[39] KIC: CLOCKS, STRAPPING, POR
[40] KIC: POWER RULES: (APPLIED WHEN POSSIBLE)
A 1. MSB TO LSB IS TOP TO BOTTOM A
[41] KIC: DECOUPLING 2. WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
3. ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
[42] ETHERNET CONTROLLER 4. AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5. LANED SIGNALS ARE GROUPED ON SYMBOLS
[43] EMMC MEMORY 6. TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7. SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
[44] CONN: RJ45,TOSLINK 8. SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9. UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE DRAWING
[45] CONN: USB (FRONT & REAR) 10.SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
12.SUFFIX _P FOR P JUNCTION Thu Apr 20 16:18:47 2017
[46] CONN: WIFI 13.SUFFIX _EN FOR ENABLE
14.'CLK' FOR CLOCKS, 'RST' FOR RESETS PROJECT NAME PAGE CSA FAB VER
[47] CONN: HDMI IN 15.PWRGD FOR POWER GOOD MICROSOFT PAGE
16.REV AND FAB ARE SET USING CUSTOM VARIABLES Cactus
TOOLS>OPTIONS>VARIABLES CONFIDENTIAL 1/82 1/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC:PCIEX,CLOCKS NOTES:
1.TO SUPPORT PCIE SPARE LANE INTERFACE (J28), POPULATE C215 AND C217
D D
2.SEE PAGES 77 AND 79 FOR ADDITIONAL PCIE SPARE LANE INFORMATION
C215
1 2 PEX_SOC_SPARE_TP_C 79
OUT
0.1 UF 10%
V_SOCPHY 6.3 V
EMPTY
402 C217
1 2 PEX_SOC_SPARE_TN_C 79
PEX_SPARE_SOC_TP
OUT
79 IN SOC_BASE 1 R500
PEX_SPARE_SOC_TN U1 IC 0.1 UF 10%
79 IN 200 OHM 6.3 V
ANUBIS 1%
C48
EMPTY
402
42 PEX_ENET_SOC_TP_C 1 OF 30 2 CH 1 2 PEX_SOC_ENET_TP_C 42
IN PEX_ENET_SOC_TN_C PCIE 402 OUT
42 IN BN58 P_ZVDD_095
P_ZCAL_VDD_095 0.1 UF 10%
16 V
35 PEX_L1_SB_SOC_TP_C X5R C53
IN PEX_L1_SB_SOC_TN_C
BU48 P_UMI_RX3_P P_UMI_TX3_P BV49 PEX_SOC_SPARE_TP 402 1 2 PEX_SOC_ENET_TN_C
35 IN BV48 BW49 PEX_SOC_SPARE_TN OUT 42
P_UMI_RX3_N P_UMI_TX3_N
BU50 P_UMI_RX2_P P_UMI_TX2_P BV51 PEX_SOC_ENET_TP 0.1 UF 10%
BV50 P_UMI_RX2_N P_UMI_TX2_N BW51 PEX_SOC_ENET_TN 16 V
35 PEX_L0_SB_SOC_TP_C X5R
IN PEX_L0_SB_SOC_TN_C
BL53 P_UMI_RX1_P P_UMI_TX1_P BK54 PEX_L1_SOC_SB_TP 402 C629
35 IN BL52 BK53 PEX_L1_SOC_SB_TN 1 2 PEX_L1_SOC_SB_TP_C
P_UMI_RX1_N P_UMI_TX1_N OUT 35
BH53 P_UMI_RX0_P P_UMI_TX0_P BG54
BH52 BG53 0.1 UF10%
C P_UMI_RX0_N P_UMI_TX0_N
PEX_L0_SOC_SB_TP
16 V
X5R C
76 PEX_L3_M2_SOC_TP BE8 P_GPP_RX3_P P_GPP_TX3_P BG8 PEX_L3_SOC_M2_TP PEX_L0_SOC_SB_TN 402 C637
IN 1 2 PEX_L1_SOC_SB_TN_C 35
76 IN PEX_L3_M2_SOC_TN BE7 P_GPP_RX3_N P_GPP_TX3_N BG7 PEX_L3_SOC_M2_TN OUT
76 PEX_L2_M2_SOC_TP BG5 P_GPP_RX2_P P_GPP_TX2_P BH7 PEX_L2_SOC_M2_TP 0.1 UF 10%
IN PEX_L2_M2_SOC_TN BG4 BH6 PEX_L2_SOC_M2_TN 16 V
76 IN P_GPP_RX2_N P_GPP_TX2_N X5R
76 PEX_L1_M2_SOC_TP BK7 P_GPP_RX1_P P_GPP_TX1_P BK4 PEX_L1_SOC_M2_TP 402
IN PEX_L1_M2_SOC_TN BK6 BK3 PEX_L1_SOC_M2_TN C649
76 IN P_GPP_RX1_N P_GPP_TX1_N 1 2 PEX_L0_SOC_SB_TP_C
PEX_L0_M2_SOC_TP BL5 BN7 PEX_L0_SOC_M2_TP OUT 35
76 IN P_GPP_RX0_P P_GPP_TX0_P
76 PEX_L0_M2_SOC_TN BL4 P_GPP_RX0_N P_GPP_TX0_N BN6 PEX_L0_SOC_M2_TN 0.1 UF 10%
IN 16 V
BP57 P_ZVSS_095 X5R
P_ZCAL_VSS 402 C658
1 2 PEX_L0_SOC_SB_TN_C 35
R501 OUT
X950118-001 BGA2409 200 OHM 0.1 UF 10%
1% 16 V
CH X5R
402 402
C1085
1 2 PEX_L3_SOC_M2_TP_C 76
M2_ONLY OUT
0.1 UF 10%
16 V
C1087 X5R
1 2 402 PEX_L3_SOC_M2_TN_C 76
M2_ONLY OUT
B V_SOCPHY 0.1 UF 10%
16 V B
X5R C1082
402 1 2 PEX_L2_SOC_M2_TP_C 76
M2_ONLY OUT
1 R235 0.1 UF 10%
510 OHM 16 V
C1083 X5R
U1 IC 5% 1 2 402 PEX_L2_SOC_M2_TN_C
OUT 76
2 CH M2_ONLY
ANUBIS 402 0.1 UF 10%
2 OF 30 16 V
CLOCKS X5R
402 1
C1080
2
77 39 SOC_NB_PEX_SS_100M_CLKP BK57 CLKIN_NB_P PEX_L1_SOC_M2_TP_C 76
IN SOC_NB_PEX_SS_100M_CLKN BK58 M2_ONLY OUT
77 39 IN CLKIN_NB_N BYPASSCLK_N
2 0.1 UF 10%
16 V
39 SOC_SYNC_NS_100M_CLKP BJ58 DISP_CLKIN_P C1081 X5R
IN SOC_SYNC_NS_100M_CLKN BJ59 1 2 402 PEX_L1_SOC_M2_TN_C
39 IN DISP_CLKIN_N OUT 76
SOC_AV_NS_100M_CLKP BG58 M2_ONLY
39 IN AV_CLKIN_P
SOC_AV_NS_100M_CLKN BG59 BYPASSCLK_P 0.1 UF 10%
39 IN AV_CLKIN_N 2 16 V
77 39 SOC_PEX_SS_100M_CLKP BH57 CLKIN_P X5R C1067
IN SOC_PEX_SS_100M_CLKN BH58 402 1 2 PEX_L0_SOC_M2_TP_C
77 39 IN CLKIN_N OUT 76
BYPASSCLK_P BM2 M2_ONLY
2 BYPASSCLK_P
BYPASSCLK_N BM3 0.1 UF 10%
2 BYPASSCLK_N 16 V
1 R239 C1068 X5R
X950118-001 BGA2409 510 OHM 1 2 402 PEX_L0_SOC_M2_TN_C 76
5% M2_ONLY OUT
2 CH 0.1 UF 10%
402 16 V
X5R
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: VIDEO
D D
U1 IC
C ANUBIS C
3 OF 30
VIDEO
35 DP_L0_SB_SOC_TP_C BM58 DP1_RX0_P DP0_TX0_P BV52 TMDS_TX_DP2 48
IN DP_L0_SB_SOC_TN_C BM57 BU52 TMDS_TX_DN2
OUT
35 IN DP1_RX0_N DP0_TX0_N OUT 48
35 DP_L1_SB_SOC_TP_C BL59 DP1_RX1_P DP0_TX1_P BW53 TMDS_TX_DP1 48
IN DP_L1_SB_SOC_TN_C BL58 BV53 TMDS_TX_DN1
OUT
35 IN DP1_RX1_N DP0_TX1_N OUT 48
DP1_RX2_P BP56 DP1_RX2_P DP0_TX2_P BV54 TMDS_TX_DP0 48
DP1_RX2_N BP55 BU54 TMDS_TX_DN0
OUT
DP1_RX2_N DP0_TX2_N OUT 48
DP1_RX3_P BN54 DP1_RX3_P DP0_TX3_P BW55 TMDS_TX_CLKP 48
DP1_RX3_N BN53 BV55 TMDS_TX_CLKN
OUT
DP1_RX3_N DP0_TX3_N OUT 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
X950118-001 BGA2409
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_GFXCORE V_GFXCORE
V_GFXCORE V_GFXCORE V_GFXCORE V_GFXCORE U1 IC
ANUBIS
U1 IC U1 IC 23 OF 30
ANUBIS ANUBIS VDD GFX
21 OF 30 22 OF 30 VDD_GFX_251 AK23
VDD GFX VDD GFX AU26 VDD_GFX_201 VDD_GFX_252 AK25
BW20 VDD_GFX_1 VDD_GFX_51 BT31 BK21 VDD_GFX_101 VDD_GFX_151 BD29 AU29 VDD_GFX_202 VDD_GFX_253 AK28
BW22 VDD_GFX_2 VDD_GFX_52 BT34 BK24 VDD_GFX_102 VDD_GFX_152 BD31 AU31 VDD_GFX_203 VDD_GFX_254 AK30
BW24 VDD_GFX_3 VDD_GFX_53 BT37 BK27 VDD_GFX_103 VDD_GFX_153 BD34 AU34 VDD_GFX_204 VDD_GFX_255 AK32
BW26 VDD_GFX_4 VDD_GFX_54 BT40 BK30 VDD_GFX_104 VDD_GFX_154 BD36 AU36 VDD_GFX_205 VDD_GFX_256 AK35
BW28 VDD_GFX_5 VDD_GFX_55 BT44 BK33 VDD_GFX_105 VDD_GFX_155 BD39 AU39 VDD_GFX_206 VDD_GFX_257 AK37
BW30 VDD_GFX_6 VDD_GFX_56 BR21 BK36 VDD_GFX_106 VDD_GFX_156 BD41 AU41 VDD_GFX_207 VDD_GFX_258 AK40
BW32 VDD_GFX_7 VDD_GFX_57 BR24 BK39 VDD_GFX_107 VDD_GFX_157 BD44 AT23 VDD_GFX_208 VDD_GFX_259 AK42
BW34 VDD_GFX_8 VDD_GFX_58 BR27 BK42 VDD_GFX_108 VDD_GFX_158 BB21 AT25 VDD_GFX_209 VDD_GFX_260 AJ24
BW36 VDD_GFX_9 VDD_GFX_59 BR30 BK45 VDD_GFX_109 VDD_GFX_159 BB24 AT28 VDD_GFX_210 VDD_GFX_261 AJ26
BW38 VDD_GFX_10 VDD_GFX_60 BR33 BJ20 VDD_GFX_110 VDD_GFX_160 BB26 AT30 VDD_GFX_211 VDD_GFX_262 AJ29
C BW40
BW42
VDD_GFX_11 VDD_GFX_61 BR36
BR39
BJ23
BJ26
VDD_GFX_111 VDD_GFX_161 BB29
BB31
AT32
AT35
VDD_GFX_212 VDD_GFX_263 AJ31
AJ34 C
VDD_GFX_12 VDD_GFX_62 VDD_GFX_112 VDD_GFX_162 VDD_GFX_213 VDD_GFX_264
BW44 VDD_GFX_13 VDD_GFX_63 BR42 BJ29 VDD_GFX_113 VDD_GFX_163 BB34 AT37 VDD_GFX_214 VDD_GFX_265 AJ36
BW45 VDD_GFX_14 VDD_GFX_64 BR45 BJ31 VDD_GFX_114 VDD_GFX_164 BB36 AT40 VDD_GFX_215 VDD_GFX_266 AJ39
BV20 VDD_GFX_15 VDD_GFX_65 BP21 BJ34 VDD_GFX_115 VDD_GFX_165 BB39 AT42 VDD_GFX_216 VDD_GFX_267 AJ41
BV22 VDD_GFX_16 VDD_GFX_66 BP24 BJ37 VDD_GFX_116 VDD_GFX_166 BB41 AR23 VDD_GFX_217 VDD_GFX_268 AH24
BV24 VDD_GFX_17 VDD_GFX_67 BP27 BJ40 VDD_GFX_117 VDD_GFX_167 BB44 AR25 VDD_GFX_218 VDD_GFX_269 AH26
BV26 VDD_GFX_18 VDD_GFX_68 BP30 BJ44 VDD_GFX_118 VDD_GFX_168 BA20 AR28 VDD_GFX_219 VDD_GFX_270 AH29
BV28 VDD_GFX_19 VDD_GFX_69 BP33 BH20 VDD_GFX_119 VDD_GFX_169 BA23 AR30 VDD_GFX_220 VDD_GFX_271 AH31
BV30 VDD_GFX_20 VDD_GFX_70 BP36 BH23 VDD_GFX_120 VDD_GFX_170 BA25 AR32 VDD_GFX_221 VDD_GFX_272 AH34
BV32 VDD_GFX_21 VDD_GFX_71 BP39 BH26 VDD_GFX_121 VDD_GFX_171 BA28 AR35 VDD_GFX_222 VDD_GFX_273 AH36
BV34 VDD_GFX_22 VDD_GFX_72 BP42 BH29 VDD_GFX_122 VDD_GFX_172 BA30 AR37 VDD_GFX_223 VDD_GFX_274 AH39
BV36 VDD_GFX_23 VDD_GFX_73 BP45 BH31 VDD_GFX_123 VDD_GFX_173 BA32 AR40 VDD_GFX_224 VDD_GFX_275 AH41
BV38 VDD_GFX_24 VDD_GFX_74 BN20 BH34 VDD_GFX_124 VDD_GFX_174 BA35 AR42 VDD_GFX_225 VDD_GFX_276 AF23
BV40 VDD_GFX_25 VDD_GFX_75 BN23 BH37 VDD_GFX_125 VDD_GFX_175 BA37 AP24 VDD_GFX_226 VDD_GFX_277 AF25
BV42 VDD_GFX_26 VDD_GFX_76 BN26 BH40 VDD_GFX_126 VDD_GFX_176 BA40 AP26 VDD_GFX_227 VDD_GFX_278 AF28
BV44 VDD_GFX_27 VDD_GFX_77 BN29 BH44 VDD_GFX_127 VDD_GFX_177 BA42 AP29 VDD_GFX_228 VDD_GFX_279 AF30
BV45 VDD_GFX_28 VDD_GFX_78 BN31 BG21 VDD_GFX_128 VDD_GFX_178 BA45 AP31 VDD_GFX_229 VDD_GFX_280 AF32
BU19 VDD_GFX_29 VDD_GFX_79 BN34 BG24 VDD_GFX_129 VDD_GFX_179 AY20 AP34 VDD_GFX_230 VDD_GFX_281 AF35
BU20 VDD_GFX_30 VDD_GFX_80 BN37 BG27 VDD_GFX_130 VDD_GFX_180 AY23 AP36 VDD_GFX_231 VDD_GFX_282 AF37
BU22 VDD_GFX_31 VDD_GFX_81 BN40 BG30 VDD_GFX_131 VDD_GFX_181 AY25 AP39 VDD_GFX_232 VDD_GFX_283 AF40
BU23 VDD_GFX_32 VDD_GFX_82 BN44 BG33 VDD_GFX_132 VDD_GFX_182 AY28 AP41 VDD_GFX_233 VDD_GFX_284 AF42
BU25 BM20 BG36 AY30 AM24 AE23
B BU26
VDD_GFX_33
VDD_GFX_34
VDD_GFX_83
VDD_GFX_84 BM23 BG39
VDD_GFX_133
VDD_GFX_134
VDD_GFX_183
VDD_GFX_184 AY32 AM26
VDD_GFX_234
VDD_GFX_235
VDD_GFX_285
VDD_GFX_286 AE25 B
BU28 VDD_GFX_35 VDD_GFX_85 BM26 BG42 VDD_GFX_135 VDD_GFX_185 AY35 AM29 VDD_GFX_236 VDD_GFX_287 AE28
BU29 VDD_GFX_36 VDD_GFX_86 BM29 BG45 VDD_GFX_136 VDD_GFX_186 AY37 AM31 VDD_GFX_237 VDD_GFX_288 AE30
BU31 VDD_GFX_37 VDD_GFX_87 BM31 BE20 VDD_GFX_137 VDD_GFX_187 AY40 AM34 VDD_GFX_238 VDD_GFX_289 AE32
BU32 VDD_GFX_38 VDD_GFX_88 BM34 BE23 VDD_GFX_138 VDD_GFX_188 AY42 AM36 VDD_GFX_239 VDD_GFX_290 AE35
BU34 VDD_GFX_39 VDD_GFX_89 BM37 BE25 VDD_GFX_139 VDD_GFX_189 AY45 AM39 VDD_GFX_240 VDD_GFX_291 AE37
BU35 VDD_GFX_40 VDD_GFX_90 BM40 BE28 VDD_GFX_140 VDD_GFX_190 AW21 AM41 VDD_GFX_241 VDD_GFX_292 AE40
BU37 VDD_GFX_41 VDD_GFX_91 BM44 BE30 VDD_GFX_141 VDD_GFX_191 AW24 AL23 VDD_GFX_242 VDD_GFX_293 AE42
BU38 VDD_GFX_42 VDD_GFX_92 BL21 BE32 VDD_GFX_142 VDD_GFX_192 AW26 AL25 VDD_GFX_243 VDD_GFX_294 AD24
BU40 VDD_GFX_43 VDD_GFX_93 BL24 BE35 VDD_GFX_143 VDD_GFX_193 AW29 AL28 VDD_GFX_244 VDD_GFX_295 AD26
BU41 VDD_GFX_44 VDD_GFX_94 BL27 BE37 VDD_GFX_144 VDD_GFX_194 AW31 AL30 VDD_GFX_245 VDD_GFX_296 AD29
BU43 VDD_GFX_45 VDD_GFX_95 BL30 BE40 VDD_GFX_145 VDD_GFX_195 AW34 AL32 VDD_GFX_246 VDD_GFX_297 AD31
BU44 VDD_GFX_46 VDD_GFX_96 BL33 BE42 VDD_GFX_146 VDD_GFX_196 AW36 AL35 VDD_GFX_247 VDD_GFX_298 AD34
BT20 VDD_GFX_47 VDD_GFX_97 BL36 BE45 VDD_GFX_147 VDD_GFX_197 AW39 AL37 VDD_GFX_248 VDD_GFX_299 AD36
BT23 VDD_GFX_48 VDD_GFX_98 BL39 BD21 VDD_GFX_148 VDD_GFX_198 AW41 AL40 VDD_GFX_249 VDD_GFX_300 AD39
BT26 VDD_GFX_49 VDD_GFX_99 BL42 BD24 VDD_GFX_149 VDD_GFX_199 AU21 AL42 VDD_GFX_250 VDD_GFX_301 AD41
BT29 VDD_GFX_50 VDD_GFX_100 BL45 BD26 VDD_GFX_150 VDD_GFX_200 AU24
X950118-001 BGA2409
X950118-001 BGA2409 X950118-001 BGA2409
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC U1 IC U1 IC
ANUBIS ANUBIS ANUBIS
28 OF 30 29 OF 30 30 OF 30
GROUND GROUND GROUND
AJ42 AD23 Y36 VSS_641 VSS_705 R48 H30 VSS_769 VSS_824 C21
VSS_513 VSS_577 Y40 R57 H34 C23
AJ44 AD25 VSS_642 VSS_706 VSS_770 VSS_825
VSS_514 VSS_578 Y41 R58 H44 C25
AJ49 AD28 VSS_643 VSS_707 VSS_771 VSS_826
VSS_515 VSS_579 Y49 N2 H47 C27
AJ57 AD30 VSS_644 VSS_708 VSS_772 VSS_827
VSS_516 VSS_580 Y52 N3 G2 C29
AJ58 AD32 VSS_645 VSS_709 VSS_773 VSS_828
VSS_517 VSS_581 T52 N5 G3 C31
AH18 AD35 VSS_646 VSS_710 VSS_774 VSS_829
VSS_518 VSS_582 W2 N8 G5 C33
AH20 AD37 VSS_647 VSS_711 VSS_775 VSS_830
VSS_519 VSS_583 W3 N11 G15 C35
AH23 AD40 VSS_648 VSS_712 VSS_776 VSS_831
VSS_520 VSS_584 W16 N49 G23 C37
AH25 AD42 VSS_649 VSS_713 VSS_777 VSS_832
VSS_521 VSS_585 W18 N52 G37 C39
AH28 AD44 VSS_650 VSS_714 VSS_778 VSS_833
VSS_522 VSS_586 W20 N55 G45 C41
AH30 AD48 VSS_651 VSS_715 VSS_779 VSS_834
VSS_523 VSS_587 W23 N57 G55 C43
AH32 AC2 VSS_652 VSS_716 VSS_780 VSS_835
VSS_524 VSS_588 W24 N58 G57 C45
AH35 AC3 VSS_653 VSS_717 VSS_781 VSS_836
VSS_525 VSS_589 W28 M6 G58 C47
AH37 AC7 VSS_654 VSS_718 VSS_782 VSS_837
C AH40
VSS_526
VSS_527
VSS_590
VSS_591 AC11 W29
W32
VSS_655 VSS_719 M9
M12
F6
F7
VSS_783 VSS_838 C49
C51 C
AH42 AC18 VSS_656 VSS_720 VSS_784 VSS_839
VSS_528 VSS_592 W34 M15 F12 C53
AG2 AC20 VSS_657 VSS_721 VSS_785 VSS_840
VSS_529 VSS_593 W37 M18 F18 C55
AG3 AC25 VSS_658 VSS_722 VSS_786 VSS_841
VSS_530 VSS_594 W39 M21 F21 C59
AG6 AC26 VSS_659 VSS_723 VSS_787 VSS_842
VSS_531 VSS_595 W42 M24 F27 B1
AG9 AC30 VSS_660 VSS_724 VSS_788 VSS_843
VSS_532 VSS_596 W44 M27 F29 B2
AG12 AC31 VSS_661 VSS_725 VSS_789 VSS_844
VSS_533 VSS_597 W57 M30 F31 B5
AG48 AC35 VSS_662 VSS_726 VSS_790 VSS_845
VSS_534 VSS_598 W58 M33 F33 B7
AG51 AC36 VSS_663 VSS_727 VSS_791 VSS_846
VSS_535 VSS_599 V12 M36 F39 B9
AG54 AC40 VSS_664 VSS_728 VSS_792 VSS_847
VSS_536 VSS_600 V18 M39 F42 B11
AG57 AC41 VSS_665 VSS_729 VSS_793 VSS_848
VSS_537 VSS_601 V20 M42 F48 B13
AG58 AC49 VSS_666 VSS_730 VSS_794 VSS_849
VSS_538 VSS_602 V25 M45 F53 B15
AF5 AC53 VSS_667 VSS_731 VSS_795 VSS_850
VSS_539 VSS_603 V26 M48 F54 B17
AF8 AC57 VSS_668 VSS_732 VSS_796 VSS_851
VSS_540 VSS_604 V30 M51 E2 B19
AF11 AC58 VSS_669 VSS_733 VSS_797 VSS_852
VSS_541 VSS_605 V31 M54 E3 B21
AF15 AA2 VSS_670 VSS_734 VSS_798 VSS_853
VSS_542 VSS_606 V35 L2 E13 B23
AF16 AA3 VSS_671 VSS_735 VSS_799 VSS_854
VSS_543 VSS_607 V36 L3 E16 B25
AF19 R9 VSS_672 VSS_736 VSS_800 VSS_855
VSS_544 VSS_608 V40 L13 E20 B27
AF21 AA9 VSS_673 VSS_737 VSS_801 VSS_856
VSS_545 VSS_609 V41 L20 E26 B29
AF24 AA12 VSS_674 VSS_738 VSS_802 VSS_857
VSS_546 VSS_610 V48 L23 E34 B31
AF26 AA15 VSS_675 VSS_739 VSS_803 VSS_858
VSS_547 VSS_611 U2 L26 E40 B33
AF29 AA16 VSS_676 VSS_740 VSS_804 VSS_859
VSS_548 VSS_612 U3 L34 E44 B35
B AF31
AF34
VSS_549 VSS_613 AA19
AA21 U57
VSS_677
VSS_678
VSS_741
VSS_742 L37 E47
VSS_805
VSS_806
VSS_860
VSS_861 B37 B
VSS_550 VSS_614 U58 L40 E57 B39
AF36 AA23 VSS_679 VSS_743 VSS_807 VSS_862
VSS_551 VSS_615 T11 L47 E58 B41
AF39 AA24 VSS_680 VSS_744 VSS_808 VSS_863
VSS_552 VSS_616 T15 L57 D1 B43
AF41 AA28 VSS_681 VSS_745 VSS_809 VSS_864
VSS_553 VSS_617 T19 L58 D9 B45
AF44 AA29 VSS_682 VSS_746 VSS_810 VSS_865
VSS_554 VSS_618 T21 K16 D15 B47
AF45 AA32 VSS_683 VSS_747 VSS_811 VSS_866
VSS_555 VSS_619 T24 K44 D45 B49
AF49 AA34 VSS_684 VSS_748 VSS_812 VSS_867
VSS_556 VSS_620 T26 J2 D51 B51
AF52 AA37 VSS_685 VSS_749 VSS_813 VSS_868
VSS_557 VSS_621 T29 J3 D59 B53
AF55 AA39 VSS_686 VSS_750 VSS_814 VSS_869
VSS_558 VSS_622 T31 J9 C1 B55
AE2 AA42 VSS_687 VSS_751 VSS_815 VSS_870
VSS_559 VSS_623 T34 J12 C5 B58
AE3 AA44 VSS_688 VSS_752 VSS_816 VSS_871
VSS_560 VSS_624 T36 J18 C7 B59
AE19 AA45 VSS_689 VSS_753 VSS_817 VSS_872
VSS_561 VSS_625 T39 J21 C9 A2
AE21 AA48 VSS_690 VSS_754 VSS_818 VSS_873
VSS_562 VSS_626 T41 J24 C11 A3
AE24 AA51 VSS_691 VSS_755 VSS_819 VSS_874
VSS_563 VSS_627 T45 J27 C13 A4
AE26 R51 VSS_692 VSS_756 VSS_820 VSS_875
VSS_564 VSS_628 T49 J29 C15 A56
AE29 AA57 VSS_693 VSS_757 VSS_821 VSS_876
VSS_565 VSS_629 R2 J31 C17 A57
AE31 AA58 VSS_694 VSS_758 VSS_822 VSS_877
VSS_566 VSS_630 R3 J33 C19 A58
AE34 T8 VSS_695 VSS_759 VSS_823 VSS_878
VSS_567 VSS_631 R12 J36
AE36 Y8 VSS_696 VSS_760
VSS_568 VSS_632 R16 J39
AE39 Y11 VSS_697 VSS_761
VSS_569 VSS_633 R19 J42
AE41 VSS_570 VSS_634 Y19 VSS_698 VSS_762 X950118-001 BGA2409
AE57 Y21 R24 VSS_699 VSS_763 J48
VSS_571 VSS_635 R29 J57
AE58 Y25 VSS_700 VSS_764
VSS_572 VSS_636 R31 J58
AD12 Y26 VSS_701 VSS_765
VSS_573 VSS_637 R36 H13
AD16 Y30 VSS_702 VSS_766
VSS_574 VSS_638 R41 H16
AD18 Y31 VSS_703 VSS_767
VSS_575 VSS_639 R44 H26
AD20 Y35 VSS_704 VSS_768
VSS_576 VSS_640
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 6 OF 30
5 OF 30 MEM CHANNEL F0
30 F0_DQ31 AP1 F0_DQ31
MEM CHANNEL F1 BI F0_DQ30 AP3
F1_DQ31 AT3 30 BI F0_DQ30
31 BI F1_DQ31 F0_DQ29 AP2
F1_DQ30 AR1 30 BI F0_DQ29
31 BI F1_DQ30 F0_DQ28 AN4
F1_DQ29 AT1 30 BI F0_DQ28
31 BI F1_DQ29 F0_DQ27 AM1
F1_DQ28 AT2 30 BI F0_DQ27
31 BI F1_DQ28 F0_DQ26 AL1
F1_DQ27 AV1 30 BI F0_DQ26
31 BI F1_DQ27 F0_DQ25 AM3
F1_DQ26 AW1 30 BI F0_DQ25
31 BI F1_DQ26 F0_DQ24 AK3
F1_DQ25 AV2 30 BI F0_DQ24
31 BI F1_DQ25 F0_DQ23 AF3
F1_DQ24 AV3 30 BI F0_DQ23
31 BI F1_DQ24 F0_DQ22 AE1
F1_DQ23 BD2 30 BI F0_DQ22
31 BI F1_DQ23 F0_DQ21 AF1
C 31 BI F1_DQ22
F1_DQ21
BD3
BD1
F1_DQ22
30
30
BI
BI F0_DQ20 AF2
F0_DQ21
F0_DQ20 C
31 BI F1_DQ21 F0_DQ19 AH1
F1_DQ20 BD4 30 BI F0_DQ19
31 BI F1_DQ20 F0_DQ18 AJ1
F1_DQ19 BB1 30 BI F0_DQ18
31 BI F1_DQ19 F0_DQ17 AH2
F1_DQ18 BA1 30 BI F0_DQ17
31 BI F1_DQ18 F0_DQ16 AH3
F1_DQ17 BB3 30 BI F0_DQ16
31 BI F1_DQ17 F0_DQ15 AG13
F1_DQ16 AY3 30 BI F0_DQ15
31 BI F1_DQ16 F0_DQ14 AK13
F1_DQ15 AP10 30 BI F0_DQ14
31 BI F1_DQ15 F0_DQ13 AJ12
F1_DQ14 AP9 30 BI F0_DQ13
31 BI F1_DQ14 F0_DQ12 AL12
F1_DQ13 AU10 30 BI F0_DQ12
31 BI F1_DQ13 F0_DQ11 AF13 AP4 F0_ADBI_N
F1_DQ12 AP7 30 BI F0_DQ11 F0_ADBI OUT 30
31 BI F1_DQ12 F0_DQ10 AL13
F1_DQ11 AY10 AT8 F1_ADBI_N 30 BI F0_DQ10
31 BI F1_DQ11 F1_ADBI OUT 31 F0_DQ9 AF12
F1_DQ10 AW10 30 BI F0_DQ9
31 BI F1_DQ10 F0_DQ8 AN13
F1_DQ9 AY9 30 BI F0_DQ8
31 BI F1_DQ9 F0_DQ7 AT11
F1_DQ8 AN8 AD13 F_DRAM_RESET 30 BI F0_DQ7
31 BI F1_DQ8 F_DRAM_RESET OUT 30 F0_DQ6 AP13
F1_DQ7 AJ9 30 BI F0_DQ6
31 BI F1_DQ7 F0_DQ5 AT13
F1_DQ6 AK8 AC13 F_MEM_CAL 30 BI F0_DQ5
31 BI F1_DQ6 F_MEM_CAL F0_DQ4 AP12
F1_DQ5 AJ10 1 R550 30 BI F0_DQ4
31 BI F1_DQ5 F0_DQ3 AW13
31 F1_DQ4 AK10 F1_DQ4 120 OHM 30 BI F0_DQ3
BI F1_DQ3 AF9 1% 30 BI F0_DQ2 AW11 F0_DQ2 F0_MA_A12 AL6 F0_MA_A12
OUT 30
31 BI F1_DQ3 F0_DQ1 AY12 AL7 F0_MA_A7
31 F1_DQ2 AF10 F1_DQ2 F1_MA_A12 AW4 F1_MA_A12 31
2 CH 30 BI F0_DQ1 F0_MA_A7 OUT 30
BI F1_DQ1 AD7 AW5 F1_MA_A7
OUT 402 30 BI F0_DQ0 AY13 F0_DQ0 F0_MA_A6 AN5 F0_MA_A6
OUT 30
31 BI F1_DQ1 F1_MA_A7 OUT 31 AJ7 F0_MA_A5
F1_DQ0 AD8 AU7 F1_MA_A6 F0_MA_A5 OUT 30
B 31 BI F1_DQ0 F1_MA_A6
F1_MA_A5 AY7 F1_MA_A5
OUT
OUT
31
31
F0_MA_A4 AJ6
AK5
F0_MA_A4
F0_MA_A3 OUT 30
B
BB4 F1_MA_A4 F0_MA_A3 OUT 30
F1_MA_A4 OUT 31 AK4 F0_MA_A2
AY4 F1_MA_A3 F0_MA_A2 OUT 30
F1_MA_A3 OUT 31 AK7 F0_MA_A1
AY6 F1_MA_A2 F0_MA_A1 OUT 30
F1_MA_A2 OUT 31 AL4 F0_MA_A0
AW8 F1_MA_A1 F0_MA_A0 OUT 30
F1_MA_A1 OUT 31
F1_MA_A0 AW7 F1_MA_A0 31
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 8 OF 30
7 OF 30 MEM CHANNEL E0
28 E0_DQ31 P1 E0_DQ31
MEM CHANNEL E1 BI E0_DQ30 P3
E1_DQ31 T3 28 BI E0_DQ30
29 BI E1_DQ31 E0_DQ29 P2
E1_DQ30 R1 28 BI E0_DQ29
29 BI E1_DQ30 E0_DQ28 N4
E1_DQ29 T1 28 BI E0_DQ28
29 BI E1_DQ29 E0_DQ27 M1
E1_DQ28 T2 28 BI E0_DQ27
29 BI E1_DQ28 E0_DQ26 L1
E1_DQ27 V1 28 BI E0_DQ26
29 BI E1_DQ27 E0_DQ25 M3
E1_DQ26 W1 28 BI E0_DQ25
29 BI E1_DQ26 E0_DQ24 K3
E1_DQ25 V2 28 BI E0_DQ24
29 BI E1_DQ25 E0_DQ23 F3
E1_DQ24 V3 28 BI E0_DQ23
29 BI E1_DQ24 E0_DQ22 E1
E1_DQ23 AD1 28 BI E0_DQ22
29 BI E1_DQ23 E0_DQ21 F1
C 29 BI E1_DQ22
E1_DQ21
AD3
AD2
E1_DQ22 28
28
BI
BI E0_DQ20 F2
E0_DQ21
E0_DQ20 C
29 BI E1_DQ21 E0_DQ19 H1
E1_DQ20 AD4 28 BI E0_DQ19
29 BI E1_DQ20 E0_DQ18 J1
E1_DQ19 AB1 28 BI E0_DQ18
29 BI E1_DQ19 E0_DQ17 H2
E1_DQ18 AA1 28 BI E0_DQ17
29 BI E1_DQ18 E0_DQ16 H3
E1_DQ17 AB3 28 BI E0_DQ16
29 BI E1_DQ17 E0_DQ15 J10
E1_DQ16 Y3 28 BI E0_DQ15
29 BI E1_DQ16 E0_DQ14 M8
E1_DQ15 V13 28 BI E0_DQ14
29 BI E1_DQ15 E0_DQ13 J8
E1_DQ14 T12 28 BI E0_DQ13
29 BI E1_DQ14 E0_DQ12 M7
E1_DQ13 Y13 28 BI E0_DQ12
29 BI E1_DQ13 E0_DQ11 G7 R7 E0_ADBI_N
E1_DQ12 T13 28 BI E0_DQ11 E0_ADBI OUT 28
29 BI E1_DQ12 E0_DQ10 N10
E1_DQ11 AA11 T7 E1_ADBI_N 28 BI E0_DQ10
29 BI E1_DQ11 E1_ADBI OUT 29 E0_DQ9 H9
E1_DQ10 AA13 28 BI E0_DQ9
29 BI E1_DQ10 E0_DQ8 N9
E1_DQ9 AC12 28 BI E0_DQ8
29 BI E1_DQ9 E0_DQ7 T10
E1_DQ8 R13 AD11 E_DRAM_RESET 28 BI E0_DQ7
29 BI E1_DQ8 E_DRAM_RESET OUT 28 E0_DQ6 T9
E1_DQ7 J13 28 BI E0_DQ6
29 BI E1_DQ7 E0_DQ5 V8
E1_DQ6 M11 D4 E_MEM_CAL 28 BI E0_DQ5
29 BI E1_DQ6 E_MEM_CAL E0_DQ4 R8
E1_DQ5 H12 28 BI E0_DQ4
29 BI E1_DQ5 1 R558 E0_DQ3 AA10
E1_DQ4 M13 28 BI E0_DQ3
29 BI E1_DQ4 120 OHM 28 E0_DQ2 Y10 E0_DQ2 E0_MA_A12 M5 E0_MA_A12 28
29 BI E1_DQ3 G13 E1_DQ3 1% BI E0_DQ1 AA8 M4 E0_MA_A7 OUT
E1_DQ2 K13 Y4 E1_MA_A12 28 BI E0_DQ1 E0_MA_A7 OUT 28
29 BI E1_DQ2 E1_MA_A12 OUT 29 2 CH 28 E0_DQ0 AC8 E0_DQ0 E0_MA_A6 N7 E0_MA_A6
E1_DQ1 E12 Y6 E1_MA_A7 402 BI OUT 28
29 BI E1_DQ1 E1_MA_A7 OUT 29 J5 E0_MA_A5
E1_DQ0 L12 V7 E1_MA_A6 E0_MA_A5 OUT 28
B 29 BI E1_DQ0 E1_MA_A6
E1_MA_A5 AC6 E1_MA_A5
OUT
OUT
29
29
E0_MA_A4 J7
K7
E0_MA_A4
E0_MA_A3 OUT 28
B
AC4 E1_MA_A4 E0_MA_A3 OUT 28
E1_MA_A4 OUT 29 J4 E0_MA_A2
AA4 E1_MA_A3 E0_MA_A2 OUT 28
E1_MA_A3 OUT 29 K6 E0_MA_A1
AA5 E1_MA_A2 E0_MA_A1 OUT 28
E1_MA_A2 OUT 29 K4 E0_MA_A0
AA7 E1_MA_A1 E0_MA_A0 OUT 28
E1_MA_A1 OUT 29
E1_MA_A0 Y7 E1_MA_A0 29
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 10 OF 30
9 OF 30 MEM CHANNELD0
25 D0_DQ31 A18 D0_DQ31
MEM CHANNEL D1 BI D0_DQ30 C18
D1_DQ31 C20 25 BI D0_DQ30
26 BI D1_DQ31 D0_DQ29 B18
D1_DQ30 A19 25 BI D0_DQ29
26 BI D1_DQ30 D0_DQ28 D18
D1_DQ29 A20 25 BI D0_DQ28
26 BI D1_DQ29 D0_DQ27 C16
D1_DQ28 B20 25 BI D0_DQ27
26 BI D1_DQ28 D0_DQ26 C14
D1_DQ27 B22 25 BI D0_DQ26
26 BI D1_DQ27 D0_DQ25 A16
D1_DQ26 C22 25 BI D0_DQ25
26 BI D1_DQ26 D0_DQ24 A15
D1_DQ25 A22 25 BI D0_DQ24
26 BI D1_DQ25 D0_DQ23 C10
D1_DQ24 A23 25 BI D0_DQ23
26 BI D1_DQ24 D0_DQ22 A9
D1_DQ23 A28 25 BI D0_DQ22
26 BI D1_DQ23 D0_DQ21 A10
C 26 BI D1_DQ22
D1_DQ21
C28
B28
D1_DQ22 25
25
BI
BI D0_DQ20 B10
D0_DQ21
D0_DQ20 C
26 BI D1_DQ21 D0_DQ19 B12
D1_DQ20 D27 25 BI D0_DQ19
26 BI D1_DQ20 D0_DQ18 D12
D1_DQ19 C26 25 BI D0_DQ18
26 BI D1_DQ19 D0_DQ17 A12
D1_DQ18 C24 25 BI D0_DQ17
26 BI D1_DQ18 D0_DQ16 A13
D1_DQ17 A26 25 BI D0_DQ16
26 BI D1_DQ17 D0_DQ15 G16
D1_DQ16 A25 25 BI D0_DQ15
26 BI D1_DQ16 D0_DQ14 H18
D1_DQ15 N27 25 BI D0_DQ14
26 BI D1_DQ15 D0_DQ13 F15
D1_DQ14 N24 25 BI D0_DQ13
26 BI D1_DQ14 D0_DQ12 G18
D1_DQ13 L27 25 BI D0_DQ12
26 BI D1_DQ13 D0_DQ11 F13 D10 D0_ADBI_N
D1_DQ12 L24 25 BI D0_DQ11 D0_ADBI OUT 25
26 BI D1_DQ12 D0_DQ10 D13
D1_DQ11 L29 E21 D1_ADBI_N 25 BI D0_DQ10
26 BI D1_DQ11 D1_ADBI OUT 26 D0_DQ9 H15
D1_DQ10 N23 25 BI D0_DQ9
26 BI D1_DQ10 D0_DQ8 G20
D1_DQ9 N29 25 BI D0_DQ8
26 BI D1_DQ9 D0_DQ7 K26
D1_DQ8 M23 A29 D_DRAM_RESET 25 BI D0_DQ7
26 BI D1_DQ8 D_DRAM_RESET OUT 25 D0_DQ6 H21
D1_DQ7 N20 25 BI D0_DQ6
26 BI D1_DQ7 D0_DQ5 J26
D1_DQ6 M20 C30 D_MEM_CAL 25 BI D0_DQ5
26 BI D1_DQ6 D_MEM_CAL D0_DQ4 G21
D1_DQ5 N18 25 BI D0_DQ4
26 BI D1_DQ5 1 R529 D0_DQ3 K27
D1_DQ4 N21 25 BI D0_DQ3
26 BI D1_DQ4 120 OHM 25 D0_DQ2 J23 D0_DQ2 D0_MA_A12 B8 D0_MA_A12 25
26 BI D1_DQ3 M16 D1_DQ3 1% BI D0_DQ1 K29 G9 D0_MA_A7 OUT
D1_DQ2 J16 E24 D1_MA_A12 25 BI D0_DQ1 D0_MA_A7 OUT 25
26 BI D1_DQ2 D1_MA_A12 OUT 26 2 CH 25 D0_DQ0 K23 D0_DQ0 D0_MA_A6 E9 D0_MA_A6 25
26 BI D1_DQ1 L15 D1_DQ1 D1_MA_A7 G24 D1_MA_A7
OUT 26 402 BI A5 D0_MA_A5 OUT
D1_DQ0 N15 D23 D1_MA_A6 D0_MA_A5 OUT 25
B 26 BI D1_DQ0 D1_MA_A6
D1_MA_A5 H27 D1_MA_A5
OUT
OUT
26
26
D0_MA_A4 A6
A7
D0_MA_A4
D0_MA_A3 OUT 25
B
G27 D1_MA_A4 D0_MA_A3 OUT 25
D1_MA_A4 OUT 26 C6 D0_MA_A2
F26 D1_MA_A3 D0_MA_A2 OUT 25
D1_MA_A3 OUT 26 C8 D0_MA_A1
D26 D1_MA_A2 D0_MA_A1 OUT 25
D1_MA_A2 OUT 26 A8 D0_MA_A0
G26 D1_MA_A1 D0_MA_A0 OUT 25
D1_MA_A1 OUT 26
D1_MA_A0 D24 D1_MA_A0 26
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 12 OF 30
11 OF 30 MEM CHANNEL C0
23 C0_DQ31 A42 C0_DQ31
MEM CHANNEL C1 BI C0_DQ30 C42
C1_DQ31 C40 23 BI C0_DQ30
24 BI C1_DQ31 C0_DQ29 B42
C1_DQ30 A41 23 BI C0_DQ29
24 BI C1_DQ30 C0_DQ28 D42
C1_DQ29 B40 23 BI C0_DQ28
24 BI C1_DQ29 C0_DQ27 A44
C1_DQ28 A40 23 BI C0_DQ27
24 BI C1_DQ28 C0_DQ26 A45
C1_DQ27 B38 23 BI C0_DQ26
24 BI C1_DQ27 C0_DQ25 C44
C1_DQ26 A37 23 BI C0_DQ25
24 BI C1_DQ26 C0_DQ24 C46
C1_DQ25 C38 23 BI C0_DQ24
24 BI C1_DQ25 C0_DQ23 A51
C1_DQ24 A38 23 BI C0_DQ23
24 BI C1_DQ24 C0_DQ22 C50
C1_DQ23 A32 23 BI C0_DQ22
24 BI C1_DQ23 C0_DQ21 B50
C 24 BI C1_DQ22
C1_DQ21
C32
B32
C1_DQ22 23
23
BI
BI C0_DQ20 A50
C0_DQ21
C0_DQ20 C
24 BI C1_DQ21 C0_DQ19 B48
C1_DQ20 D33 23 BI C0_DQ19
24 BI C1_DQ20 C0_DQ18 A47
C1_DQ19 A34 23 BI C0_DQ18
24 BI C1_DQ19 C0_DQ17 C48
C1_DQ18 A35 23 BI C0_DQ17
24 BI C1_DQ18 C0_DQ16 A48
C1_DQ17 C34 23 BI C0_DQ16
24 BI C1_DQ17 C0_DQ15 H45
C1_DQ16 C36 23 BI C0_DQ15
24 BI C1_DQ16 C0_DQ14 G44
C1_DQ15 L36 23 BI C0_DQ14
24 BI C1_DQ15 C0_DQ13 F45
C1_DQ14 N37 23 BI C0_DQ13
24 BI C1_DQ14 C0_DQ12 G42
C1_DQ13 N36 23 BI C0_DQ12
24 BI C1_DQ13 C0_DQ11 D47 D50 C0_ADBI_N
C1_DQ12 M37 23 BI C0_DQ11 C0_ADBI OUT 23
24 BI C1_DQ12 C0_DQ10 H42
C1_DQ11 N33 E39 C1_ADBI_N 23 BI C0_DQ10
24 BI C1_DQ11 C1_ADBI OUT 24 C0_DQ9 F47
C1_DQ10 L33 23 BI C0_DQ9
24 BI C1_DQ10 C0_DQ8 G40
C1_DQ9 L31 23 BI C0_DQ8
24 BI C1_DQ9 C0_DQ7 J37
C1_DQ8 N31 A31 C_DRAM_RESET 23 BI C0_DQ7
24 BI C1_DQ8 C_DRAM_RESET OUT 23 C0_DQ6 H39
C1_DQ7 M44 23 BI C0_DQ6
24 BI C1_DQ7 C0_DQ5 K37
C1_DQ6 N42 D30 C_MEM_CAL 23 BI C0_DQ5
24 BI C1_DQ6 C_MEM_CAL C0_DQ4 G39
C1_DQ5 J44 23 BI C0_DQ4
24 BI C1_DQ5 1 R533 C0_DQ3 K34
C1_DQ4 M40 23 BI C0_DQ3
24 BI C1_DQ4 120 OHM 23 C0_DQ2 J34 C0_DQ2 C0_MA_A12 B52 C0_MA_A12 23
24 BI C1_DQ3 L45 C1_DQ3 1% BI C0_DQ1 K33 G51 C0_MA_A7 OUT
C1_DQ2 N40 E36 C1_MA_A12 23 BI C0_DQ1 C0_MA_A7 OUT 23
24 BI C1_DQ2 C1_MA_A12 OUT 24 2 CH 23 C0_DQ0 K31 C0_DQ0 C0_MA_A6 E51 C0_MA_A6 23
24 BI C1_DQ1 N45 C1_DQ1 C1_MA_A7 G36 C1_MA_A7
OUT 24 402 BI A55 C0_MA_A5 OUT
C1_DQ0 N39 D37 C1_MA_A6 C0_MA_A5 OUT 23
B 24 BI C1_DQ0 C1_MA_A6
C1_MA_A5 H33 C1_MA_A5
OUT
OUT
24
24
C0_MA_A4 A54
A53
C0_MA_A4
C0_MA_A3 OUT 23
B
G33 C1_MA_A4 C0_MA_A3 OUT 23
C1_MA_A4 OUT 24 C54 C0_MA_A2
F34 C1_MA_A3 C0_MA_A2 OUT 23
C1_MA_A3 OUT 24 C52 C0_MA_A1
D34 C1_MA_A2 C0_MA_A1 OUT 23
C1_MA_A2 OUT 24 A52 C0_MA_A0
G34 C1_MA_A1 C0_MA_A0 OUT 23
C1_MA_A1 OUT 24
C1_MA_A0 D36 C1_MA_A0 24
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 14 OF 30
13 OF 30 MEM CHANNEL B0
20 B0_DQ31 P59 B0_DQ31
MEM CHANNEL B1 BI B0_DQ30 P57
B1_DQ31 T57 20 BI B0_DQ30
21 BI B1_DQ31 B0_DQ29 P58
B1_DQ30 R59 20 BI B0_DQ29
21 BI B1_DQ30 B0_DQ28 N56
B1_DQ29 T59 20 BI B0_DQ28
21 BI B1_DQ29 B0_DQ27 M57
B1_DQ28 T58 20 BI B0_DQ27
21 BI B1_DQ28 B0_DQ26 K57
B1_DQ27 V58 20 BI B0_DQ26
21 BI B1_DQ27 B0_DQ25 M59
B1_DQ26 V57 20 BI B0_DQ25
21 BI B1_DQ26 B0_DQ24 L59
B1_DQ25 V59 20 BI B0_DQ24
21 BI B1_DQ25 B0_DQ23 F57
B1_DQ24 W59 20 BI B0_DQ23
21 BI B1_DQ24 B0_DQ22 E59
B1_DQ23 AD59 20 BI B0_DQ22
21 BI B1_DQ23 B0_DQ21 F59
B1_DQ22 AD57 20 BI B0_DQ21
C 21
21
BI
BI B1_DQ21 AD58
B1_DQ22
B1_DQ21 20 BI B0_DQ20
B0_DQ19
F58
H58
B0_DQ20
C
B1_DQ20 AD56 20 BI B0_DQ19
21 BI B1_DQ20 B0_DQ18 H57
B1_DQ19 AB57 20 BI B0_DQ18
21 BI B1_DQ19 B0_DQ17 H59
B1_DQ18 Y57 20 BI B0_DQ17
21 BI B1_DQ18 B0_DQ16 J59
B1_DQ17 AB59 20 BI B0_DQ16
21 BI B1_DQ17 B0_DQ15 M53
B1_DQ16 AA59 20 BI B0_DQ15
21 BI B1_DQ16 B0_DQ14 N50
B1_DQ15 AA49 20 BI B0_DQ14
21 BI B1_DQ15 B0_DQ13 M52
B1_DQ14 V47 20 BI B0_DQ13
21 BI B1_DQ14 B0_DQ12 N51
B1_DQ13 Y47 20 BI B0_DQ12
21 BI B1_DQ13 B0_DQ11 G53 R53 B0_ADBI_N
B1_DQ12 T47 20 BI B0_DQ11 B0_ADBI OUT 20
21 BI B1_DQ12 B0_DQ10 J52
B1_DQ11 AA47 T53 B1_ADBI_N 20 BI B0_DQ10
21 BI B1_DQ11 B1_ADBI OUT 21 B0_DQ9 H51
B1_DQ10 T48 20 BI B0_DQ9
21 BI B1_DQ10 B0_DQ8 J50
B1_DQ9 AC48 20 BI B0_DQ8
21 BI B1_DQ9 B0_DQ7 AA52
B1_DQ8 R47 AD49 B_DRAM_RESET 20 BI B0_DQ7
21 BI B1_DQ8 B_DRAM_RESET OUT 20 B0_DQ6 V52
B1_DQ7 M49 20 BI B0_DQ6
21 BI B1_DQ7 B0_DQ5 Y50
B1_DQ6 L48 D56 B_MEM_CAL 20 BI B0_DQ5
21 BI B1_DQ6 B_MEM_CAL B0_DQ4 T51
B1_DQ5 K47 20 BI B0_DQ4
21 BI B1_DQ5 1 R495 B0_DQ3 AA50
B1_DQ4 M47 20 BI B0_DQ3
21 BI B1_DQ4 120 OHM 20 B0_DQ2 R52 B0_DQ2 B0_MA_A12 M55 B0_MA_A12 20
21 BI B1_DQ3 H48 B1_DQ3 1% BI B0_DQ1 AC52 M56 B0_MA_A7 OUT
B1_DQ2 J47 Y56 B1_MA_A12 20 BI B0_DQ1 B0_MA_A7 OUT 20
21 BI B1_DQ2 B1_MA_A12 OUT 21 2 CH 20 B0_DQ0 T50 B0_DQ0 B0_MA_A6 N53 B0_MA_A6 20
21 BI B1_DQ1 G47 B1_DQ1 B1_MA_A7 Y54 B1_MA_A7
OUT 21 402 BI J55 B0_MA_A5 OUT
B1_DQ0 E48 V53 B1_MA_A6 B0_MA_A5 OUT 20
21 BI B1_DQ0 B1_MA_A6 OUT 21 J53 B0_MA_A4
B B1_MA_A5 AC54
AC56
B1_MA_A5
B1_MA_A4
OUT 21
B0_MA_A4
B0_MA_A3 K53 B0_MA_A3 OUT
OUT
20
20 B
B1_MA_A4 OUT 21 J56 B0_MA_A2
AA56 B1_MA_A3 B0_MA_A2 OUT 20
B1_MA_A3 OUT 21 K54 B0_MA_A1
AA55 B1_MA_A2 B0_MA_A1 OUT 20
B1_MA_A2 OUT 21 K56 B0_MA_A0
AA53 B1_MA_A1 B0_MA_A0 OUT 20
B1_MA_A1 OUT 21
B1_MA_A0 Y53 B1_MA_A0 21
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1 IC
U1 IC ANUBIS
ANUBIS 16 OF 30
15 OF 30 MEM CHANNEL A0
18 A0_DQ31 AP59 A0_DQ31
MEM CHANNEL A1 BI A0_DQ30 AP57
A1_DQ31 AT57 18 BI A0_DQ30
19 BI A1_DQ31 A0_DQ29 AP58
A1_DQ30 AR59 18 BI A0_DQ29
19 BI A1_DQ30 A0_DQ28 AN56
A1_DQ29 AT59 18 BI A0_DQ28
19 BI A1_DQ29 A0_DQ27 AM57
A1_DQ28 AT58 18 BI A0_DQ27
19 BI A1_DQ28 A0_DQ26 AK57
A1_DQ27 AV58 18 BI A0_DQ26
19 BI A1_DQ27 A0_DQ25 AM59
A1_DQ26 AV57 18 BI A0_DQ25
19 BI A1_DQ26 A0_DQ24 AL59
A1_DQ25 AV59 18 BI A0_DQ24
19 BI A1_DQ25 A0_DQ23 AF57
A1_DQ24 AW59 18 BI A0_DQ23
19 BI A1_DQ24 A0_DQ22 AE59
A1_DQ23 BD59 18 BI A0_DQ22
19 BI A1_DQ23 A0_DQ21 AF59
C 19 BI A1_DQ22
A1_DQ21
BD57
BD58
A1_DQ22 18
18
BI
BI A0_DQ20 AF58
A0_DQ21
A0_DQ20 C
19 BI A1_DQ21 A0_DQ19 AH58
A1_DQ20 BD56 18 BI A0_DQ19
19 BI A1_DQ20 A0_DQ18 AH57
A1_DQ19 BB57 18 BI A0_DQ18
19 BI A1_DQ19 A0_DQ17 AH59
A1_DQ18 AY57 18 BI A0_DQ17
19 BI A1_DQ18 A0_DQ16 AJ59
A1_DQ17 BB59 18 BI A0_DQ16
19 BI A1_DQ17 A0_DQ15 AK47
A1_DQ16 BA59 18 BI A0_DQ15
19 BI A1_DQ16 A0_DQ14 AL47
A1_DQ15 AW50 18 BI A0_DQ14
19 BI A1_DQ15 A0_DQ13 AJ48
A1_DQ14 AP51 18 BI A0_DQ13
19 BI A1_DQ14 A0_DQ12 AN47
A1_DQ13 AU50 18 BI A0_DQ12
19 BI A1_DQ13 A0_DQ11 AF48 AP56 A0_ADBI_N
A1_DQ12 AP50 18 BI A0_DQ11 A0_ADBI OUT 18
19 BI A1_DQ12 A0_DQ10 AG47
A1_DQ11 AY50 AT52 A1_ADBI_N 18 BI A0_DQ10
19 BI A1_DQ11 A1_ADBI OUT 19 A0_DQ9 AF47
A1_DQ10 AP53 18 BI A0_DQ9
19 BI A1_DQ10 A0_DQ8 AL48
A1_DQ9 AY51 18 BI A0_DQ8
19 BI A1_DQ9 A0_DQ7 AW47
A1_DQ8 AN52 AD47 A_DRAM_RESET 18 BI A0_DQ7
19 BI A1_DQ8 A_DRAM_RESET OUT 18 A0_DQ6 AT47
A1_DQ7 AJ50 18 BI A0_DQ6
19 BI A1_DQ7 A0_DQ5 AW49
A1_DQ6 AK52 AC47 A_MEM_CAL 18 BI A0_DQ5
19 BI A1_DQ6 A_MEM_CAL A0_DQ4 AT49
A1_DQ5 AJ51 1 R510 18 BI A0_DQ4
19 BI A1_DQ5 A0_DQ3 AY48
19 A1_DQ4 AK50 A1_DQ4 120 OHM 18 BI A0_DQ3
BI A1_DQ3 AF51 1% 18 BI A0_DQ2 AP48 A0_DQ2 A0_MA_A12 AL54 A0_MA_A12
OUT 18
19 BI A1_DQ3 A0_DQ1 AY47 AL53 A0_MA_A7
19 A1_DQ2 AF50 A1_DQ2 A1_MA_A12 AW56 A1_MA_A12 19
2 CH 18 BI A0_DQ1 A0_MA_A7 OUT 18
BI A1_DQ1 AD52 AW55 A1_MA_A7
OUT 402 18 BI A0_DQ0 AP47 A0_DQ0 A0_MA_A6 AN55 A0_MA_A6
OUT 18
19 BI A1_DQ1 A1_MA_A7 OUT 19 AJ53 A0_MA_A5
A1_DQ0 AD53 AU53 A1_MA_A6 A0_MA_A5 OUT 18
B 19 BI A1_DQ0 A1_MA_A6
A1_MA_A5 AY53 A1_MA_A5
OUT
OUT
19
19
A0_MA_A4 AJ54
AK55
A0_MA_A4
A0_MA_A3 OUT 18
B
BB56 A1_MA_A4 A0_MA_A3 OUT 18
A1_MA_A4 OUT 19 AK56 A0_MA_A2
AY56 A1_MA_A3 A0_MA_A2 OUT 18
A1_MA_A3 OUT 19 AK53 A0_MA_A1
AY54 A1_MA_A2 A0_MA_A1 OUT 18
A1_MA_A2 OUT 19 AL56 A0_MA_A0
AW52 A1_MA_A1 A0_MA_A0 OUT 18
A1_MA_A1 OUT 19
A1_MA_A0 AW53 A1_MA_A0 19
OUT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC:DEBUG,SB SIGNALS,V_BAT
D D
U1 IC
ANUBIS
4 OF 30
JTAG/DEBUG
ATE_TSTCLK_EN BE47 ATE_TSTCLK_EN
BF58 DLY_PSP_RESET
BD13 PSEN TMON_CAL1 BH4 TMON_CAL1 1
FTP FT75
BF57 A0_BYPASS TMON_CAL0 BH3 TMON_CAL0 1
FTP FT78
36 SOC_THERMTRIP_N BL1 THERMTRIP_N
OUT
R84
39 X32K_X2_R 1 2 X32K_X2 BN50 X32K_X2
IN X32K_X1 BP50
0 OHM 5% X32K_X1
402 CH
R97 GPIO_3P3_3 BD53 3P3V_GPIO3 PLLTEST0 BP4 PLLTEST0 75
1 2
GPIO_3P3_2 BE55 BN4 PLLTEST1
OUT
3P3V_GPIO2 PLLTEST1 OUT 75
20 MOHM 5% GPIO_3P3_1 BE56 3P3V_GPIO1
402 EMPTY GPIO_3P3_0 BE59 BE4 THERMDA
3P3V_GPIO0 THERMDA
58 GPIO_1P8_3 BN56 1P8V_GPIO9 THERMDC BE5 THERMDC
Y1 OUT GPIO_1P8_2 BK51 1P8V_GPIO8 R524
2 1 GPIO_1P8_1 BT48 1P8V_GPIO7 ANALOGOUT BE50 ANALOGOUT 1 KOHM R525
C144 C155 1GPIO_1P8_0 BT50 1% DEBUG 1 KOHM
C EMPTY SM 1
EMPTY
FT415 FTP
GPIO_POSTOUT_5 BR51
1P8V_GPIO6
1P8V_GPIO5 DIECRACKMON BE49 DIECRACKMON CH 1% DEBUG
V_1P8STBY C
2.2 PF 402 EMPTY 402 2.2 PF GPIO_POSTOUT_4 BT51 1P8V_GPIO4 402 CH
32.768 KHZ GPIO_POSTOUT_3 BR54 BG47 BP_0
402
50 V 50 V 1P8V_GPIO3 BP_0 DEBUG
2 GPIO_POSTOUT_2 BP53 BG48 BP_1
+/-0.1PF +/-0.1PF 1P8V_GPIO2 BP_1 1 R405
GPIO_POSTOUT_1 BT54 1P8V_GPIO1 BP_2 BH49 BP_2 475 OHM
GPIO_POSTOUT_0 BT53 1P8V_GPIO0 BP_3 BH50 BP_3 SVT 54 1%
V_SOC1P8 IN
SVD 2 EMPTY
75 DBREQ_L BF2 DBREQ_N ANATSTIN_P BG50 ANATSTIN_P 1 R626 BI 54 R430 402
IN DBRDY BE1 BG51 ANATSTIN_N 0 OHM SVC
2 1 SB_SOC_DATA
BI 36
C144, C155 VALUE SELECTED 75 OUT DBRDY ANATSTIN_N 5% OUT 54
1% 243 OHM
TO CENTER XTAL FREQ 1 R392 75 IN TRST_L BJ2 TRST_N CH 402 1 DEBUG
10 KOHM TMS BH2 BE52 ANATSTOUT_P 2 CH 1 R627 C553
5% 75 36 IN TMS ANATSTOUT_P 402
DB16 TDO BF3 TDO ANATSTOUT_N BE53 ANATSTOUT_N 0 OHM 47 PF
2 EMPTY
75 36 OUT TDI BG2 5% 5% V_1P8STBY
1
402 75 36 IN TDI 50 V
TCK BG1 BK2 SP_SMC_INT_N 2 CH 1 R628 2 EMPTY
75 36 IN TCK ALERT_N OUT 36 402 402 DEBUG
0 OHM
1 R391 SOC_RST_N BJ1 BM48 SVT_R_SOC 5% 1 R406
10 KOHM 75 36 IN RESET_N SVT
2 CH 475 OHM
1% 54 36 IN SOC_PWR_OK BL2 PWROK SVD BR48 SVD_R_SOC
402 1%
2 CH 75 SVC BN48 SVC_R_SOC 2 EMPTY
402 SID BM51 SID R431 402
1 SIC BN51 SIC 2 1 SB_SOC_CLK 36
FT414 FTP
BJ48 RTCCLK
IN
RTCCLK 1% 243 OHM
CH 402 1 DEBUG
B C554
VDD_MEM_SENSE K30 SOC_MEMIO_S
BI 14 58
47 PF
5% B
N30 SOC_MEMPHY_S 50 V
VDD_MEMP_SENSE BI 14 58 2 EMPTY
VSS_MEM_SENSE L30 SOC_MEMIO_S_RTN 14 58 402
BV46 SOC_GFXCORE_S_RTN
BI
VSS_GFX_SENSE 1 OUT 14 54
VDD_GFX_SENSE BW46 SOC_GFXCORE_S DB127 14 54
OUT
C1220
VDD_CORE_PROBE BP47 VDD_CORE_PROBE VDD_NB_SENSE BV7 SOC_NBCORE_S 61 58 14 SOC_MEMIO_S 1 2 SOC_MEMIO_S_RTN 14 58
DB58
1
VSS_CORE_PROBE BN47 BW7 SOC_NBCORE_S_RTN
BI
VSS_CORE_PROBE VSS_NB_SENSE 61
VDD_GFX_PROBE BK47 BW47 SOC_CPUCORE_S 1 UF 10%
54 OUT VDD_GFX_PROBE VDD_CORE_SENSE OUT 14 54 6.3 V
54 VSS_GFX_PROBE BK48 VSS_GFX_PROBE VSS_CORE_SENSE BV47 SOC_CPUCORE_S_RTN 14 54 EMPTY
OUT VDD_MEMP_PROBE B30 BP58 SOC_SOCPHY_S
BI 402
VDD_MEMP_PROBE VDD_095_SENSE OUT 64
VSS_MEMP_PROBE A30 VSS_MEMP_PROBE VSS_095_SENSE BR57 C1221
V_CPUCORE 58 14 SOC_MEMPHY_S 1 2 SOC_MEMIO_S_RTN 14 58
X950118-001 BGA2409 NOTE: SOC_MEMIO_S_RTN IS ACTUALLY SENSE 1 UF 10%
1 SENSE CONNECTION FOR VRTB RETURN FROM SOC FOR MEMPHY. NOT CHANGING 6.3 V
DB63 EMPTY
V_GFXCORE NETNAME TO STAY CONSISTENT WITH SCB 402
C1222
54 14 SOC_GFXCORE_S 1 2 SOC_GFXCORE_S_RTN 14 54
1
DB59 1 UF 10%
6.3 V
EMPTY
V_1P8STBY 402
C1223
SOC_CPUCORE_S 1 2 SOC_CPUCORE_S_RTN
V_3P3STBY 54 14 14 54
1 R387 NOTE: SINCE C1222 AND C1223 ARE NEAR SOC,
1 UF 10%
0 OHM V_BAT CHANGE THEM TO X6S/X7R IF EVER STUFFED 6.3 V
U77 Q1 EMPTY 5% DUE TO HIGHER TEMPERATURES IN AREA EMPTY
2 2 CH V_BAT 402
NCP663 R77 402 A
A DB93 1 RTC_VREG_IN 1
3 RTC_VREG_IN_D 2 VIN VOUT 3 RTC_VREG_OUT 1 2 NOM.VOLTAGE: 1.8V C1220, C1221, C1222, AND C1223 ARE THE QUALIFICATION/MEASUREMENT TEST POINTS
FOR THE RELEVANT SOC VR, AND MUST BE MEASURED WITH A DIFFERENTIAL PROBE
0 OHM 5%
3.0V BATTERY LARGE-TP 4 NC GND 1 402 EMPTY
INPUT DB92 1 C513 1
SOT-523 C512 X899201-001 0.1 UF
LARGE-TP 0.1 UF 10% R388
EMPTY 10% SC82 16 V
2 221 KOHM
16 V EMPTY 1%
EMPTY 402
402 EMPTY
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_GFXCORE
SOC: DECOUPLING V_GFXCORE 57 0603 10UF
1
C785
10 UF 20%
2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_CPUCORE V_CPUCORE
SOC: DECOUPLING
V_CPUCORE
V_NBCORE V_NBCORE V_NBCORE V_NBCORE
12 0805 10UF V_SOCPHY
D 13 0805 22UF D
27 0805 22UF 22 0603 10UF 15 0805 22UF EMPTY
1
C713
2 V_NBCORE
10 UF 20%
5 0402 1UF
6.3 V C824 C921 C336
X6S 1 2 1 2 1 2 C879 C825 C614
805 1 2 1 2 1 2 C965 C374 C511 C1295 3 0402 1UF 4 0603 4.7 UF 10 0603 10UF
1 2 1 2 1 2 1 2
C859 22 UF 20% 22 UF 20% 22 UF 20% C946 C928
1 2 6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% 1 UF 10% 1 2 C958 1 2
X6S X6S X6S 6.3 V 6.3 V 6.3 V 22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% 1 2
805 805 805 X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V
10 UF 20% 603 603 402 X6S X6S EMPTY EMPTY 1 UF 10% 10 UF 20%
6.3 V 805 805 805 805 6.3 V 4.7 UF 10% 6.3 V
X6S C887 C884 C337 X6S 6.3 V X6S
1 2 1 2 1 2 C878 C810 C611 C1287 X6S
805 1 2 1 2 1 2 C964 C362 C1296 402 603
1 2 1 2 1 2 1 2 603
C860 22 UF 20% 22 UF 20% 22 UF 20% C949 C974
1 2 6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% 1 UF 10% 1 2 C957 1 2
X6S X6S X6S 6.3 V 6.3 V 6.3 V 22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% 1 2
805 805 805 X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V
10 UF 20% 603 603 402 X6S X6S EMPTY X6S 1 UF 10% 10 UF 20%
6.3 V 805 805 805 805 6.3 V 4.7 UF 10% 6.3 V
X6S C316 C923 C338 X6S 6.3 V X6S
1 2 1 2 1 2 C880 C794 C605 X6S
805 1 2 1 2 1 2 402 603
C966 C359 C1288 C1297 603
22 UF 20% 22 UF 20% 22 UF 20% 1 2 1 2 1 2 1 2
C861 6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% 1 UF 10% C950 C952 C986
1 2 X6S X6S X6S 6.3 V 6.3 V 6.3 V 22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% 1 2 1 2 1 2
805 805 805 X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V
603 603 402 X6S X6S X6S X6S 4.7 UF
10 UF 20% 1 UF 10% 10% 10 UF 20%
C 6.3 V
X6S 1
C738
2 1
C885
2 1
C339
2 C877 C774 C608
805 805 805
C1289
805
C1298
6.3 V
X6S
6.3 V
X6S
6.3 V
X6S C
805 1 2 1 2 1 2 C993 C360 1 2 1 2 402 603 603
1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% C959 C973
10 UF 20% 10 UF 20% 1 UF 10% 22 UF 20% 22 UF 20% 1 2 1 2
C858 6.3 V 6.3 V 6.3 V 22 UF 20% 22 UF 20%
1 2 X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
805 805 805 X6S X6S X6S 6.3 V 6.3 V X6S EMPTY 4.7 UF 10% 10 UF 20%
603 603 402 X6S X6S 805 805 6.3 V 6.3 V
10 UF 20% 805 805 X6S X6S
6.3 V C612 C1290 C1293 603 603
X6S C922 C924 C319 1 2 1 2 1 2
1 2 1 2 1 2 C902 C755
805 1 2 1 2 C963 C361 C951
1 UF 10% 1 2 1 2 22 UF 20% 22 UF 20% 1 2
22 UF 20% 22 UF 20% 22 UF 20% 6.3 V 6.3 V 6.3 V
6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% X6S 22 UF 20% 22 UF 20% X6S EMPTY 10 UF 20%
C857 X6S X6S X6S 6.3 V 6.3 V
1 2 X6S X6S 402 6.3 V 6.3 V 805 805 6.3 V
805 805 805 X6S X6S X6S
603 603 805 805 C1291 C1294 603
10 UF 20% 1 2 1 2
6.3 V C754 C883 C320 C941
X6S 1 2 1 2 1 2 C903 C739 C937 C375 1 2
805 1 2 1 2 1 2 1 2 22 UF 20% 22 UF 20%
6.3 V 6.3 V
22 UF 20% 22 UF 20% 22 UF 20% X6S EMPTY 10 UF 20%
6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% 22 UF 20% 22 UF 20% 805 805 6.3 V
C855 X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V X6S
1 2 X6S X6S X6S X6S
805 805 805 C1292 C1286 603
603 603 805 805 1 2 2 1
10 UF 20% C918
6.3 V 22 UF 20% 22 UF 20% 1 2
X6S C773 C886 C862
1 2 1 2 1 2 C901 C714 C994 6.3 V 6.3 V
B 805 1 2 1 2 1 2 X6S
805
X6S
805
10 UF 20%
6.3 V B
22 UF 20% 22 UF 20% 22 UF 20% X6S
6.3 V 6.3 V 6.3 V 10 UF 20% 10 UF 20% 22 UF 20% C1285
C856 X6S X6S X6S 6.3 V 6.3 V 6.3 V 2 1 603
1 2 X6S X6S X6S
805 805 805
603 603 805 22 UF 20%
10 UF 20% C927
6.3 V 1 2
6.3 V C793 C925 EMPTY
X6S 1 2 1 2 C900 C706 805
805 1 2 1 2 10 UF 20%
6.3 V
22 UF 20% 22 UF 20% X6S
C873 6.3 V 6.3 V 10 UF 20% 10 UF 20% 603
1 2 X6S X6S 6.3 V 6.3 V
805 805 X6S X6S C926
10 UF 20% 603 603 1 2
6.3 V C809 C317 C869 C898
X6S 1 2 1 2 1 2 1 2 10 UF 20%
805 6.3 V
X6S
22 UF 20% 22 UF 20% 10 UF 20% 10 UF 20% 603
C874 6.3 V 6.3 V 6.3 V 6.3 V
1 2 X6S X6S X6S X6S C960
805 805 603 603 1 2
10 UF 20%
6.3 V C705 C340 10 UF 20%
X6S 1 2 1 2
C867 C891 6.3 V
805 1 2 1 2 X6S
22 UF 20% 22 UF 20% 603
C872 6.3 V 6.3 V 10 UF 20% 10 UF 20%
1 2 X6S X6S 6.3 V 6.3 V
805 805 X6S X6S
10 UF 20% 603 603
6.3 V C899 C881
X6S 1 2 1 2
805
10 UF 20% 10 UF 20%
A 1
C318
2 6.3 V
X6S
6.3 V
X6S A
603 603
10 UF 20%
6.3 V
X6S
805
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DECOUPLING
D D
V_MEMIO V_MEMIO V_MEMIO
V_MEMPHY
68 0402 0.22UF 8 0603 10UF 8 0402 1UF 19 0603 10UF
C622 C621 C938 C679 C943 C939
1 2 1 2 1 2 1 2 1 2 1 2 C663 C788 C668 C797
1 2 1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20% 1 UF 10% 10 UF 20% 10 UF 20%
X6S X6S X6S X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 X6S X6S X6S X6S
603 402 603 603
C961 C647 C933 C715 C991 C947
1 2 1 2 1 2 1 2 1 2 1 2 C906 C778 C823 C911
1 2 1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20% 1 UF 10% 10 UF 20% 10 UF 20%
X6S X6S X6S X6S X6S X6S 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 X6S X6S X6S X6S
603 402 603 603
C657 C615 C627 C984 C936 C979 C848
1 2 1 2 1 2 1 2 1 2 1 2 1 2 C669
C988 C631 1 2
1 2 1 2
C 0.22 UF 10%
6.3 V
0.22 UF 10%
6.3 V
0.22 UF 10%
6.3 V
0.22 UF 10%
6.3 V
0.22 UF 10%
6.3 V
0.22 UF 10%
6.3 V
10 UF 20%
6.3 V 10 UF 20% C
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
603 402
C624 C632 C628 C795 C948 C956 C665
1 2 1 2 1 2 1 2 1 2 1 2 1 2 C910
C962 C787 1 2
1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 10 UF 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
603 402
C650 C609 C643 C940 C786 C968 C666
1 2 1 2 1 2 1 2 1 2 1 2 1 2 C909
C613 C644 1 2
1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 10 UF 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
603 402
C617 C641 C689 C779 C889 C919 C708
1 2 1 2 1 2 1 2 1 2 1 2 1 2 C908
C620 C653 1 2
1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 10 UF 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
603 402
C633 C654 C777 C760 C967 C896 C731
B 1 2 1 2 1 2 1 2 1 2 1 2
C677 C630
1 2
1
C907
2 B
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 1 2 1 2 10 UF 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
C920 C932 C871 C660 C904 C978 603 402 C748
1 2 1 2 1 2 1 2 1 2 1 2 1 2 C776
1 2
C895 C625
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 1 2 1 2 10 UF 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S X6S X6S X6S X6S X6S 10 UF 20% 1 UF 10% X6S 6.3 V
402 402 402 402 402 402 6.3 V 6.3 V 603 X6S
X6S X6S 603
C929 C642 C849 C935 603 402 C870
1 2 C616 C674 1 2 1 2 1 2 1 2 C667
1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 10 UF 20%
6.3 V 0.22 UF 10% 0.22 UF 10% 6.3 V 6.3 V 6.3 V 6.3 V 10 UF 20%
X6S 6.3 V 6.3 V X6S X6S X6S X6S 6.3 V
402 X6S X6S 402 402 402 603 X6S
402 402 603
C651 C652 C634 C945 C981
1 2 1 2 C656 1 2 1 2 1 2 C664
1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 10 UF 20%
6.3 V 6.3 V 0.22 UF 10% 6.3 V 6.3 V 6.3 V
X6S X6S 6.3 V X6S X6S X6S 6.3 V
402 402 X6S 402 402 402 X6S
402 603
C646 C661 C890 C905 C954 C944
1 2 1 2 1 2 1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X6S X6S X6S X6S X6S X6S
402 402 402 402 402 402
A C655 C680
A
1 2 1 2
0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V
X6S X6S
402 402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: CHANNEL A0
D D
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D MEMORY: CHANNEL A1 D
M1005505-001 BGA170
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
MEMORY: CHANNEL B0 D
GDDR5_BASE
U7 IC V_MEMIO MIRROR FUNCTION ENABLED WITH PIN J1 HIGH V_MEMIO
DDR5_8GBx32 PINS A4-M2 USE RIGHT SIDE VALUES
2 OF 2 U7 IC
POWER/GROUND DDR5_8GBX32
20 B0_VREFC J14 VREFC_37 1 OF 2
IN A10 J1
1 R111
VREFD_38 MF0/MF1 MF=0/MF=1 2.37 KOHM
U10 VREFD_39 1%
12 B0_MA_A5 H10 BA3_A3/BA1_A5 DQ0/DQ24 A4 B0_DQ24 12 2 CH
G1 H1
IN B0_MA_A2 K11 A2 B0_DQ25
BI 402
VDD_1 VSS_1 12 IN BA2_A4/BA0_A2 DQ1/DQ25 BI 12
L1 VDD_2 VSS_2 K1 12 B0_MA_A3 K10 BA1_A5/BA3_A3 DQ2/DQ26 B4 B0_DQ26 12 B0_VREFC 20
G4 B5
IN B0_MA_A4 H11 B2 B0_DQ27
BI OUT
VDD_3 VSS_3 12 IN BA0_A2/BA2_A4 DQ3/DQ27 BI 12
C L4
C5
VDD_4 VSS_4 G5
L5 B0_MA_A12 J5
DQ4/DQ28 E4
E2
B0_DQ28
B0_DQ29
BI 12 1 R109 1
C167 C
VDD_5 VSS_5 12 IN A12_A13 DQ5/DQ29 BI 12 5.49 KOHM 1 UF
R5 VDD_6 VSS_6 T5 12 IN B0_MA_A1 K5 A11_A6/A9_A1 DQ6/DQ30 F4 B0_DQ30
BI 12 1% 10%
6.3 V
C10 VDD_7 VSS_7 B10 12 B0_MA_A7 H4 A10_A0/A8_A7 DQ7/DQ31 F2 B0_DQ31 12 2 CH 2 X5R
R10 D10
IN B0_MA_A6 H5
BI 402 402
VDD_8 VSS_8 12 IN A9_A1/A11_A6
V_MEMIO D11 VDD_9 VSS_9 G10 12 B0_MA_A0 K4 A8_A7/A10_A0
G11 L10
IN A11 B0_DQ16
VDD_10 VSS_10 DQ8/DQ16 BI 12
L11 VDD_11 VSS_11 P10 12 B0_EDC_0 R2 EDC3/EDC0 DQ9/DQ17 A13 B0_DQ17 12
P11 T10
BI B0_EDC_1 R13 B11 B0_DQ18
BI
VDD_12 VSS_12 12 BI EDC2/EDC1 DQ10/DQ18 BI 12
G14 VDD_13 VSS_13 H14 12 B0_EDC_2 C13 EDC1/EDC2 DQ11/DQ19 B13 B0_DQ19 12
L14 K14
BI B0_EDC_3 C2 E11 B0_DQ20
BI V_MEMIO
VDD_14 VSS_14 12 BI EDC0/EDC3 DQ12/DQ20 BI 12
DQ13/DQ21 E13 B0_DQ21 12
B1 A1 B0_DDBI_0 P2 F11 B0_DQ22
BI
VDDQ_1 VSSQ_1 12 BI DBI3_N/DBI0_N DQ14/DQ22 BI 12
D1 VDDQ_2 VSSQ_2 C1 12 B0_DDBI_1 P13 DBI2_N/DBI1_N DQ15/DQ23 F13 B0_DQ23 12
F1 E1
BI B0_DDBI_2 D13
BI
VDDQ_3 VSSQ_3 12 BI DBI1_N/DBI2_N
M1 VDDQ_4 VSSQ_4 N1 12 B0_DDBI_3 D2 DBI0_N/DBI3_N
P1 R1
BI U11 B0_DQ8
VDDQ_5 VSSQ_5 DQ16/DQ8 BI 12
T1 VDDQ_6 VSSQ_6 U1 12 B0_WCK1_P D4 WCK01_P/WCK23_P DQ17/DQ9 U13 B0_DQ9 12
G2 H2
IN B0_WCK1_N D5 T11 B0_DQ10
BI 1 R439 1 R442
VDDQ_7 VSSQ_7 12 IN WCK01_N/WCK23_N DQ18/DQ10 BI 12
L2 VDDQ_8 VSSQ_8 K2 12 B0_WCK0_P P4 WCK23_P/WCK01_P DQ19/DQ11 T13 B0_DQ11 12 60.4 OHM 60.4 OHM
B3 A3
IN B0_WCK0_N P5 N11 B0_DQ12
BI 1% 1%
VDDQ_9 VSSQ_9 12 IN WCK23_N/WCK01_N DQ20/DQ12 BI 12
D3 VDDQ_10 C3 N13 B0_DQ13 2 CH 2 CH
VSSQ_10 DQ21/DQ13 BI 12 402 402
F3 E3 B0_CLK0_P J12 M11 B0_DQ14
B H3
VDDQ_11
VDDQ_12
VSSQ_11
VSSQ_12 N3
20 12
20 12
IN
IN B0_CLK0_N J11
CK_P
CK_N
DQ22/DQ14
DQ23/DQ15 M13 B0_DQ15
BI
BI
12
12 B
K3 VDDQ_13 VSSQ_13 R3 20 12 B0_CLK0_P
M3 U3 B0_CKE0 J3
IN
VDDQ_14 VSSQ_14 12 IN CKE_N
P3 VDDQ_15 VSSQ_15 C4 DQ24/DQ0 U4 B0_DQ0 12
T3 R4 B0_CAS_N G3 U2 B0_DQ1
BI B0_CLK0_N
VDDQ_16 VSSQ_16 12 IN RAS_N/CAS_N DQ25/DQ1 BI 12 20 12 IN
E5 VDDQ_17 VSSQ_17 F5 12 B0_RAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 B0_DQ2 12
N5 M5
IN T2 B0_DQ3
BI
VDDQ_18 VSSQ_18 DQ27/DQ3 BI 12
E10 VDDQ_19 VSSQ_19 F10 12 B0_CS0_N L12 WE_N/CS_N DQ28/DQ4 N4 B0_DQ4 12
N10 M10
IN B0_WE_N G12 N2 B0_DQ5
BI
VDDQ_20 VSSQ_20 12 IN CS_N/WE_N DQ29/DQ5 BI 12
B12 VDDQ_21 VSSQ_21 C11 DQ30/DQ6 M4 B0_DQ6 12
D12 R11 J13 M2 B0_DQ7
BI
VDDQ_22 VSSQ_22 ZQ DQ31/DQ7 BI 12
F12 VDDQ_23 VSSQ_23 A12 21 20 B_DRAM_RESET_R J2 RESET_N
H12 C12
IN J10 A5
VDDQ_24 VSSQ_24 SEN NC_1
K12 VDDQ_25 VSSQ_25 E12 12 B0_ADBI_N J4 ABI_N NC_2 U5
M12 N12
IN
VDDQ_26 VSSQ_26
P12 VDDQ_27 VSSQ_27 R12 M1005505-001 BGA170
T12 B0_ZQ
VDDQ_28 VSSQ_28 U12
G13 VDDQ_29 VSSQ_29 H13
L13 VDDQ_30 VSSQ_30 K13 1 R102
B14 VDDQ_31 VSSQ_31 A14 120 OHM R448 R437
D14 VDDQ_32 VSSQ_32 C14 1% 12 IN B_DRAM_RESET 1 2 B_DRAM_RESET_C 1 2 B_DRAM_RESET_R
OUT 20 21
F14 VDDQ_33 E14 2 CH 10 OHM 1% 49.9 OHM 1%
VSSQ_33 402 402 CH 402 CH
M14 VDDQ_34 VSSQ_34 N14
P14 VDDQ_35 VSSQ_35 R14
T14 VDDQ_36 VSSQ_36 U14
1 R444 1
4.99 KOHM C572
M1005505-001 BGA170 1% 120 PF
2 CH 5%
A 402 2
50 V
NPO
402
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D MEMORY: CHANNEL B1 D
GDDR5_BASE
U6 IC MIRROR FUNCTION DISABLED WITH PIN J1 LOW
DDR5_8GBx32 PINS A4-M2 USE LEFT SIDE VALUES V_MEMIO
2 OF 2
POWER/GROUND U6 IC
21 B1_VREFC J14 VREFC_37 DDR5_8GBX32
IN A10 VREFD_38 1 OF 2 1 R409
U10 VREFD_39 J1 MF0/MF1 MF=0/MF=1 2.37 KOHM
1%
G1 VDD_1 VSS_1 H1 12 B1_MA_A3 H10 BA3_A3/BA1_A5 DQ0/DQ24 A4 B1_DQ0 12 2 CH
L1 K1 IN B1_MA_A4 K11 A2 B1_DQ1
BI 402
C G4
VDD_2
VDD_3
VSS_2
VSS_3 B5
12
12
IN
IN B1_MA_A5 K10
BA2_A4/BA0_A2
BA1_A5/BA3_A3
DQ1/DQ25
DQ2/DQ26 B4 B1_DQ2
BI
BI
12
12 B1_VREFC
OUT 21 C
L4 VDD_4 VSS_4 G5 12 B1_MA_A2 H11 BA0_A2/BA2_A4 DQ3/DQ27 B2 B1_DQ3 12
C5 L5
IN E4 B1_DQ4
BI 1
VDD_5 VSS_5 DQ4/DQ28 BI 12 1 R402 C537
R5 VDD_6 VSS_6 T5 12 B1_MA_A12 J5 A12_A13 DQ5/DQ29 E2 B1_DQ5 12 5.49 KOHM 1 UF
C10 B10
IN B1_MA_A6 K5 F4 B1_DQ6
BI 1% 10%
VDD_7 VSS_7 12 IN A11_A6/A9_A1 DQ6/DQ30 BI 12
R10 D10 B1_MA_A0 H4 F2 B1_DQ7 6.3 V
VDD_8 VSS_8 12 IN A10_A0/A8_A7 DQ7/DQ31 BI 12 2 CH 2 X5R
V_MEMIO D11 VDD_9 VSS_9 G10 12 IN B1_MA_A1 H5 A9_A1/A11_A6 402 402
G11 VDD_10 VSS_10 L10 12 B1_MA_A7 K4 A8_A7/A10_A0
L11 P10
IN A11 B1_DQ8
VDD_11 VSS_11 DQ8/DQ16 BI 12
P11 VDD_12 VSS_12 T10 12 B1_EDC_3 R2 EDC3/EDC0 DQ9/DQ17 A13 B1_DQ9 12
G14 H14
BI B1_EDC_2 R13 B11 B1_DQ10
BI
VDD_13 VSS_13 12 BI EDC2/EDC1 DQ10/DQ18 BI 12
L14 VDD_14 VSS_14 K14 12 B1_EDC_1 C13 EDC1/EDC2 DQ11/DQ19 B13 B1_DQ11 12
BI B1_EDC_0 C2 E11 B1_DQ12
BI V_MEMIO
12 BI EDC0/EDC3 DQ12/DQ20 BI 12
B1 VDDQ_1 VSSQ_1 A1 DQ13/DQ21 E13 B1_DQ13 12
D1 C1 B1_DDBI_3 P2 F11 B1_DQ14
BI
VDDQ_2 VSSQ_2 12 BI DBI3_N/DBI0_N DQ14/DQ22 BI 12
F1 VDDQ_3 VSSQ_3 E1 12 B1_DDBI_2 P13 DBI2_N/DBI1_N DQ15/DQ23 F13 B1_DQ15 12
M1 N1
BI B1_DDBI_1 D13
BI
VDDQ_4 VSSQ_4 12 BI DBI1_N/DBI2_N
P1 VDDQ_5 VSSQ_5 R1 12 B1_DDBI_0 D2 DBI0_N/DBI3_N
T1 U1
BI U11 B1_DQ16
VDDQ_6 VSSQ_6 DQ16/DQ8 BI 12
G2 VDDQ_7 VSSQ_7 H2 12 B1_WCK0_P D4 WCK01_P/WCK23_P DQ17/DQ9 U13 B1_DQ17 12
L2 K2
IN B1_WCK0_N D5 T11 B1_DQ18
BI 1 R414 1 R415
VDDQ_8 VSSQ_8 12 IN WCK01_N/WCK23_N DQ18/DQ10 BI 12
B3 VDDQ_9 VSSQ_9 A3 12 B1_WCK1_P P4 WCK23_P/WCK01_P DQ19/DQ11 T13 B1_DQ19 12 60.4 OHM 60.4 OHM
IN BI 1% 1%
B D3
F3
VDDQ_10 VSSQ_10 C3
E3
12 IN B1_WCK1_N P5 WCK23_N/WCK01_N DQ20/DQ12 N11
N13
B1_DQ20
B1_DQ21
BI 12
2 CH 2 CH B
VDDQ_11 VSSQ_11 DQ21/DQ13 BI 12 402 402
H3 VDDQ_12 VSSQ_12 N3 21 12 B1_CLK0_P J12 CK_P DQ22/DQ14 M11 B1_DQ22 12
K3 R3
IN B1_CLK0_N J11 M13 B1_DQ23
BI
VDDQ_13 VSSQ_13 21 12 IN CK_N DQ23/DQ15 BI 12
M3 VDDQ_14 VSSQ_14 U3 21 12 B1_CLK0_P
P3 C4 B1_CKE0 J3
IN
VDDQ_15 VSSQ_15 12 IN CKE_N
T3 VDDQ_16 VSSQ_16 R4 DQ24/DQ0 U4 B1_DQ24 12
E5 F5 B1_RAS_N G3 U2 B1_DQ25
BI B1_CLK0_N
VDDQ_17 VSSQ_17 12 IN RAS_N/CAS_N DQ25/DQ1 BI 12 21 12 IN
N5 VDDQ_18 VSSQ_18 M5 12 B1_CAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 B1_DQ26 12
E10 F10
IN T2 B1_DQ27
BI
VDDQ_19 VSSQ_19 DQ27/DQ3 BI 12
N10 VDDQ_20 VSSQ_20 M10 12 B1_WE_N L12 WE_N/CS_N DQ28/DQ4 N4 B1_DQ28 12
B12 C11
IN B1_CS0_N G12 N2 B1_DQ29
BI
VDDQ_21 VSSQ_21 12 IN CS_N/WE_N DQ29/DQ5 BI 12
D12 VDDQ_22 VSSQ_22 R11 DQ30/DQ6 M4 B1_DQ30 12
F12 A12 J13 M2 B1_DQ31
BI
VDDQ_23 VSSQ_23 ZQ DQ31/DQ7 BI 12
H12 VDDQ_24 VSSQ_24 C12 20 B_DRAM_RESET_R J2 RESET_N
K12 E12
IN J10 A5
VDDQ_25 VSSQ_25 SEN NC_1
M12 VDDQ_26 VSSQ_26 N12 12 B1_ADBI_N J4 ABI_N NC_2 U5
P12 R12
IN
VDDQ_27 VSSQ_27
T12 VDDQ_28 VSSQ_28 U12 M1005505-001 BGA170
G13 B1_ZQ
VDDQ_29 VSSQ_29 H13
L13 VDDQ_30 VSSQ_30 K13
B14 VDDQ_31 VSSQ_31 A14
D14 C14
R399
VDDQ_32 VSSQ_32 120 OHM
F14 VDDQ_33 VSSQ_33 E14 1%
M14 VDDQ_34 VSSQ_34 N14 CH
P14 VDDQ_35 VSSQ_35 R14 402
T14 VDDQ_36 VSSQ_36 U14
M1005505-001 BGA170 A
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEMIO
CHANNEL A/B DECOUPLING
1 1 1 1
C516 C514 C510 C529
22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805
V_MEMIO V_MEMIO
V_MEMIO V_MEMIO
B B
V_MEMIO V_MEMIO
V_MEMIO V_MEMIO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C101 C566 C121 C73 C71 C86 C562 C555 C546 C560 C526 C518 C565 C527 C515 C561
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
A 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R
A
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
NOTE: ADDITIONAL MEMORY DECOUPLING ON PAGE 33 MICROSOFT PROJECT NAME PAGE CSA
PAGE
FAB VER
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: CHANNEL C0
D D
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: CHANNEL C1
D D
GDDR5_BASE
U9 IC
DDR5_8GBx32 MIRROR FUNCTION ENABLED WITH PIN J1 HIGH
2 OF 2 V_MEMIO
PINS A4-M2 USE RIGHT SIDE VALUES
POWER/GROUND
24 IN
C1_VREFC J14 VREFC_37 U9 IC
A10 VREFD_38 DDR5_8GBX32
U10 VREFD_39 1 OF 2
J1 MF0/MF1 MF=0/MF=1
G1 VDD_1 VSS_1 H1 V_MEMIO
L1 VDD_2 VSS_2 K1 11 C1_MA_A5 H10 BA3_A3/BA1_A5 DQ0/DQ24 A4 C1_DQ24 11
G4 B5
IN C1_MA_A2 K11 A2 C1_DQ25
BI
VDD_3 VSS_3 11 IN BA2_A4/BA0_A2 DQ1/DQ25 BI 11
L4 VDD_4 VSS_4 G5 11 C1_MA_A3 K10 BA1_A5/BA3_A3 DQ2/DQ26 B4 C1_DQ26 11
C5 L5
IN C1_MA_A4 H11 B2 C1_DQ27
BI 1 R165
VDD_5 VSS_5 11 IN BA0_A2/BA2_A4 DQ3/DQ27 BI 11
R5 VDD_6 VSS_6 T5 DQ4/DQ28 E4 C1_DQ28 11
2.37 KOHM
C10 B10 C1_MA_A12 J5 E2 C1_DQ29
BI 1%
VDD_7 VSS_7 11 IN A12_A13 DQ5/DQ29 BI 11
2 CH
C R10
D11
VDD_8 VSS_8 D10
G10
11 IN C1_MA_A1
C1_MA_A7
K5
H4
A11_A6/A9_A1 DQ6/DQ30 F4
F2
C1_DQ30
C1_DQ31
BI 11 402 C
V_MEMIO VDD_9 VSS_9 11 IN A10_A0/A8_A7 DQ7/DQ31 BI 11 C1_VREFC
G11 L10 C1_MA_A6 H5 OUT 24
VDD_10 VSS_10 11 IN A9_A1/A11_A6
L11 VDD_11 VSS_11 P10 11 C1_MA_A0 K4 A8_A7/A10_A0
P11 T10
IN A11 C1_DQ16 1 R164 1
C276
VDD_12 VSS_12 DQ8/DQ16 BI 11
G14 VDD_13 VSS_13 H14 11 C1_EDC_0 R2 EDC3/EDC0 DQ9/DQ17 A13 C1_DQ17 11
5.49 KOHM 1 UF
L14 K14
BI C1_EDC_1 R13 B11 C1_DQ18
BI 1% 10%
VDD_14 VSS_14 EDC2/EDC1 DQ10/DQ18
11 BI C1_EDC_2 C13 B13 C1_DQ19
BI 11
2 CH 2 6.3
X5R
V
11 BI EDC1/EDC2 DQ11/DQ19 BI 11 402 402
B1 VDDQ_1 VSSQ_1 A1 11 C1_EDC_3 C2 EDC0/EDC3 DQ12/DQ20 E11 C1_DQ20 11
D1 C1
BI E13 C1_DQ21
BI
VDDQ_2 VSSQ_2 DQ13/DQ21 BI 11
F1 VDDQ_3 VSSQ_3 E1 11 C1_DDBI_0 P2 DBI3_N/DBI0_N DQ14/DQ22 F11 C1_DQ22 11
M1 N1
BI C1_DDBI_1 P13 F13 C1_DQ23
BI
VDDQ_4 VSSQ_4 11 BI DBI2_N/DBI1_N DQ15/DQ23 BI 11
P1 VDDQ_5 VSSQ_5 R1 11 C1_DDBI_2 D13 DBI1_N/DBI2_N
T1 U1
BI C1_DDBI_3 D2
VDDQ_6 VSSQ_6 11 BI DBI0_N/DBI3_N V_MEMIO
G2 VDDQ_7 VSSQ_7 H2 DQ16/DQ8 U11 C1_DQ8 11
L2 K2 C1_WCK1_P D4 U13 C1_DQ9
BI
VDDQ_8 VSSQ_8 11 IN WCK01_P/WCK23_P DQ17/DQ9 BI 11
B3 VDDQ_9 VSSQ_9 A3 11 C1_WCK1_N D5 WCK01_N/WCK23_N DQ18/DQ10 T11 C1_DQ10 11
D3 C3
IN C1_WCK0_P P4 T13 C1_DQ11
BI
VDDQ_10 VSSQ_10 11 IN WCK23_P/WCK01_P DQ19/DQ11 BI 11
F3 VDDQ_11 VSSQ_11 E3 11 C1_WCK0_N P5 WCK23_N/WCK01_N DQ20/DQ12 N11 C1_DQ12 11
H3 N3
IN N13 C1_DQ13
BI
VDDQ_12 VSSQ_12 DQ21/DQ13 BI 11
K3 VDDQ_13 VSSQ_13 R3 24 11 C1_CLK0_P J12 CK_P DQ22/DQ14 M11 C1_DQ14 11
M3 U3
IN C1_CLK0_N J11 M13 C1_DQ15
BI
VDDQ_14 VSSQ_14 24 11 IN CK_N DQ23/DQ15 BI 11 1 R523
P3 C4 1 R519
B T3
VDDQ_15
VDDQ_16
VSSQ_15
VSSQ_16 R4 11 IN C1_CKE0 J3 CKE_N
60.4 OHM
1% 60.4 OHM
1% B
E5 VDDQ_17 VSSQ_17 F5 DQ24/DQ0 U4 C1_DQ0 11 2 CH
N5 M5 C1_CAS_N G3 U2 C1_DQ1
BI 402 2 CH
VDDQ_18 VSSQ_18 11 IN RAS_N/CAS_N DQ25/DQ1 BI 11 402
E10 VDDQ_19 VSSQ_19 F10 11 C1_RAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 C1_DQ2 11
N10 M10
IN T2 C1_DQ3
BI
VDDQ_20 VSSQ_20 DQ27/DQ3 BI 11 C1_CLK0_P
B12 C11 C1_CS0_N L12 N4 C1_DQ4 24 11 IN
VDDQ_21 VSSQ_21 11 IN WE_N/CS_N DQ28/DQ4 BI 11
D12 VDDQ_22 VSSQ_22 R11 11 C1_WE_N G12 CS_N/WE_N DQ29/DQ5 N2 C1_DQ5 11
F12 A12
IN M4 C1_DQ6
BI
VDDQ_23 VSSQ_23 DQ30/DQ6 BI 11 C1_CLK0_N
H12 C12 J13 M2 C1_DQ7 24 11 IN
VDDQ_24 VSSQ_24 ZQ DQ31/DQ7 BI 11
K12 VDDQ_25 VSSQ_25 E12 23 C_DRAM_RESET_R J2 RESET_N
M12 N12
IN J10 A5
VDDQ_26 VSSQ_26 SEN NC_1
P12 VDDQ_27 VSSQ_27 R12 11 C1_ADBI_N J4 ABI_N NC_2 U5
T12 U12
IN
VDDQ_28 VSSQ_28
G13 VDDQ_29 VSSQ_29 H13 M1005505-001 BGA170
L13 C1_ZQ
VDDQ_30 VSSQ_30 K13
B14 VDDQ_31 VSSQ_31 A14
D14 VDDQ_32 VSSQ_32 C14
F14 E14
1 R163
VDDQ_33 VSSQ_33 120 OHM
M14 VDDQ_34 VSSQ_34 N14 1%
P14 VDDQ_35 VSSQ_35 R14 2 CH
T14 VDDQ_36 VSSQ_36 U14 402
M1005505-001 BGA170
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: CHANNEL D0
D D
GDDR5_BASE
MIRROR FUNCTION ENABLED WITH PIN J1 HIGH
U11 IC PINS A4-M2 USE RIGHT SIDE VALUES
DDR5_8GBx32 V_MEMIO
2 OF 2
POWER/GROUND U11 IC V_MEMIO
25
D0_VREFC J14 VREFC_37 DDR5_8GBX32
IN A10 VREFD_38 1 OF 2
U10 VREFD_39 J1 MF0/MF1 MF=0/MF=1
G1 H1 D0_MA_A5 H10 A4 D0_DQ24
1 R224
VDD_1 VSS_1 10 IN BA3_A3/BA1_A5 DQ0/DQ24 BI 10 2.37 KOHM
L1 VDD_2 VSS_2 K1 10 IN D0_MA_A2 K11 BA2_A4/BA0_A2 DQ1/DQ25 A2 D0_DQ25
BI 10 1%
G4 VDD_3 VSS_3 B5 10 D0_MA_A3 K10 BA1_A5/BA3_A3 DQ2/DQ26 B4 D0_DQ26 10 2 CH
L4 G5
IN D0_MA_A4 H11 B2 D0_DQ27
BI 402
VDD_4 VSS_4 10 IN BA0_A2/BA2_A4 DQ3/DQ27 BI 10 D0_VREFC
C5 L5 E4 D0_DQ28 OUT 25
VDD_5 VSS_5 DQ4/DQ28 BI 10
R5 VDD_6 VSS_6 T5 10 D0_MA_A12 J5 A12_A13 DQ5/DQ29 E2 D0_DQ29 10
C10 B10
IN D0_MA_A1 K5 F4 D0_DQ30
BI 1 R223 C3871
VDD_7 VSS_7 10 IN A11_A6/A9_A1 DQ6/DQ30 BI 10
R10 D10 D0_MA_A7 H4 F2 D0_DQ31 5.49 KOHM 1 UF
C V_MEMIO D11
VDD_8
VDD_9
VSS_8
VSS_9 G10
10
10
IN
IN D0_MA_A6 H5
A10_A0/A8_A7
A9_A1/A11_A6
DQ7/DQ31 BI 10
1% 10%
6.3 V C
G11 VDD_10 L10 D0_MA_A0 K4 2 CH 2 X5R
VSS_10 10 IN A8_A7/A10_A0 402 402
L11 VDD_11 VSS_11 P10 DQ8/DQ16 A11 D0_DQ16 10
P11 T10 D0_EDC_0 R2 A13 D0_DQ17
BI
VDD_12 VSS_12 10 BI EDC3/EDC0 DQ9/DQ17 BI 10
G14 VDD_13 VSS_13 H14 10 D0_EDC_1 R13 EDC2/EDC1 DQ10/DQ18 B11 D0_DQ18 10
L14 K14
BI D0_EDC_2 C13 B13 D0_DQ19
BI
VDD_14 VSS_14 10 BI EDC1/EDC2 DQ11/DQ19 BI 10
10 D0_EDC_3 C2 EDC0/EDC3 DQ12/DQ20 E11 D0_DQ20 10
B1 A1
BI E13 D0_DQ21
BI
VDDQ_1 VSSQ_1 DQ13/DQ21 BI 10 V_MEMIO
D1 VDDQ_2 VSSQ_2 C1 10 D0_DDBI_0 P2 DBI3_N/DBI0_N DQ14/DQ22 F11 D0_DQ22 10
F1 E1
BI D0_DDBI_1 P13 F13 D0_DQ23
BI
VDDQ_3 VSSQ_3 10 BI DBI2_N/DBI1_N DQ15/DQ23 BI 10
M1 VDDQ_4 VSSQ_4 N1 10 D0_DDBI_2 D13 DBI1_N/DBI2_N
P1 R1
BI D0_DDBI_3 D2
VDDQ_5 VSSQ_5 10 BI DBI0_N/DBI3_N
T1 VDDQ_6 VSSQ_6 U1 DQ16/DQ8 U11 D0_DQ8 10
G2 H2 D0_WCK1_P D4 U13 D0_DQ9
BI
VDDQ_7 VSSQ_7 10 IN WCK01_P/WCK23_P DQ17/DQ9 BI 10
L2 VDDQ_8 VSSQ_8 K2 10 D0_WCK1_N D5 WCK01_N/WCK23_N DQ18/DQ10 T11 D0_DQ10 10
B3 A3
IN D0_WCK0_P P4 T13 D0_DQ11
BI
VDDQ_9 VSSQ_9 10 IN WCK23_P/WCK01_P DQ19/DQ11 BI 10 1 R562 1 R561
D3 VDDQ_10 VSSQ_10 C3 10 D0_WCK0_N P5 WCK23_N/WCK01_N DQ20/DQ12 N11 D0_DQ12 10 60.4 OHM 60.4 OHM
F3 E3
IN N13 D0_DQ13
BI 1% 1%
VDDQ_11 VSSQ_11 DQ21/DQ13 BI 10
H3 VDDQ_12 VSSQ_12 N3 25 10 D0_CLK0_P J12 CK_P DQ22/DQ14 M11 D0_DQ14 10 2 CH 2 CH
K3 R3
IN D0_CLK0_N J11 M13 D0_DQ15
BI 402 402
VDDQ_13 VSSQ_13 25 10 IN CK_N DQ23/DQ15 BI 10
M3 VDDQ_14 VSSQ_14 U3
P3 VDDQ_15 VSSQ_15 C4 10 D0_CKE0 J3 CKE_N
IN D0_CLK0_P
B T3
E5
VDDQ_16 VSSQ_16 R4
F5 D0_CAS_N G3
DQ24/DQ0 U4
U2
D0_DQ0
D0_DQ1
BI 10
25 10 IN
B
VDDQ_17 VSSQ_17 10 IN RAS_N/CAS_N DQ25/DQ1 BI 10
N5 VDDQ_18 VSSQ_18 M5 10 D0_RAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 D0_DQ2 10
E10 F10
IN T2 D0_DQ3
BI 25 10 IN D0_CLK0_N
VDDQ_19 VSSQ_19 DQ27/DQ3 BI 10
N10 VDDQ_20 VSSQ_20 M10 10 D0_CS0_N L12 WE_N/CS_N DQ28/DQ4 N4 D0_DQ4 10
B12 C11
IN D0_WE_N G12 N2 D0_DQ5
BI
VDDQ_21 VSSQ_21 10 IN CS_N/WE_N DQ29/DQ5 BI 10
D12 VDDQ_22 VSSQ_22 R11 DQ30/DQ6 M4 D0_DQ6 10
F12 A12 J13 M2 D0_DQ7
BI
VDDQ_23 VSSQ_23 ZQ DQ31/DQ7 BI 10
H12 VDDQ_24 VSSQ_24 C12 26 25 D_DRAM_RESET_R J2 RESET_N
K12 E12
IN J10 A5
VDDQ_25 VSSQ_25 SEN NC_1
M12 VDDQ_26 VSSQ_26 N12 10 D0_ADBI_N J4 ABI_N NC_2 U5
P12 R12
IN
VDDQ_27 VSSQ_27
T12 VDDQ_28 VSSQ_28 U12 M1005505-001 BGA170
G13 D0_ZQ
VDDQ_29 VSSQ_29 H13
L13 VDDQ_30 VSSQ_30 K13
B14 VDDQ_31 VSSQ_31 A14
D14 C14
1 R222
VDDQ_32 VSSQ_32 120 OHM R551 R553
F14 VDDQ_33 VSSQ_33 E14 1% 10 IN D_DRAM_RESET 1 2 D_DRAM_RESET_C 1 2 D_DRAM_RESET_R
OUT 25 26
M14 VDDQ_34 VSSQ_34 N14 2 CH 10 OHM 1% 49.9 OHM 1%
P14 VDDQ_35 VSSQ_35 R14 402 402 CH 402 CH
T14 VDDQ_36 VSSQ_36 U14
1 R554
M1005505-001 BGA170 4.99 KOHM 1
1% C894
2 CH 120 PF
5%
402 50 V
2 NPO
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
MEMORY: CHANNEL D1
M1005505-001 BGA170
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
MEMORY: CHANNEL C/D DECOUPLING D
V_MEMIO CHANNEL C/D DECOUPLING
1 1 1
C598 C683 1
C875 C999
22 UF 22 UF 22 UF
20% 20% 22 UF 20%
6.3 V 6.3 V 20% 6.3 V
2 X5R 2 X5R 6.3 V 2 X5R
805 805 2 X5R 805
805
V_MEMIO V_MEMIO
V_MEMIO V_MEMIO
MEMORY CHANNEL C1 DECOUPLING MEMORY CHANNEL C1 DECOUPLING
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C273 C636 C272 C635 C756 C227 C228 C229 C729 C676 C681 C711 C709 C707 C682 C757
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
B 2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402
2 6.3 V
X5R
402 B
V_MEMIO V_MEMIO
MEMORY CHANNEL D0 DECOUPLING MEMORY CHANNEL D0 DECOUPLING
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1002 C975 C996 C1007 C1008 C1004 C976 C995 C997 C385 C355 C356 C1003 C1006 C384 C354
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
V_MEMIO V_MEMIO
NOTE: ADDITIONAL MEMORY DECOUPLING ON PAGE 33 MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 27/82 27/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D MEMORY: CHANNEL E0 D
GDDR5_BASE
U12 IC MIRROR FUNCTION DISABLED WITH PIN J1 LOW
DDR5_8GBx32 PINS A4-M2 USE LEFT SIDE VALUES
2 OF 2 V_MEMIO
POWER/GROUND
28 IN E0_VREFC J14 VREFC_37 U12 IC
A10 VREFD_38 DDR5_8GBX32
U10 VREFD_39 1 OF 2
J1
1 R236
MF0/MF1 MF=0/MF=1 2.37 KOHM
G1 VDD_1 VSS_1 H1 1%
L1 VDD_2 VSS_2 K1 9 E0_MA_A3 H10 BA3_A3/BA1_A5 DQ0/DQ24 A4 E0_DQ0 9 2 CH
G4 B5 IN E0_MA_A4 K11 A2 E0_DQ1
BI 402
C L4
VDD_3
VDD_4
VSS_3
VSS_4 G5
9
9
IN
IN E0_MA_A5 K10
BA2_A4/BA0_A2
BA1_A5/BA3_A3
DQ1/DQ25
DQ2/DQ26 B4 E0_DQ2
BI
BI
9
9 E0_VREFC OUT 28 C
C5 VDD_5 VSS_5 L5 9 E0_MA_A2 H11 BA0_A2/BA2_A4 DQ3/DQ27 B2 E0_DQ3 9
R5 T5
IN E4 E0_DQ4
BI 1
VDD_6 VSS_6 DQ4/DQ28 BI 9 1 R238 C388
C10 VDD_7 VSS_7 B10 9 E0_MA_A12 J5 A12_A13 DQ5/DQ29 E2 E0_DQ5 9 5.49 KOHM 1 UF
R10 D10
IN E0_MA_A6 K5 F4 E0_DQ6
BI 1% 10%
VDD_8 VSS_8 9 IN A11_A6/A9_A1 DQ6/DQ30 BI 9
D11 G10 E0_MA_A0 H4 F2 E0_DQ7 6.3 V
V_MEMIO VDD_9 VSS_9 9 IN A10_A0/A8_A7 DQ7/DQ31 BI 9 2 CH 2 X5R
G11 VDD_10 VSS_10 L10 9 IN E0_MA_A1 H5 A9_A1/A11_A6 402 402
L11 VDD_11 VSS_11 P10 9 E0_MA_A7 K4 A8_A7/A10_A0
P11 T10
IN A11 E0_DQ8
VDD_12 VSS_12 DQ8/DQ16 BI 9
G14 VDD_13 VSS_13 H14 9 E0_EDC_3 R2 EDC3/EDC0 DQ9/DQ17 A13 E0_DQ9 9
L14 K14
BI E0_EDC_2 R13 B11 E0_DQ10
BI
VDD_14 VSS_14 9 BI EDC2/EDC1 DQ10/DQ18 BI 9
9 E0_EDC_1 C13 EDC1/EDC2 DQ11/DQ19 B13 E0_DQ11 9
B1 A1
BI E0_EDC_0 C2 E11 E0_DQ12
BI V_MEMIO
VDDQ_1 VSSQ_1 9 BI EDC0/EDC3 DQ12/DQ20 BI 9
D1 VDDQ_2 VSSQ_2 C1 DQ13/DQ21 E13 E0_DQ13 9
F1 E1 E0_DDBI_3 P2 F11 E0_DQ14
BI
VDDQ_3 VSSQ_3 9 BI DBI3_N/DBI0_N DQ14/DQ22 BI 9
M1 VDDQ_4 VSSQ_4 N1 9 E0_DDBI_2 P13 DBI2_N/DBI1_N DQ15/DQ23 F13 E0_DQ15 9
P1 R1
BI E0_DDBI_1 D13
BI
VDDQ_5 VSSQ_5 9 BI DBI1_N/DBI2_N
T1 VDDQ_6 VSSQ_6 U1 9 E0_DDBI_0 D2 DBI0_N/DBI3_N
G2 H2
BI U11 E0_DQ16
VDDQ_7 VSSQ_7 DQ16/DQ8 BI 9
L2 VDDQ_8 VSSQ_8 K2 9 E0_WCK0_P D4 WCK01_P/WCK23_P DQ17/DQ9 U13 E0_DQ17 9
B3 A3
IN E0_WCK0_N D5 T11 E0_DQ18
BI 1 R569 1 R573
VDDQ_9 VSSQ_9 9 IN WCK01_N/WCK23_N DQ18/DQ10 BI 9
D3 VDDQ_10 VSSQ_10 C3 9 E0_WCK1_P P4 WCK23_P/WCK01_P DQ19/DQ11 T13 E0_DQ19 9
60.4 OHM 60.4 OHM
IN BI 1% 1%
B F3
H3
VDDQ_11 VSSQ_11 E3
N3
9 IN E0_WCK1_N P5 WCK23_N/WCK01_N DQ20/DQ12 N11
N13
E0_DQ20
E0_DQ21
BI 9
2 CH 2 CH B
VDDQ_12 VSSQ_12 DQ21/DQ13 BI 9 402 402
K3 VDDQ_13 VSSQ_13 R3 28 9 E0_CLK0_P J12 CK_P DQ22/DQ14 M11 E0_DQ22 9
M3 U3
IN E0_CLK0_N J11 M13 E0_DQ23
BI
VDDQ_14 VSSQ_14 28 9 IN CK_N DQ23/DQ15 BI 9
P3 VDDQ_15 VSSQ_15 C4 28 9 E0_CLK0_P
T3 R4 E0_CKE0 J3
IN
VDDQ_16 VSSQ_16 9 IN CKE_N
E5 VDDQ_17 VSSQ_17 F5 DQ24/DQ0 U4 E0_DQ24 9
N5 M5 E0_RAS_N G3 U2 E0_DQ25
BI E0_CLK0_N
VDDQ_18 VSSQ_18 9 IN RAS_N/CAS_N DQ25/DQ1 BI 9 28 9 IN
E10 VDDQ_19 VSSQ_19 F10 9 E0_CAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 E0_DQ26 9
N10 M10
IN T2 E0_DQ27
BI
VDDQ_20 VSSQ_20 DQ27/DQ3 BI 9
B12 VDDQ_21 VSSQ_21 C11 9 E0_WE_N L12 WE_N/CS_N DQ28/DQ4 N4 E0_DQ28 9
D12 R11
IN E0_CS0_N G12 N2 E0_DQ29
BI
VDDQ_22 VSSQ_22 9 IN CS_N/WE_N DQ29/DQ5 BI 9
F12 VDDQ_23 VSSQ_23 A12 DQ30/DQ6 M4 E0_DQ30 9
H12 C12 J13 M2 E0_DQ31
BI
VDDQ_24 VSSQ_24 ZQ DQ31/DQ7 BI 9
K12 VDDQ_25 VSSQ_25 E12 29 28 E_DRAM_RESET_R J2 RESET_N
M12 N12
IN J10 A5
VDDQ_26 VSSQ_26 SEN NC_1
P12 VDDQ_27 VSSQ_27 R12 9 E0_ADBI_N J4 ABI_N NC_2 U5
T12 U12
IN
VDDQ_28 VSSQ_28
G13 VDDQ_29 VSSQ_29 H13 M1005505-001 BGA170
L13 E0_ZQ
VDDQ_30 VSSQ_30 K13
B14 VDDQ_31 VSSQ_31 A14 R570 R575
9 E_DRAM_RESET 1 2 E_DRAM_RESET_C 1 2 E_DRAM_RESET_R 28 29
D14 VDDQ_32 VSSQ_32 C14 1 R242 IN OUT
F14 VDDQ_33 VSSQ_33 E14 120 OHM 10 OHM 1% 49.9 OHM 1%
M14 VDDQ_34 VSSQ_34 N14 1% 402 CH 402 CH
P14 VDDQ_35 R14 2 CH
VSSQ_35 402
T14 VDDQ_36 VSSQ_36 U14
1 R572 1
4.99 KOHM C1025
M1005505-001 BGA170 1% 120 PF
2 CH 5%
A 402 2
50 V
NPO
A
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D MEMORY: CHANNEL E1 D
GDDR5_BASE
U13 IC
DDR5_8GBx32
2 OF 2
POWER/GROUND
29 E1_VREFC J14 VREFC_37 MIRROR FUNCTION ENABLED WITH PIN J1 HIGH
IN A10 VREFD_38 PINS A4-M2 USE RIGHT SIDE VALUES
U10 VREFD_39 V_MEMIO
G1 H1
U13 IC
VDD_1 VSS_1
L1 VDD_2 VSS_2 K1 DDR5_8GBX32
G4 VDD_3 VSS_3 B5 1 OF 2 V_MEMIO
L4 G5 J1 MF0/MF1 MF=0/MF=1
C C5
VDD_4
VDD_5
VSS_4
VSS_5 L5
E1_MA_A5 H10 A4 E1_DQ24 C
R5 VDD_6 T5 9 IN BA3_A3/BA1_A5 DQ0/DQ24 BI 9
VSS_6 E1_MA_A2 K11 A2 E1_DQ25
C10 VDD_7 B10 9 IN BA2_A4/BA0_A2 DQ1/DQ25 BI 9 1 R585
VSS_7 E1_MA_A3 K10 B4 E1_DQ26
R10 VDD_8 VSS_8 D10 9 IN BA1_A5/BA3_A3 DQ2/DQ26 BI 9 2.37 KOHM
D11 VDD_9 VSS_9 G10 9 IN E1_MA_A4 H11 BA0_A2/BA2_A4 DQ3/DQ27 B2 E1_DQ27
BI 9 1%
V_MEMIO G11 L10 DQ4/DQ28 E4 E1_DQ28
BI 9 2 CH
VDD_10 VSS_10 E1_MA_A12 J5 E2 E1_DQ29 402
L11 VDD_11 P10 9 IN A12_A13 DQ5/DQ29 BI 9
VSS_11 E1_MA_A1 K5 F4 E1_DQ30 E1_VREFC
P11 VDD_12 T10 9 IN A11_A6/A9_A1 DQ6/DQ30 BI 9 OUT 29
VSS_12 E1_MA_A7 H4 F2 E1_DQ31
G14 VDD_13 H14 9 IN A10_A0/A8_A7 DQ7/DQ31 BI 9
VSS_13 E1_MA_A6 H5 1
L14 VDD_14 K14 9 IN A9_A1/A11_A6 1 R587 C1050
VSS_14 E1_MA_A0 K4
9 IN A8_A7/A10_A0 5.49 KOHM 1 UF
B1 VDDQ_1 VSSQ_1 A1 DQ8/DQ16 A11 E1_DQ16
BI 9 1% 10%
6.3 V
9 E1_EDC_0 R2 EDC3/EDC0 DQ9/DQ17 A13 E1_DQ17 9 2 CH 2 X5R
D1 VDDQ_2 VSSQ_2 C1 BI E1_EDC_1 R13 B11 E1_DQ18
BI 402 402
F1 VDDQ_3 E1 9 BI EDC2/EDC1 DQ10/DQ18 BI 9
VSSQ_3 E1_EDC_2 C13 B13 E1_DQ19
M1 VDDQ_4 N1 9 BI EDC1/EDC2 DQ11/DQ19 BI 9
VSSQ_4 E1_EDC_3 C2 E11 E1_DQ20
P1 VDDQ_5 R1 9 BI EDC0/EDC3 DQ12/DQ20 BI 9
VSSQ_5 E13 E1_DQ21
T1 VDDQ_6 U1 DQ13/DQ21 BI 9
VSSQ_6 E1_DDBI_0 P2 F11 E1_DQ22
G2 VDDQ_7 H2 9 BI DBI3_N/DBI0_N DQ14/DQ22 BI 9
VSSQ_7 E1_DDBI_1 P13 F13 E1_DQ23
L2 VDDQ_8 K2 9 BI DBI2_N/DBI1_N DQ15/DQ23 BI 9
VSSQ_8 E1_DDBI_2 D13 V_MEMIO
B3 VDDQ_9 A3 9 BI DBI1_N/DBI2_N
VSSQ_9 E1_DDBI_3 D2
D3 VDDQ_10 C3 9 BI DBI0_N/DBI3_N
VSSQ_10 U11 E1_DQ8
F3 VDDQ_11 E3 DQ16/DQ8 BI 9
VSSQ_11 E1_WCK1_P D4 U13 E1_DQ9
B H3
K3
VDDQ_12 VSSQ_12 N3
R3
9
9
IN
IN E1_WCK1_N D5
WCK01_P/WCK23_P
WCK01_N/WCK23_N
DQ17/DQ9
DQ18/DQ10 T11 E1_DQ10
BI
BI
9
9 B
VDDQ_13 VSSQ_13 E1_WCK0_P P4 T13 E1_DQ11
M3 VDDQ_14 U3 9 IN WCK23_P/WCK01_P DQ19/DQ11 BI 9
VSSQ_14 E1_WCK0_N P5 N11 E1_DQ12
P3 VDDQ_15 C4 9 IN WCK23_N/WCK01_N DQ20/DQ12 BI 9
VSSQ_15 N13 E1_DQ13
T3 VDDQ_16 R4 DQ21/DQ13 BI 9
VSSQ_16 E1_CLK0_P J12 M11 E1_DQ14
E5 F5 29 9 IN CK_P DQ22/DQ14 BI 9
VDDQ_17 VSSQ_17 E1_CLK0_N J11 M13 E1_DQ15 1 R583 1 R586
N5 M5 29 9 IN CK_N DQ23/DQ15 BI 9
VDDQ_18 VSSQ_18 60.4 OHM 60.4 OHM
E10 VDDQ_19 VSSQ_19 F10
9 E1_CKE0 J3 CKE_N
1% 1%
N10 VDDQ_20 VSSQ_20 M10 IN U4 E1_DQ0 2 CH 2 CH
B12 VDDQ_21 C11 DQ24/DQ0 BI 9 402 402
VSSQ_21 E1_CAS_N G3 U2 E1_DQ1
D12 VDDQ_22 R11 9 IN RAS_N/CAS_N DQ25/DQ1 BI 9
VSSQ_22 E1_RAS_N L3 T4 E1_DQ2 E1_CLK0_P
F12 A12 9 IN CAS_N/RAS_N DQ26/DQ2 BI 9 29 9 IN
VDDQ_23 VSSQ_23 T2 E1_DQ3
H12 VDDQ_24 C12 DQ27/DQ3 BI 9
VSSQ_24 E1_CS0_N L12 N4 E1_DQ4
K12 VDDQ_25 E12 9 IN WE_N/CS_N DQ28/DQ4 BI 9
VSSQ_25 E1_WE_N G12 N2 E1_DQ5 E1_CLK0_N
M12 N12 9 IN CS_N/WE_N DQ29/DQ5 BI 9 29 9 IN
VDDQ_26 VSSQ_26 M4 E1_DQ6
P12 VDDQ_27 R12 DQ30/DQ6 BI 9
VSSQ_27 J13 M2 E1_DQ7
T12 VDDQ_28 U12 ZQ DQ31/DQ7 BI 9
VSSQ_28 E_DRAM_RESET_R J2
G13 VDDQ_29 H13 28 IN RESET_N
VSSQ_29 J10 A5
L13 VDDQ_30 K13 SEN NC_1
VSSQ_30 E1_ADBI_N J4 U5
B14 A14 9 IN ABI_N NC_2
VDDQ_31 VSSQ_31
D14 VDDQ_32 VSSQ_32 C14
F14 VDDQ_33 VSSQ_33 E14 E1_ZQ M1005505-001 BGA170
M14 VDDQ_34 VSSQ_34 N14
P14 VDDQ_35 VSSQ_35 R14
T14 VDDQ_36 VSSQ_36 U14 1 R590
120 OHM
M1005505-001 BGA170 1%
2 CH
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
MEMORY: CHANNEL F0
U14 GDDR5_BASE IC
DDR5_8GBx32 MIRROR FUNCTION DISABLED WITH PIN J1 LOW
2 OF 2 PINS A4-M2 USE LEFT SIDE VALUES
POWER/GROUND
30 IN F0_VREFC J14 VREFC_37 U14 IC
A10 VREFD_38 DDR5_8GBX32
U10 VREFD_39 1 OF 2 V_MEMIO
J1 MF0/MF1 MF=0/MF=1
G1 VDD_1 VSS_1 H1
L1 VDD_2 VSS_2 K1 8 F0_MA_A3 H10 BA3_A3/BA1_A5 DQ0/DQ24 A4 F0_DQ0 8
IN BI
C G4
L4
VDD_3 VSS_3 B5
G5
8 IN F0_MA_A4
F0_MA_A5
K11
K10
BA2_A4/BA0_A2 DQ1/DQ25 A2
B4
F0_DQ1
F0_DQ2
BI 8 1 R582
2.37 KOHM C
VDD_4 VSS_4 8 IN BA1_A5/BA3_A3 DQ2/DQ26 BI 8 1%
C5 VDD_5 VSS_5 L5 8 F0_MA_A2 H11 BA0_A2/BA2_A4 DQ3/DQ27 B2 F0_DQ3 8
R5 T5
IN E4 F0_DQ4
BI 2 CH
VDD_6 VSS_6 DQ4/DQ28 BI 8 402
C10 B10 F0_MA_A12 J5 E2 F0_DQ5 F0_VREFC
VDD_7 VSS_7 8 IN A12_A13 DQ5/DQ29 BI 8 OUT 30
R10 VDD_8 VSS_8 D10 8 F0_MA_A6 K5 A11_A6/A9_A1 DQ6/DQ30 F4 F0_DQ6 8
D11 G10
IN F0_MA_A0 H4 F2 F0_DQ7
BI 1 R584 1
V_MEMIO VDD_9 VSS_9 8 IN A10_A0/A8_A7 DQ7/DQ31 BI 8
C1046
G11 VDD_10 VSS_10 L10 8 F0_MA_A1 H5 A9_A1/A11_A6 5.49 KOHM 1 UF
L11 P10
IN F0_MA_A7 K4 1% 10%
VDD_11 VSS_11 8 IN A8_A7/A10_A0
P11 VDD_12 T10 A11 F0_DQ8 2 CH 6.3 V
VSS_12 DQ8/DQ16 BI 8 402 2 X5R
G14 VDD_13 VSS_13 H14 8 F0_EDC_3 R2 EDC3/EDC0 DQ9/DQ17 A13 F0_DQ9 8 402
L14 K14
BI F0_EDC_2 R13 B11 F0_DQ10
BI
VDD_14 VSS_14 8 BI EDC2/EDC1 DQ10/DQ18 BI 8
8 F0_EDC_1 C13 EDC1/EDC2 DQ11/DQ19 B13 F0_DQ11 8
B1 A1
BI F0_EDC_0 C2 E11 F0_DQ12
BI
VDDQ_1 VSSQ_1 8 BI EDC0/EDC3 DQ12/DQ20 BI 8
D1 VDDQ_2 VSSQ_2 C1 DQ13/DQ21 E13 F0_DQ13 8
F1 E1 F0_DDBI_3 P2 F11 F0_DQ14
BI
VDDQ_3 VSSQ_3 8 BI DBI3_N/DBI0_N DQ14/DQ22 BI 8
M1 VDDQ_4 VSSQ_4 N1 8 BI F0_DDBI_2 P13 DBI2_N/DBI1_N DQ15/DQ23 F13 F0_DQ15
BI 8 V_MEMIO
P1 VDDQ_5 VSSQ_5 R1 8 F0_DDBI_1 D13 DBI1_N/DBI2_N
T1 U1
BI F0_DDBI_0 D2
VDDQ_6 VSSQ_6 8 BI DBI0_N/DBI3_N
G2 VDDQ_7 VSSQ_7 H2 DQ16/DQ8 U11 F0_DQ16 8
L2 K2 F0_WCK0_P D4 U13 F0_DQ17
BI
VDDQ_8 VSSQ_8 8 IN WCK01_P/WCK23_P DQ17/DQ9 BI 8
B3 VDDQ_9 VSSQ_9 A3 8 F0_WCK0_N D5 WCK01_N/WCK23_N DQ18/DQ10 T11 F0_DQ18 8
D3 C3
IN F0_WCK1_P P4 T13 F0_DQ19
BI
B F3
VDDQ_10
VDDQ_11
VSSQ_10
VSSQ_11 E3
8
8
IN
IN F0_WCK1_N P5
WCK23_P/WCK01_P
WCK23_N/WCK01_N
DQ19/DQ11
DQ20/DQ12 N11 F0_DQ20
BI
BI
8
8 B
H3 VDDQ_12 VSSQ_12 N3 DQ21/DQ13 N13 F0_DQ21 8
K3 R3 F0_CLK0_P J12 M11 F0_DQ22
BI 1 R578 1 R576
VDDQ_13 VSSQ_13 30 8 IN CK_P DQ22/DQ14 BI 8 60.4 OHM 60.4 OHM
M3 VDDQ_14 VSSQ_14 U3 30 8 IN F0_CLK0_N J11 CK_N DQ23/DQ15 M13 F0_DQ23
BI 8 1% 1%
P3 VDDQ_15 VSSQ_15 C4 2 CH 2 CH
T3 VDDQ_16 VSSQ_16 R4 8 IN F0_CKE0 J3 CKE_N 402 402
E5 VDDQ_17 VSSQ_17 F5 DQ24/DQ0 U4 F0_DQ24 8
N5 M5 F0_RAS_N G3 U2 F0_DQ25
BI F0_CLK0_P
VDDQ_18 VSSQ_18 8 IN RAS_N/CAS_N DQ25/DQ1 BI 8 30 8 IN
E10 VDDQ_19 VSSQ_19 F10 8 F0_CAS_N L3 CAS_N/RAS_N DQ26/DQ2 T4 F0_DQ26 8
N10 M10
IN T2 F0_DQ27
BI
VDDQ_20 VSSQ_20 DQ27/DQ3 BI 8
B12 VDDQ_21 VSSQ_21 C11 8 F0_WE_N L12 WE_N/CS_N DQ28/DQ4 N4 F0_DQ28 8 30 8 F0_CLK0_N
D12 R11
IN F0_CS0_N G12 N2 F0_DQ29
BI IN
VDDQ_22 VSSQ_22 8 IN CS_N/WE_N DQ29/DQ5 BI 8
F12 VDDQ_23 VSSQ_23 A12 DQ30/DQ6 M4 F0_DQ30 8
H12 C12 J13 M2 F0_DQ31
BI
VDDQ_24 VSSQ_24 ZQ DQ31/DQ7 BI 8
K12 VDDQ_25 VSSQ_25 E12 31 30 F_DRAM_RESET_R J2 RESET_N
M12 N12
IN J10 A5
VDDQ_26 VSSQ_26 SEN NC_1
P12 VDDQ_27 VSSQ_27 R12 8 F0_ADBI_N J4 ABI_N NC_2 U5
T12 U12
IN
VDDQ_28 VSSQ_28
G13 VDDQ_29 VSSQ_29 H13 M1005505-001 BGA170
L13 F0_ZQ
VDDQ_30 VSSQ_30 K13 R566 R571
B14 VDDQ_31 VSSQ_31 A14 8 F_DRAM_RESET 1 2 F_DRAM_RESET_C 1 2 F_DRAM_RESET_R 30 31
D14 C14
IN OUT
VDDQ_32 VSSQ_32 1 R588 10 OHM 1% 49.9 OHM 1%
F14 VDDQ_33 VSSQ_33 E14 120 OHM 402 CH 402 CH
M14 VDDQ_34 VSSQ_34 N14 1%
P14 VDDQ_35 VSSQ_35 R14 2 CH
T14 VDDQ_36 VSSQ_36 U14 402 1 R567 1
4.99 KOHM C1015
M1005505-001 BGA170 1% 120 PF
5%
A 2 CH
402 2
50 V
NPO
A
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D MEMORY: CHANNEL F1 D
GDDR5_BASE
U15 IC MIRROR FUNCTION ENABLED WITH PIN J1 HIGH
DDR5_8GBx32 PINS A4-M2 USE RIGHT SIDE VALUES
2 OF 2 V_MEMIO
POWER/GROUND
31 IN F1_VREFC J14 VREFC_37 U15 IC V_MEMIO
A10 VREFD_38 DDR5_8GBX32
U10 VREFD_39 1 OF 2
J1 MF0/MF1 MF=0/MF=1
G1 VDD_1 VSS_1 H1
L1 K1 F1_MA_A5 H10 A4 F1_DQ24
1 R251
VDD_2 VSS_2 8 IN BA3_A3/BA1_A5 DQ0/DQ24 BI 8 2.37 KOHM
C G4 VDD_3 VSS_3 B5 8 IN F1_MA_A2 K11 BA2_A4/BA0_A2 DQ1/DQ25 A2 F1_DQ25
BI 8 1%
L4
C5
VDD_4 VSS_4 G5
L5
8 IN F1_MA_A3
F1_MA_A4
K10
H11
BA1_A5/BA3_A3 DQ2/DQ26 B4
B2
F1_DQ26
F1_DQ27
BI 8 2 CH
402
C
VDD_5 VSS_5 8 IN BA0_A2/BA2_A4 DQ3/DQ27 BI 8 F1_VREFC
R5 T5 E4 F1_DQ28 OUT 31
VDD_6 VSS_6 DQ4/DQ28 BI 8
C10 VDD_7 VSS_7 B10 8 F1_MA_A12 J5 A12_A13 DQ5/DQ29 E2 F1_DQ29 8
R10 D10
IN F1_MA_A1 K5 F4 F1_DQ30
BI 1 R254 1
C398
VDD_8 VSS_8 8 IN A11_A6/A9_A1 DQ6/DQ30 BI 8
D11 VDD_9 VSS_9 G10 F1_MA_A7 H4 A10_A0/A8_A7 DQ7/DQ31 F2 F1_DQ31 5.49 KOHM 1 UF
V_MEMIO G11 L10
8 IN F1_MA_A6 H5
BI 8
1% 10%
VDD_10 VSS_10 8 IN A9_A1/A11_A6 6.3 V
L11 VDD_11 P10 F1_MA_A0 K4 2 CH 2 X5R
VSS_11 8 IN A8_A7/A10_A0 402 402
P11 VDD_12 VSS_12 T10 DQ8/DQ16 A11 F1_DQ16 8
G14 H14 F1_EDC_0 R2 A13 F1_DQ17
BI
VDD_13 VSS_13 8 BI EDC3/EDC0 DQ9/DQ17 BI 8
L14 VDD_14 VSS_14 K14 8 F1_EDC_1 R13 EDC2/EDC1 DQ10/DQ18 B11 F1_DQ18 8
BI F1_EDC_2 C13 B13 F1_DQ19
BI
8 BI EDC1/EDC2 DQ11/DQ19 BI 8
B1 VDDQ_1 VSSQ_1 A1 8 F1_EDC_3 C2 EDC0/EDC3 DQ12/DQ20 E11 F1_DQ20 8
D1 C1
BI E13 F1_DQ21
BI
VDDQ_2 VSSQ_2 DQ13/DQ21 BI 8 V_MEMIO
F1 VDDQ_3 VSSQ_3 E1 8 F1_DDBI_0 P2 DBI3_N/DBI0_N DQ14/DQ22 F11 F1_DQ22 8
M1 N1
BI F1_DDBI_1 P13 F13 F1_DQ23
BI
VDDQ_4 VSSQ_4 8 BI DBI2_N/DBI1_N DQ15/DQ23 BI 8
P1 VDDQ_5 VSSQ_5 R1 8 F1_DDBI_2 D13 DBI1_N/DBI2_N
T1 U1
BI F1_DDBI_3 D2
VDDQ_6 VSSQ_6 8 BI DBI0_N/DBI3_N
G2 VDDQ_7 VSSQ_7 H2 DQ16/DQ8 U11 F1_DQ8 8
L2 K2 F1_WCK1_P D4 U13 F1_DQ9
BI
VDDQ_8 VSSQ_8 8 IN WCK01_P/WCK23_P DQ17/DQ9 BI 8
B3 VDDQ_9 VSSQ_9 A3 8 F1_WCK1_N D5 WCK01_N/WCK23_N DQ18/DQ10 T11 F1_DQ10 8
D3 C3
IN F1_WCK0_P P4 T13 F1_DQ11
BI
VDDQ_10 VSSQ_10 8 IN WCK23_P/WCK01_P DQ19/DQ11 BI 8
B F3
H3
VDDQ_11 VSSQ_11 E3
N3
8 IN F1_WCK0_N P5 WCK23_N/WCK01_N DQ20/DQ12 N11
N13
F1_DQ12
F1_DQ13
BI 8 1 R577
60.4 OHM
1 R579
60.4 OHM B
VDDQ_12 VSSQ_12 DQ21/DQ13 BI 8
1% 1%
K3 VDDQ_13 VSSQ_13 R3 31 8 F1_CLK0_P J12 CK_P DQ22/DQ14 M11 F1_DQ14 8
M3 U3
IN F1_CLK0_N J11 M13 F1_DQ15
BI 2 CH 2 CH
VDDQ_14 VSSQ_14 31 8 IN CK_N DQ23/DQ15 BI 8 402 402
P3 VDDQ_15 VSSQ_15 C4
T3 VDDQ_16 VSSQ_16 R4 8 F1_CKE0 J3 CKE_N
E5 F5
IN U4 F1_DQ0 31 8 IN F1_CLK0_P
VDDQ_17 VSSQ_17 DQ24/DQ0 BI 8
N5 VDDQ_18 VSSQ_18 M5 8 F1_CAS_N G3 RAS_N/CAS_N DQ25/DQ1 U2 F1_DQ1 8
E10 F10
IN F1_RAS_N L3 T4 F1_DQ2
BI
VDDQ_19 VSSQ_19 8 IN CAS_N/RAS_N DQ26/DQ2 BI 8 F1_CLK0_N
N10 M10 T2 F1_DQ3 31 8 IN
VDDQ_20 VSSQ_20 DQ27/DQ3 BI 8
B12 VDDQ_21 VSSQ_21 C11 8 F1_CS0_N L12 WE_N/CS_N DQ28/DQ4 N4 F1_DQ4 8
D12 R11
IN F1_WE_N G12 N2 F1_DQ5
BI
VDDQ_22 VSSQ_22 8 IN CS_N/WE_N DQ29/DQ5 BI 8
F12 VDDQ_23 VSSQ_23 A12 DQ30/DQ6 M4 F1_DQ6 8
H12 C12 J13 M2 F1_DQ7
BI
VDDQ_24 VSSQ_24 ZQ DQ31/DQ7 BI 8
K12 VDDQ_25 VSSQ_25 E12 30 F_DRAM_RESET_R J2 RESET_N
M12 N12
IN J10 A5
VDDQ_26 VSSQ_26 SEN NC_1
P12 VDDQ_27 VSSQ_27 R12 8 F1_ADBI_N J4 ABI_N NC_2 U5
T12 U12
IN
VDDQ_28 VSSQ_28
G13 VDDQ_29 VSSQ_29 H13 M1005505-001 BGA170
L13 F1_ZQ
VDDQ_30 VSSQ_30 K13
B14 VDDQ_31 VSSQ_31 A14
D14 C14
1 R260
VDDQ_32 VSSQ_32 120 OHM
F14 VDDQ_33 VSSQ_33 E14 1%
M14 VDDQ_34 VSSQ_34 N14 2 CH
P14 VDDQ_35 VSSQ_35 R14 402
T14 VDDQ_36 VSSQ_36 U14
M1005505-001 BGA170
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1 1 1 1
C1055 C1065 C1063 C1062
22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805
C 1
C1012 1
C1045 1 C1052 1 C1013 1 C394 1
C1043 1 C392 1 C1016 1
C419 1
C1049 1 C409 1
C1040 1 C406 1
C1014 1 C1048 1 C1044 1
C1303 1
C1306 1 C1309 1
C1312 1 C1315 1 C1318 1 C1321 1 C1324 C
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
V_MEMIO
V_MEMIO V_MEMIO
B V_MEMIO B
V_MEMIO V_MEMIO
V_MEMIO V_MEMIO
1
C1018 1 C1026 1 C1030 1 C1019 1 C1037 1 C1059 1 C1029 1 C1017 1
C396 1
C400 1
C412 1
C413 1
C1051 1 C1047 1 C1033 1 C404
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
A A
NOTE: ADDITIONAL MEMORY DECOUPLING ON PAGE 33 MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 32/82 32/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1
C1088 1 C11021 C1106 1 C11101 C11141 C1118 1 C11221 C11261 C11301 C1134
1 UF
1
C1138 1 C11421 C1146 1 C11501 C11541 C1158 1 C11621 C11661 C11701 C11741
C1178 1 C11821 C1186 1 C11901 C11941 C1198 1 C12021 C12061 C12101 C1214
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
C 10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
1 UF
10%
1 UF
10%
1 UF
10%
1 UF 1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10% 10% C
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1
C1089 1 C11031 C1107 1 C11111 C11151 C1119 1 C11231 C11271 C11311 C1135
1 UF
1
C1139 1 C11431 C1147 1 C11511 C11551 C1159 1 C11631 C11671 C11711 C11751
C1179 1 C11831 C1187 1 C11911 C11951 C1199 1 C12031 C12071 C12111 C1215
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1
C1101 1 C11051 C1109 1 C11131 C11171 C1121 1 C11251 C11291 C11331 C1137
1 UF
1
C1141 1 C11451 C1149 1 C11531 C11571 C1161 1 C11651 C11691 C11731 C11771
C1181 1 C11851 C1189 1 C11931 C11971 C1201 1 C12051 C12091 C12131 C1217
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
ADDITIONAL DECOUPLING
V_MEMPHY
A A
1
C1301 1 C1302
1 UF 1 UF
10% 10%
6.3 V 6.3 V
2 X5R 2 X5R
402 402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U2 KIC IC
KIC: USB 6 of 11
USBD_D0_DP AF8 USB2_WIFI_DP
BI 46
WIFI
USBD_D0_DN AE8 USB2_WIFI_DN 46
BI
D D
USBC_D0_DP AC4 USB2_AUX_DP 45
BI
USBC_D0_DN AC3 USB2_AUX_DN 45
BI
C501 REAR 1
1 2 USB3_AUX_TP 45
OUT
45 USB3_AUX_RP Y1 USBC_D1_RXP USBC_D1_TXP W3 USB3_AUX_TP_C 0.1 UF 10% X5R
IN 16 V 402
REAR 1 45 USB3_AUX_RN Y2 USBC_D1_RXN USBC_D1_TXN W4 USB3_AUX_TN_C C500
IN 1 2 USB3_AUX_TN
OUT 45
0.1 UF 10% X5R
16 V 402
C499
1 2 USB3_BP_P1_TP 45
USB3_BP_P1_RP V1 U3 USB3_BP_P1_TP_C
OUT
45 IN USBB_D2_RXP USBB_D2_TXP
0.1 UF 10% X5R
REAR 0 16 V 402
45 USB3_BP_P1_RN V2 USBB_D2_RXN USBB_D2_TXN U4 USB3_BP_P1_TN_C C498
IN 1 2 USB3_BP_P1_TN
OUT 45
0.1 UF 10% X5R
REAR 0
16 V 402
C USBB_D0_DP AE4 USB2_BP_P1_DP
BI 45
C
USBB_D0_DN AE3 USB2_BP_P1_DN 45
BI
B 1
C1097
2 USB3_FP_P0_TP
OUT 45 B
45 USB3_FP_P0_RP_BUFF AA8 USBA_D2_RXP USBA_D2_TXP AB10 USB3_FP_P0_TP_C
IN 0.1 UF 10% X5R
FRONT 16 V 402
45 USB3_FP_P0_RN_BUFF AA7 USBA_D2_RXN USBA_D2_TXN AB9 USB3_FP_P0_TN_C
IN C1096
1 2 USB3_FP_P0_TN 45 FRONT
OUT
0.1 UF 10% 402
USBA_D0_DP AC7 16 V X5R USB2_FP_P0_DP 45
BI
USBA_D0_DN AC8 USB2_FP_P0_DN 45
BI
A AA5 USBA_D2_AMOUNT 1
A
USBA_D2_AMOUT DB97
USBA_D1_AMOUT AE6 USBA_D1_AMOUNT 1
DB23
USBA_D0_AMOUT AC11 USBA_D0_AMOUNT 1
DB100
USBB_D2_AMOUT R5 USBB_D2_AMOUNT 1
DB10
USBB_D1_AMOUT AD5 USBB_D1_AMOUNT 1
DB95
USBB_D0_AMOUT AF4 USBB_D0_AMOUNT 1
DB94
USBA_D1_TXRTUNE AB11 USBA_D1_TXRTUNE USBC_D1_AMOUT W5 USBC_D1_AMOUNT 1
DB24
USBC_D0_AMOUT AC5 USBC_D0_AMOUNT 1
1 R86 DB21
174 OHM
1% USBD_D0_AMOUT AE9 USBD_D0_AMOUNT 1
DB98 PROJECT NAME PAGE CSA FAB VER
2 CH MICROSOFT PAGE
402
X861949-001 BGA515 Cactus
CONFIDENTIAL 34/82 34/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KIC: PCIEX,SATA,VIDEO
D D
C589
1 2 PEX_L0_SB_SOC_TP_C 2
OUT
0.1 UF 10% X5R
U2 KIC IC 16 V 402
1
C594
2 PEX_L0_SB_SOC_TN_C 2
OUT
3 of 11 0.1 UF 10% X5R
C586 16 V 402
1 2 PEX_L1_SB_SOC_TP_C 2
2 IN PEX_L0_SOC_SB_TP_C D26 PEX_RX0_DP PEX_TX0_DP C24 PEX_L0_SB_SOC_TP OUT
2 PEX_L0_SOC_SB_TN_C E26 PEX_RX0_DN PEX_TX0_DN D24 PEX_L0_SB_SOC_TN 0.1 UF 10% X5R
IN PEX_L1_SOC_SB_TP_C A23 C22 PEX_L1_SB_SOC_TP 16 V 402
2 IN PEX_RX1_DP PEX_TX1_DP C587
2 PEX_L1_SOC_SB_TN_C B23 PEX_RX1_DN PEX_TX1_DN D22 PEX_L1_SB_SOC_TN 1 2 PEX_L1_SB_SOC_TN_C 2
IN OUT
0.1 UF 10% X5R
16 V 402
50 SATA1_HDD_RP B6 SATA1_RX_DP SATA1_TX_DP D5 SATA1_HDD_TP 50
IN SATA1_HDD_RN A6 C5 SATA1_HDD_TN
OUT
50 IN SATA1_RX_DN SATA1_TX_DN OUT 50
50 SATA0_ODD_RP B4 SATA0_RX_DP SATA0_TX_DP D3 SATA0_ODD_TP 50
IN OUT
C 50 IN SATA0_ODD_RN A4 SATA0_RX_DN SATA0_TX_DN C3 SATA0_ODD_TN
OUT 50
C
SATA_AMOUT C1 SATA_AMOUT 1
DB13
PEX_AMOUT B25 PEX_AMOUT 1
DB51
X861949-001 BGA515
C540
1 2 DP_L1_SB_SOC_TP_C 3
OUT
0.1 UF 10% X5R
V_3P3 16 V 402
V_3P3STBY
U2 IC C536
KIC 1 2 DP_L1_SB_SOC_TN_C
B R74 1 OUT 3
B
2
SOT23-3
2 KOHM
16 V 402
1
NC
1%
U17
CH 2
402 C532
1 HDMI_RX_REXT N3 TMDS_RX_REXT 1 2 DP_L0_SB_SOC_TP_C 3
DB19 OUT
3
3 DP1_HPD_R B8 DP_TX_HPD
IN
A DDA_LFCSENSE F11
A
DDA_LFCSENSE
R81 1
100 KOHM DDA_LFC F10 DDA_LFC DP_ATB C12 DP_ATB 1
1% DB27
CH 2 1
402 C112 X861949-001 BGA515
0.1 UF
10%
16 V
2 X5R
402 PLACE C112 AS CLOSE AS POSSIBLE
TO U2 PINS F10-F11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R514 1 1 R517
V_3P3STBY 4.7 KOHM
10 KOHM 5%
D V_3P3STBY 1% 1 2 CH D
U2 CH 2 FT60 FTP
KIC IC 36 14 402
1 R472 402 IN
4.7 KOHM 36 14 IN
1 R486 5%
100 KOHM 2 EMPTY
4 of 11
1% 1 402 V_3P3STBY
SOC_THERMTRIP_N
2 CH FT43 FTP SMC_UART1_TXD T24 SMC_TXD 1
FTP FT48
402 73 39 SMC_RST_N AF23 SMC_RST_N_IN
IN
SP_SMC_INT_N
3P3V 5V OK
C466 74 51 IN PWRSW_N V23 SMC_P4_GPIO7 SMC_UART1_RTS V24 ODD_3P3V_STBY_EN_N
OUT 50 R110 1 1 R126
0.01 UF
10 KOHM 10 KOHM
10% 74 51 EJECTSW_N V22 SMC_P4_GPIO6
1% 1%
16 V IN CH 2 2 CH
EMPTY
402 BINDSW_N_R T23
V_3P3STBY 402 402
45 IN SMC_P4_GPIO5
36 SP_SMC_INT SOC_THERMTRIP 36
AUDIO_PWM_OUT U23 1 R205 R122 1 1 R123
51 OUT SMC_P4_GPIO4
100 KOHM
0 OHM 0 OHM
1%
5% U37 3 6 5%
64 VREG_PWRGPC_EN U22 SMC_P4_GPIO3 CH 2 2 CH
OUT 2 CH 402 402
402 5 2 SOC_THERMTRIP_N_R
1 R483 51 OUT ACC_RESET_N U21 SMC_P4_GPIO2 3P3V 5V OK SP_SMC_INT_N_R
10 KOHM SMC_P2_GPIO7 G2 VREG_PWRGPAB_CPUGFX_PWRGD 54 58 61 64 74
1% PCIE_RST_N T21
IN
76 42 OUT SMC_P4_GPIO1
2 CH 1 F2 COLD_RESET_N XSTR
402 FT53 FTP SMC_P2_GPIO6 IN 74 75 4 1
C R380 1
63 40 OUT VREG_3P3_EN R23 SMC_P4_GPIO0
G1 HDD_PWR_EN C
SMC_P2_GPIO5 OUT 50
10 KOHM I21 R125
1% 1P8V NO 5V SMC_P2_GPIO4 F1 SOC_THERMTRIP_R 1 2 SOC_THERMTRIP 36
CH 2 75 14 TCK L21 SMC_P3_GPIO7 0 OHM 5%
402 OUT G3 ODD_PWR_EN 402 CH
SMC_P2_GPIO3 OUT 50
75 14 TMS M22 SMC_P3_GPIO6
OUT H5 ODD_OPEN
SMC_P2_GPIO2 OUT 50
62 IN VREG_V5P0_PWRGD N22 SMC_P3_GPIO5 R105 V_SOC1P8
SMC_P2_GPIO1 J5 SP_SMC_INT_R 1 2 SP_SMC_INT 36
62 VREG_V5P0_EN N21 SMC_P3_GPIO4 0 OHM 5%
OUT J6 ODD_WAKE_N 402 CH
SMC_P2_GPIO0 IN 50 1 R518
1 PSU_FAN_EN P21 SMC_P3_GPIO3 R129 4.7 KOHM
FT413 FTP
1 1 2 SOC_THERMTRIP_N 14 36 5%
DB8
VREG_PWRGPB_EN R21
IN
64 54 OUT SMC_P3_GPIO2 1P8V NO 5V 0 OHM 5% R133 2 CH
R488 SMC_P1_GPIO7 J21 TDI_R 402 EMPTY 1 2 TDI 14 75 402
FAN_TACH_IN 1 2 FAN_SPEED R22
OUT 1
FTP FT39
51 IN SMC_P3_GPIO1 0 OHM 5% R127
100 OHM 1% 1 SMC_P1_GPIO6 H21 SOC_PWR_OK_R 402 CH 1 2 SOC_PWR_OK 14 54 75
DB122 VREG_PWRGPA_EN P23
OUT
63 58 OUT 402 CH SMC_P3_GPIO0 R136 0 OHM 5%
65 SMC_P1_GPIO5 J22 SOC_RST_N_R 1 2 402 CH SOC_RST_N 14 75
1 SMC_RXD
3P3V 5V OK OUT
FT52 FTP 0 OHM 5% 1
V_3P3STBY SMC_P1_GPIO4 K22 TDO_R 402 CH FTP FT61
V_SOC1P8 R139 R128 1
B 1 SMC_P1_GPIO3 J23 FAN_PWM
OUT 51
1 2 SP_SMC_INT_N
IN 14 36 4.7 KOHM B
FTP FT51 0 OHM 5% R137 5%
402 EMPTY 1 2 TDO 14 75 CH 2
V25 SMC_UART1_RXD SMC_P1_GPIO2 H25 IR_MOD_TIMER_IN 1
DB53
IN 402
R467 1 1 R469 0 OHM 5%
1.27 KOHM 1.27 KOHM 1 R515 1 R516 ODD_STATUS J25 IR_BLAST_SMC_OUT 402 CH
1% 1% 2 KOHM 2 KOHM 50
IN SMC_P1_GPIO1 OUT 69
1% 1%
CH 2 2 CH V26 H26 LED_NEXUS
402 402 2 CH 2 CH SMC_UART1_CTS SMC_P1_GPIO0 OUT 51
402 402 R471 3P3V NO 5V
14 SB_SOC_DATA 1 2 SB_SOC_DATA_R 1
BI FTP FT41
3P3V 5V OK
243 OHM 1%
402 CH R473 AE21 SMBUS3_SDA SMC_P0_GPIO7 M23 HDMI_V_5P0_EN 48
SB_SOC_CLK 1 2 SB_SOC_CLK_R AD21
OUT
14 OUT SMBUS3_SCK
243 OHM 1% 1 SMC_P0_GPIO6 M24 IR_MOD_TIMER_OUT 1
1 FTP FT42 DB52
FT38 FTP R470 402 CH
78 73 70 58 54 48 SMBUS_DATA 1 2 SMBUS_DATA_R AE20 SMBUS2_SDA SMC_P0_GPIO5 L23 DP0_HPD_SB 48
BI SMBUS_CLK_R AF20
IN
0 OHM 5% SMBUS2_SCK
402 CH SMC_P0_GPIO4 K24 WIFI_RESET_N 46
FT36 FTP
1 OUT
R468
78 73 70 58 54 48 SMBUS_CLK 1 2 HDMI_TX_DDC_DATA_SB H6 SMBUS1_SDA SMC_P0_GPIO3 L25 M2_PWR_EN 42 76
OUT HDMI_TX_DDC_CLK_SB G6
OUT
0 OHM 5% SMBUS1_SCK R491
402 CH SMC_P0_GPIO2 M25 HDMI_RX_DDC_5V_E_R 1 2 HDMI_RX_DDC_5V_E 47
IN
DDC = HDMI OUT 0 OHM 5%
R20 HDMI_RX_DDC_DATA_SB G5 SMBUS0_SDA SMC_P0_GPIO1 L26 SMC_DBG_LED0_SWO 73 402 CH
48 BI SB_DDC_DATA 1 2
HDMI_RX_DDC_CLK_SB F5
OUT
SMBUS0_SCK
49.9 OHM1% SMC_P0_GPIO0 K26 VREG_1P1_ACTIVE_EN 65 68
402 CH SECURITY_BYPASS AC14
OUT
SECURITY_BYPASS
R27 N26 SMC_IR_IN 1
48 SB_DDC_CLK 1 2 R492
OUT 10 KOHM
A 49.9 OHM1%
402 CH
BGA515
1%
2
A
RX_DDC = HDMI IN
R390 X861949-001 CH
402
47 HDMI_RX_DDC_DATA 1 2
BI USED BY SMC IR BLASTER SOLUTION
49.9 OHM1% SMC IR BLASTER GPIO'S
402 CH ---------------------
R389 SMC_P1_GPIO1 > IR_SMC_BLAST_OUT (TIMER 0)
47 HDMI_RX_DDC_CLK 1 2 SMC_P0_GPIO6 > IR_MOD_TIMER_OUT (TIMER 1)
IN
10 OHM 1% SMC_P4_GPIO2 > IR_MOD_TIMER_IN (TIMER 2)
402 CH
51 IR_DATA
IN
MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 36/82 36/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
KIC: FACET
V_3P3STBY
1
2
BAS40LT
SOT23-3
EG400
NC
C
3
C
HDPO_MD_PUR
1
FT49 FTP
1
FT57 FTP
1
FT22 FTP
1 U2 KIC IC 1
FT20 FTP FTP FT56
1 2 of 11 1
FT24 FTP FTP FT47
73 IN KER_DBG_CTS R26 UART0_CTS UART0_TXD U25 KER_DBG_TXD
OUT 73 R611 1
1 KOHM
73 KER_DBG_RXD U26 UART0_RXD UART0_RTS T25 KER_DBG_RTS 73
1%
IN OUT CH 2
SPI_SS_N AF13
402
73 IN SPI_SS_N 1
R400 FTP FT74 R490
73 SPI_MOSI AF11 SPI_MOSI SPI_MISO AE12 SPI_MISO_R 1 2 SPI_MISO 73 HDMIDPOUT_MODE_DET 48
IN OUT IN
36.5 OHM 1% 200 OHM 1%
73 SPI_CLK AE11 SPI_CLK_IN 402 CH 402 CH
IN N24 SMM_GPIO3
GPIO3 R149
GPIO2 P24 SMM_GPIO2 HDMIDPOUT_MODE_SEL 48
P25 SMM_GPIO1
OUT
GPIO1 100 OHM 1%
73 SB_TDI AA13 TDI GPIO0 P26 SMM_GPIO0 1 402 CH
IN SB_TMS AB14
FTP FT412
B 73 IN
IN SB_TRST AB12
TMS
TRST R489 B
73 SB_TCK AB13 TCK TDO AA12 1 2 HDMI_TX_RTMR_EN_R 48
IN 1 H22
OUT
FT29 FTP POR_ATB 100 OHM 1%
1 402 CH
FT19 FTP
1 SB_TDO 73
FT32 FTP
1 X861949-001 BGA515 OUT
FT27 FTP 1
FTP FT18
POR_ATB 1 DB43
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
KIC: POWER D
U2 KIC
9 of 11 IC
AF1 VSS[0] VSS[68] L22
AF2 VSS[1] VSS[69] L24
U2 KIC IC AF3 VSS[2] VSS[70] K6
8 of 11 AF7 VSS[3] VSS[71] K21
AF9 VSS[4] VSS[72] K23
AF10 VSS[5] VSS[73] K25
PEX_VSS[0] A26 AF12 VSS[6] VSS[74] J24
PEX_VSS[1] A25 AF15 VSS[7] VSS[75] J26
PEX_VSS[2] A24 AF17 VSS[8] VSS[76] H1
PEX_VSS[3] A22 AF19 VSS[9] VSS[77] AB21
PEX_VSS[4] B26 AF21 VSS[10] VSS[78] G4
PEX_VSS[5] B24 AF24 VSS[11] VSS[79] G25
PEX_VSS[6] B22 AF25 VSS[12] VSS[80] F3
PEX_VSS[7] C26 AF26 VSS[13] VSS[81] F7
E9 DP_VSS[0] PEX_VSS[8] C25 AE1 VSS[14] VSS[82] F8
A8 C23 AE2 F18
C D10
DP_VSS[1]
DP_VSS[2]
PEX_VSS[9]
PEX_VSS[10] D25 AE5
VSS[15]
VSS[16]
VSS[83]
VSS[84] F23 C
D8 DP_VSS[3] PEX_VSS[11] D23 AE7 VSS[17] VSS[85] E1
A10 DP_VSS[4] PEX_VSS[12] E25 AE16 VSS[18] VSS[86] E21
C8 DP_VSS[5] PEX_VSS[13] E24 AE22 VSS[19] VSS[87] AB22
C9 DP_VSS[6] PEX_VSS[14] E22 AE23 VSS[20] VSS[88] AB23
C11 DP_VSS[7] PEX_VSS[15] F25 AE24 VSS[21] VSS[89] AB24
E11 DP_VSS[8] AE25 VSS[22] VSS[90] D18
AE26 VSS[23] VSS[91] D19
F4 SATA_VSS[0] USB3_VSS[0] AC1 AD3 VSS[24] VSS[92] AB25
E3 SATA_VSS[1] USB3_VSS[1] AC2 AD4 VSS[25] VSS[93] C16
E5 SATA_VSS[2] USB3_VSS[2] AC9 AD6 VSS[26] VSS[94] C17
D1 SATA_VSS[3] USB3_VSS[3] AC10 AD8 VSS[27] VSS[95] C21
D2 SATA_VSS[4] USB3_VSS[4] AB3 AD9 VSS[28] VSS[96] B12
D4 SATA_VSS[5] USB3_VSS[5] AB4 AD18 VSS[29] VSS[97] AB26
C2 SATA_VSS[6] USB3_VSS[6] AB5 AC12 VSS[30] VSS[98] AA19
C6 SATA_VSS[7] USB3_VSS[7] AB6 AC13 VSS[31] VSS[99] AA20
C4 SATA_VSS[8] USB3_VSS[8] AB7 AC15 VSS[32] VSS[100] B18
B3 SATA_VSS[9] USB3_VSS[9] AB8 AC17 VSS[33] VSS[101] B19
B2 SATA_VSS[10] USB3_VSS[10] AA1 AC19 VSS[34] VSS[102] A12
B5 SATA_VSS[11] USB3_VSS[11] AA2 AC20 VSS[35] VSS[103] A17
B7 SATA_VSS[12] USB3_VSS[12] AA9 AC21 VSS[36] VSS[104] H23
A2 SATA_VSS[13] USB3_VSS[13] AA10 AB16 VSS[37] VSS[105] AB19
B A3
A5
SATA_VSS[14] USB3_VSS[14] AA11
Y3
AA14
AA18
VSS[38] VSS[106] AB20
AC18 B
SATA_VSS[15] USB3_VSS[15] VSS[39] VSS[107]
A7 SATA_VSS[16] USB3_VSS[16] Y4 V21 VSS[40] VSS[108] AC22
B1 SATA_VSS[17] USB3_VSS[17] Y5 U24 VSS[41] VSS[109] AC23
D6 SATA_VSS[18] USB3_VSS[18] W1 T11 VSS[42] VSS[110] AC26
USB3_VSS[19] W2 T12 VSS[43] VSS[111] AD23
USB3_VSS[20] V3 T13 VSS[44] VSS[112] AD25
R6 HDMI_VSS[0] USB3_VSS[21] V4 T15 VSS[45] VSS[113] AB18
N1 HDMI_VSS[1] USB3_VSS[22] V5 T16 VSS[46] VSS[114] AD20
N2 HDMI_VSS[2] USB3_VSS[23] U1 T22 VSS[47] VSS[115] AD19
N4 HDMI_VSS[3] USB3_VSS[24] U2 T26 VSS[48] VSS[116] AE19
N6 HDMI_VSS[4] USB3_VSS[25] T3 R11 VSS[49] VSS[117] AA21
M3 HDMI_VSS[5] USB3_VSS[26] T4 R24 VSS[50] VSS[118] AA22
M4 HDMI_VSS[6] USB3_VSS[27] T5 R25 VSS[51] VSS[119] AA23
L1 HDMI_VSS[7] USB3_VSS[28] R1 P12 VSS[52] VSS[120] AA24
L4 HDMI_VSS[8] USB3_VSS[29] R2 P14 VSS[53] VSS[121] AA25
K3 HDMI_VSS[9] USB3_VSS[30] P3 P22 VSS[54] VSS[122] AA26
J1 HDMI_VSS[10] USB3_VSS[31] P4 N15 VSS[55] VSS[123] Y21
H2 HDMI_VSS[11] N23 VSS[56] VSS[124] Y22
H3 HDMI_VSS[12] N25 VSS[57] VSS[125] Y23
H4 HDMI_VSS[13] M11 VSS[58] VSS[126] Y24
M14 VSS[59] VSS[127] Y25
M16 VSS[60] VSS[128] Y26
F14 PLL_VSS[0] M21 VSS[61] VSS[129] D13
E16 PLL_VSS[1] M26 VSS[62] VSS[130] D14
E13 PLL_VSS[2] L5 VSS[63] VSS[131] D15
L11 VSS[64] VSS[132] C13
L12 VSS[65] VSS[133] B13
L15 B14
A X861949-001 BGA515 L16
VSS[66]
VSS[67]
VSS[134]
VSS[135] B15 A
VSS[136] A20
X861949-001 BGA515
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3
KIC: CLOCKS,STRAPPING,POR
1 R94
10 KOHM
1%
2 CH
402 V_12P0_GATED
D D
PEX REF CLOCKS CONTROLLED BY SMC
1 R90
10 KOHM
1% C212 1 1 R494
2 EMPTY 10 KOHM
KIC_BASE 1 UF 1%
V_3P3 402 10%
U2 16 V 2 CH R494/V_EXT_DET IS NOW CONNECTED TO V_12P0_GATED
KIC IC X5R 2 402
V_1P8STBY 603 NOMINAL TRIP POINT = 9.55V
1 of 11 1 R493
1 R108 1.13 KOHM
10 KOHM V_EXT_DET G21 V_EXT_DET 1%
1% G22 V_VDD18_DET OUT 64 2 CH
2 CH V_EXT_OK F22 V12P0_PWRGD 402
1
402 DB49 R476
PEX_REF_CLK1_REQN C18 PEX_REF_CLK1_REQN SMC_RST_N_OUT AF22 SMC_RST_N_OUT_R 1 2 SMC_RST_N 36 73
PEX_REF_CLK2_REQN C19 1 1
OUT
PEX_REF_CLK2_REQN DB29 DB30 1 KOHM 1% 1
1 R107 402 CH C593
10 KOHM AD22 VPGM CLK_MONITOR E17 SB_CLK_MONITOR KEEP DB29 AND DB30 270 PF
1% CLOSE TO EACH OTHER IN 10%
50 V
2 EMPTY 1 BKUP_SB_SYNC_CLKP E18 LAYOUT 2 X7R
402 DB36 100M_SYNC_CLK_BYPASS_DP R120 402
1 BKUP_SB_SYNC_CLKN E19 100M_SYNC_CLK_BYPASS_DN RTC_CLK_OUT A21 RTC_CLK_OUT 1 2 X32K_X2_R 14
DB42 OUT
R457 0 OHM 5%
SMC_XTAL_OUT 1 2 SMC_XTAL_OUT_R 402 CH 1 R112
C 1
R461
2
1 KOHM
402 CH
1%
SMC_XTAL_IN
A18
A19
XTAL_CLK_OUT EMMC_CLK AC16
C20
MMC_CLK
OUT 43
ENET_REF_CLK
69.8 KOHM
1% C
XTAL_CLK_IN ENET_REF_CLK OUT 42
249 KOHM 1% 2 EMPTY
402 CH 2 R465 402
49.9 OHM AD24 B16 SOC_SYNC_NS_100M_CLKP
Y2 1% TEST SOC_NS_SYNC_CLK_DP OUT 2
EMPTY SOC_NS_SYNC_CLK_DN B17 SOC_SYNC_NS_100M_CLKN 2
25 MHZ 1
402 OUT
XTAL R121
1 2 SMC_BYPASS_CLK_IN D21 SMC_BYPASS_CLK_IN
10 KOHM1% SOC_NS_AV_CLK_DP A13 SOC_AV_NS_100M_CLKP 2
1 3
402 CH A14 SOC_AV_NS_100M_CLKN
OUT
SOC_NS_AV_CLK_DN OUT 2
1 1
C582 2 4 C585 R456 R460
30 PF 30 PF NO_M2 1 NO_M2 1
5% 5% 1BKUP_SB_PEX_REF_CLKP E20 PCIE_BYPASS_CLK_DP PEX_REF_CLK2_DP B20 SOC_NB_CLKP 2 SOC_NB_CLKP_R 2 SOC_NB_PEX_SS_100M_CLKP 2
50 V M1020244-001 50 V DB25
1BKUP_SB_PEX_REF_CLKN D20 B21 SOC_NB_CLKN
OUT 77
2 NPO 2 NPO DB28 PCIE_BYPASS_CLK_DN PEX_REF_CLK2_DN 0 OHM 5% 0 OHM 5% R459 NO_M2
402 SM 402 402 CH R464 NO_M2 CH 1
OUT 77 1 2 SOC_NB_CLKN_R 402 2 SOC_NB_PEX_SS_100M_CLKN 2
OUT 77
1 250M_CLK_BYPASS_DP F20 250M_CLK_BYPASS_DP PEX_REF_CLK1_DP C14 ENET_CLKP 0 OHM 5% 0 OHM 5%
DB46 R411 402 CH R423 402 CH
1 250M_CLK_BYPASS_DN F21 250M_CLK_BYPASS_DN PEX_REF_CLK1_DN C15 ENET_CLKN NO_M2 1 NO_M2 1
DB47 2 ENET_CLKP_R 2 ENET_PEX_SS_100M_CLKP 42
OUT 77
0 OHM 5% R419 NO_M2 0 OHM 5%
1 BKUP_SB_AV_CLKP D16 A15 SOC_CLKP
OUT 77
402 CH 1 2 ENET_CLKN_R 402 CH 1 R4282 NO_M2
ENET_PEX_SS_100M_CLKN
DB31 AV_CLK_BYPASS_DP PEX_REF_CLK0_DP OUT 42
1 BKUP_SB_AV_CLKN D17 AV_CLK_BYPASS_DN PEX_REF_CLK0_DN A16 SOC_CLKN 77
DB32 0 OHM 5% 0 OHM 5%
402 CH 402 CH
B NO_M2 1
R427
2 SOC_CLKP_R NO_M2 1
R443
2 SOC_PEX_SS_100M_CLKP B
OUT 2
X861949-001 M2_ONLY 77
BGA515 0 OHM 5% R435 NO_M2 0 OHM 5% R449 NO_M2
R432 1 402 CH 1 2 SOC_CLKN_R 402 CH 1 2 SOC_PEX_SS_100M_CLKN
10 KOHM OUT 2
1% 0 OHM 5% 0 OHM 5% 77
CH 2 402 CH 402 CH
TODO; IF SMCFW CHANGES 402
DO NOT STUFF RESISTORS IF BOTH HDD AND M2 ARE STUFFED
BASED ON M2_ONLY STUFFING
OPTION, THEN TURN OFF CLOCKS
INSTEAD OF TERMINATING
M2_ONLY
R462 1
10 KOHM
1%
CH 2
402
A A
X861949-008 IC U2 IC,KRAKEN SB,BGA515 KIC_DEV MICROSOFT PROJECT NAME PAGE CSA FAB VER
ZZ480
I1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C492 V_3P3
1 2
D 1 R367 D
10 KOHM 1 UF 10% 402
1% 6.3 V EMPTY
2
2 CH R368
63 36 IN VREG_3P3_EN 402 1 2 VREG_3P3_EN_KIC_R 1 R379
R376 U25 0 OHM 1
0 OHM 5% 1 221 OHM 5%
402 CH FET
1% SOT23-3 EMPTY
EMPTY C488 402 2
3
V_SB1P8 2 402 1 2
KIC3P3HDMI_C
U2 KIC IC 0.1 UF 10%
16 V EMPTY
402
11 of 11
E10 AUX_VDD18[0] HDMI_VDD33[0] M5 KIC3P3HDMI_FB
D9 AUX_VDD18[1] HDMI_VDD33[1] M6
D11 AUX_VDD18[2] 2 1
C88 C93
1 UF 1 UF
10% 10%
6.3 V 6.3 V
1 X5R 2 X5R
U2 KIC IC 402 402
V_SB1P8 V_SB1P1
10 of 11 I4
F12 P5
C V_3P3STBY
F13
CK_VDD18[0]
CK_VDD18[1]
HDMI_VDD11[0]
HDMI_VDD11[1] P6 V_SB1P1 C
C142 2 C131 2 C147 1 E12 CK_VDD18[2] HDMI_VDD11[2] N5
1 UF 1 UF 1 UF
VDD33S_1[0] AB15 10% 10% 10%
AB17 6.3 V 6.3 V 6.3 V
VDD33S_1[1] X5R X5R X5R
AA15 1 1 2 1 1
VDD33S_1[2] 402 402 402
C159 C164
V_1P1STBY VDD33S_1[3] AA16 1 UF 1 UF
VDD33S_1[4] AA17 10% 10%
E14 PLL1_VDD18 PLL1_VDD11 F15 6.3 V 6.3 V
VDD33S_1[5] W21 2 2
E15 PLL0_VDD18 PLL0_VDD11 F16 X5R X5R
VDD33S_1[6] W22 V_SB1P8 402 402
H24 PLL2_VDD11S[0] VDD33S_1[7] W23
G23 PLL2_VDD11S[1] VDD33S_2[0] L6 V_SB1P1
G24 PLL2_VDD11S[2] VDD33S_2[1] K5
1 1
C130 C146 F24 G26
1 UF 1 UF PEX_VDD18[0] PEX_VDD11[0]
V_3P3STBY 10% 10% E23 PEX_VDD18[1] PEX_VDD11[1] F26
6.3 V 6.3 V
2 X5R 2 X5R 1 1 1 1
402 402 C204 C199 C198 C205
10 UF 1 UF 1 UF 4.7 UF
USB2_VDD33S[0] AE10 20% 10% 10% 10%
AD10 6.3 V 6.3 V 6.3 V 6.3 V
USB2_VDD33S[1] 2 X5R 2 X5R 2 X5R 2 X5R
USB2_VDD33S[2] AD11 V_SB1P8 603 402 402 603
V_1P1STBY
B AD7
AC6
USB3_VDD18<0>
V6 B
V_3P3STBY USB3_VDD18<1> USB3_VDD11<0> V_SB1P1
AA6 USB3_VDD18<2> USB3_VDD11<1> U5
T14 VDD11S[0] 1 2 1 1 2 1
C191 C188 C138 C123 C104 C195 Y6 USB3_VDD18<3> USB3_VDD11<2> U6
R12 VDD11S[1] 1 UF 1 UF 1 UF 1 UF 1 UF 10 UF W6 USB3_VDD18<4> USB3_VDD11<3> T6
R13 VDD11S[2] VDD33S_XTAL[0] F19 10% 10% 10% 10% 10% 20%
R14 F17 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
VDD11S[3] VDD33S_XTAL[1] 2 X5R 1 X5R 2 X5R 2 X5R 1 X5R 2 X5R 1 1 1 1 1 1
R15 VDD11S[4] V_1P8STBY 1 1 402 402 402 402 402 603 C109 C79 C102 C103 C90 C160
R16 C173 C174 10 UF 1 UF 1 UF 1 UF 1 UF 4.7 UF
VDD11S[5] 1 UF 1 UF 20% 10% 10% 10% 10% 10%
P11 VDD11S[6] VDD18S[0] AD26 10% 10% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
P13 AC24 6.3 V 6.3 V V_SB1P8 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
VDD11S[7] VDD18S[1] 2 X5R 2 X5R 603 402 402 402 402 603
P15 VDD11S[8] VDD18S[2] AC25 402 402
P16 VDD11S[9] VDD18S[3] W24 V_SB1P8
N11 VDD11S[10] VDD18S[4] W25
E2 SATA_VDD18[0] SATA_VDD11[0] F6
N12 VDD11S[11] VDD18S[5] W26 V_SB1P1
E4 SATA_VDD18[1] SATA_VDD11[1] E6
N13 VDD11S[12]
N14 VDD11S[13] V_1P8STBY
N16 VDD11S[14] 1 2 2 2 2
M12 AD14 C106 C98 C96 C97 C95
VDD11S[15] FLSH_VDD18S[0] 1 UF 1 UF 1 UF 1 UF 1 UF
M13 VDD11S[16] FLSH_VDD18S[1] AD13 10% 10% 10% 10% 10%
AD12 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 1 1 1 1
M15 VDD11S[17] FLSH_VDD18S[2] 2 X5R 1 X5R 1 X5R 1 X5R 1 X5R V_SB1P1 C148 C111 C87 C134
L13 VDD11S[18] FLSH_VDD18S[3] AE13 402 402 402 402 402 V_SB1P8 10 UF
20%
1 UF
10%
1 UF
10%
4.7 UF
10%
L14 VDD11S[19] 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
DP_VDD11[0] E7 603 402 402 603
C7 DP_VDD18[0] DP_VDD11[1] E8
X861949-001 BGA515 D7 DP_VDD18[1] DP_VDD11[2] F9
A X861949-001 BGA515 A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
KIC: DECOUPLING D
V_SB1P8
V_1P1STBY V_SB1P1 V_3P3STBY V_1P8STBY
C84 C165
C 1
C180
2 1
C163
2
1
C85
2
1 2 1 2
1
C143
2 C
1 UF 10% 1 UF 10%
4.7 UF 10% 6.3 V 6.3 V 1 UF 10%
4.7 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 6.3 V X5R 402 402 X5R
X5R X5R 603 402
603 402
C94 C184
C70 1 2 1 2 C197
C114 C152 1 2 1 2
1 2 1 2
1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10%
4.7 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 6.3 V X5R 402 402 X5R
X5R X5R 402 402
603 402 C110 C157
C78 1 2 1 2 C149
C150 C139 1 2 1 2
1 2 1 2
1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10%
1 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 6.3 V X5R 402 402 X5R
X5R X5R 402 402
402 402 C92 C189
C156 1 2 1 2 C201
C140 1 2 1 2
1 2 C171
1 2 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10%
1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 1 UF 10% X5R X5R
X5R 6.3 V 402 402
X5R 402 402
402
B C161
402
1
C115
2
1
C89
2 1
C113
2
1
C196
2 B
1 2 C172
1 2 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10%
1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 1 UF 10% X5R X5R
X5R 6.3 V 402 402
X5R 402 402
402
402 C105 C91
C153 1 2 1 2 C200
C127 1 2 1 2
1 2 C128
1 2 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10%
1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 1 UF 10% X5R X5R
X5R 6.3 V 402 402
X5R 402 402
402
402 C122 C168
1 2 1 2 C154
C126 1 2
1 2 C187
1 2 1 UF 10% 1 UF 10%
6.3 V 6.3 V 1 UF 10%
1 UF 10% X5R X5R 6.3 V
6.3 V 1 UF 10% X5R
X5R 6.3 V 402 402
X5R 402
402
402 C132
C170 1 2
1 2 C194
1 2
1 UF 10%
1 UF 10% 6.3 V
6.3 V 1 UF 10% X5R
X5R 6.3 V 402
402 X5R
402 C124
1 2
C183
1 2 1 UF 10%
6.3 V
1 UF 10% X5R
6.3 V 402
A X5R
402 C133
A
1 2
1 UF 10%
6.3 V
X5R
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ETHERNET CONTROLLER
D 1
FT2
FTP V_3P3_ENET
D
1 DB78 PLACE 0.1UF CLOSE TO PINS 11, 23 AND 32
PLACE 4.7UF CLOSE TO PINS 11 AND 32
V_3P3_ENET V_3P3_ENET 1 1 1 1 1
C502 C482 C477 C505 C12
DEBUG 0.1 UF 0.1 UF 0.1 UF 4.7 UF 4.7 UF
1 R33 10% 10% 10% 10% 10%
RED = 1 GBPS LINK 10 KOHM U28 IC 2
16 V
2
16 V
2
16 V
2
6.3 V
X5R 2
6.3 V
X5R
GREEN = 10 MBPS LINK 1% X5R
402
X5R
402
X5R
402 603 603
NO INDICATION FOR 100 MBPS LINK 2 CH RTL8111HM
1 2 R357 402 44 MDIP3 9 MDIP3 V_1P0_ENET
DEBUG 36 IN M2_PWR_EN 1 2 BI MDIN3 10
76 44 BI MDIN3
D1 0 OHM 5% 44 MDIP2 6 MDIP2
LED 1 402 EMPTY BI MDIN2 7 PLACE 0.1UF CLOSE TO PINS 3, 8, 22 AND 30
RED-GREEN 3 FT1 FTP 44 BI MDIN2
4 MDIP1 4
SM 44 BI MDIP1
44 MDIN1 5 MDIN1 AVDD33_2 32
BI MDIP0 1 11
1
C481
1
C491
1
C485
1
C496
1
C30
1
C10
44 BI MDIP0 AVDD33_1
44 MDIN0 2 MDIN0 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1 UF 4.7 UF
BI 10% 10% 10% 10% 10% 10%
16 V 16 V 16 V 16 V 6.3 V 6.3 V
22 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
DEBUG DVDD10 402 402 402 402 402 603
R26
ENET_LED2_R 1 2 ENET_LED2 25
C 511 OHM 1% ENET_GPO 26
LED2
LED1/GPO AVDD10_3 30 C
ENET_LED0_R 402 CH DEBUG
2 1 R17 ENET_LED0 27 LED0 AVDD10_2 8 PLACE 0.1UF
R36 511 OHM 1% AVDD10_1 3 CLOSE TO PIN 24 C480
39 IN ENET_REF_CLK 2 1 CH 402 1
DB4
1 2 V_3P3_ENET V_3P3_ENET
100 OHM 1% R35 1
402 CH 2 1 ENET_RSET 31 23 0.1 UF 10% FTP FT12
RSET VDDREG 16 V
2.49 KOHM 1% X5R 1
1 R366
CH 402 402 DB3 10 KOHM
24 1% 1 R383
REGOUT
2 CH 10 KOHM
ENET_XTAL2 29 CKXTAL2 402 1%
2 1 ENET_XTAL1 28 CKXTAL1 LANWAKE_N 21 ENET_WAKE_N 2 CH
R37 402
0 OHM 5% ENET_ISOLATE_N 20 ISOLATE_N CLKREQ_N 12 ENET_CLKREQ_N
402 EMPTY
2 PEX_SOC_ENET_TP_C 13 HSIP HSOP 17 C37 REF CLK CONTROLLED BY SMC
IN PEX_SOC_ENET_TN_C 14 18 PEX_ENET_SOC_TP 1 2 PEX_ENET_SOC_TP_C
2 IN HSIN HSON OUT 2
1
FT9 FTP
76 36 PCIE_RST_N
IN
SOFT START
NOM. VOLTAGE: 3.3V
MAX POWER: 590MW
U30 V_3P3_ENET
V_3P3 FET
SOT23
X889118-002
2 3
1 1
1
C47 1 C32 C31
0.22 UF 10 UF
1 UF 10% 20%
10% 25 V 6.3 V
6.3 V 2 X7R 2 X5R
A
2 X5R
402
603 603 A
R61
V_ENET_G 1 2 V_ENET_G_R
100 OHM 1%
1 R67 402 CH
20 KOHM
1%
2 CH
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_1P8STBY
NOTES: R403
1. MMC_X NETS ARE NEEDED TO IMPROVE PAD ADHESION
USING 13 MIL TRACES CONNECTED TO DB PADS
10 KOHM
1%
10 KOHM
1%
2
2
CH
CH
1
1
402
R463
402
EMMC MEMORY
2. EMMC DATA,CMD AND CLK SIGNALS ROUTED 10 KOHM
1%
2 1 R424
402
THROUGH MULTIPLE PADS TO PROVIDE SIGNAL ESCAPE CH
CH
1 R429
402 D
CONSIDERING NEW EMMC MEMORY PARTS FOR VALIDATION 10 KOHM
1%
2 1 R441
402 V_1P8STBY
CH
V_1P8STBY 10 KOHM 2 1 R436
1% 402
CH
10 KOHM 2 1 R454 1 1 1
1 1 1 1
R417 1 1%
CH
402
C119 C542 C118 C166 C120 C177 C182
10 KOHM 10 KOHM 2 1 R451 0.1 UF 0.1 UF 2.2 UF 1 UF 0.1 UF 0.1 UF 2.2 UF
1% 1% 402 10% 10% 20% 10% 10% 10% 20%
CH U3 EMMC_BASE IC 16 V 16 V 6.3 V 6.3 V 2 16 V
2 16 V
2 6.3 V
CH 2 10 KOHM 2 1 R447 EMMC_BASE 2 X5R 2 X5R 2 X5R 2 X5R X5R X5R X5R
402 1% 402 R466 EMMC_153PIN 402 402 402 402 402 402 402
CH 1 2
43 MMC_DATA<7> 1 of 3
EMMC_BASE 0 OHM 5% VCCQ4 P5 V_3P3STBY
R426 402 CH VCCQ3 P3
43 MMC_DATA<6> 1 2 VCCQ2 N4
EMMC_BASE 0 OHM 5% VCCQ1 M4
R434 402 CH VCCQ0 C6
1 2 1 1 1
43 MMC_DATA<5> C136 C145 C162
K9 0.1 UF 0.1 UF 2.2 UF
0 OHM 5% EMMC_BASE VCC3 10% 10% 20%
402 CH R446 VCC2 F5 16 V 16 V 6.3 V
MMC_DATA<4> 1 2 43 MMC_DATA_R<7> B6 E6 2 X5R 2 X5R 2 X5R
43 DATA7 VCC1 402 402 402
EMMC_BASE 0 OHM 5% 43 MMC_DATA_R<6> B5 DATA6 VCC0 J10
R440 402 CH 43 MMC_DATA_R<5> B4 DATA5
MMC_DATA<3> 1 2 43 MMC_DATA_R<4> B3 C2 VDDI_BYPASS
C 43
EMMC_BASE 0 OHM 5% 43 MMC_DATA_R<3> B2
DATA4
DATA3
VDDI 43
C
R458 402 CH MMC_DATA_R<2> A5 DATA2 VSS10 J5
43 MMC_DATA<2> 1 2 MMC_DATA_R<1> A4 DATA1 VSS9 A6 1
MMC_DATA_R<0> A3 P4 C158
0 OHM 5% EMMC_BASE DATA0 VSS8 1 UF
402 CH R452 VSS7 N2 10% SMT ICT PADS
MMC_DATA<1> 1 2 MMC_DS H5 C4 6.3 V
43 DATA_STROBE VSS6 2 X5R 1 MMC_DATA<7>
N5 FT35 FTP 43
EMMC_BASE 0 OHM 5% VSS5 402 1 MMC_DATA<2>
M5 G5 FT34 FTP 43
R450 402 CH CMD VSS4 1 MMC_DATA<1> 43
43 MMC_DATA<0> 1 2 43 MMC_CMD_R VSS3 P6 FT33 FTP
M6 E7 1 MMC_DATA<0> 43
0 OHM 5% CLK VSS2 FT31 FTP
K8 1 MMC_DATA<4> 43
R413 402 CH 43 MMC_CLK_R VSS1 FT30 FTP
1 2 K5 H10 1 MMC_DATA<3> 43
43 MMC_CMD RSTN VSS0 FT28 FTP
1 MMC_DATA<5> 43
0 OHM 5% MMC_RST_N_R FT26 FTP
1 MMC_DATA<6> 43
402 CH R421 X939723-001 BGA153 FT25 FTP
1 2 1 MMC_CLK 39 43
43 39 MMC_CLK FT23 FTP
IN FT21 FTP
1 MMC_CMD 43
0 OHM 5% 1 MMC_RST_N 43
R410 402 CH FT17 FTP
43 MMC_RST_N 1 2
1 KOHM 1%
402 CH
B U3 EMMC_BASE IC U3 EMMC_BASE IC
B
EMMC_153PIN EMMC_153PIN
2 of 3 3 of 3
U2 KIC IC DB115 1 MMC_X7 A1 NC0 NC35 E1
MMC_DATA<7..0> 43 43 MMC_DATA_R<4> A2 NC1 NC36 E2 A7 RFU1 NC80 M8
5 of 12 BI A8 E3 43 MMC_DATA_R<6> C5 M9
I446 NC2 NC37 NC106 NC81
A9 NC3 NC38 E12 E5 RFU3 NC82 M10
MMC_DATA7 AE18 7 A10 E13 E8 M11
6 NC4 NC39 RFU4 NC83
MMC_DATA6 AD15 A11 NC5 E14 E9 M12
5 NC40 RFU5 NC84
MMC_DATA5 AE15 A12 NC6 F1 E10 M13
4 NC41 RFU6 NC85
MMC_DATA4 AD16 A13
MMC_DATA3 AF16 3 DB116 1 MMC_X6 NC7 NC42 F2 F10 RFU7 NC86 M14
DB114 1 MMC_X4 A14 NC8 NC43 F3 G3 RFU8 NC87 N1 MMC_X11 1
MMC_DATA2 AF18 2 B1 F12 G10 N3 DB107
1 43 MMC_DATA_R<3> NC9 NC44 RFU9 NC88
MMC_DATA1 AD17 B7 NC10 F13 N6
0 NC45 NC89
MMC_DATA0 AE17 MMC_DATA_R<7> B8 F14 MMC_X8 1 N7
43 NC11 NC46 DB112 NC90
B9 NC12 NC47 G1 K6 RFU12 NC91 N8
MMC_CMD AF14 MMC_CMD 43
BI B10 NC13 NC48 G2 K7 RFU13 NC92 N9
B11 NC14 NC49 G12 K10 RFU14 NC93 N10
MMC_RESET_N AE14 MMC_RST_N 43
OUT B12 NC15 NC50 G13 P7 RFU15 NC94 N11
B13 NC16 NC51 G14 MMC_X9 1 DB111 P10 RFU16 NC95 N12
DB113 1 MMC_X5 B14 NC17 NC52 H1 L1 NC70 NC96 N13
X861949-001 BGA515 43 VDDI_BYPASS C1 NC18 NC53 H2 L2 NC71 NC97 N14 MMC_X3 1
C3 NC19 NC54 H3 43 MMC_CMD_R L3 NC72 NC98 P1 MMC_X10 1 DB106
C7 NC20 NC55 H12 L12 NC73 NC99 P2 MMC_X12 1 DB105
C8 NC21 NC56 H13 L13 NC74 NC100 P8 DB103
C9 NC22 NC57 H14 MMC_X13 1 DB110 L14 NC75 NC101 P9
C10 NC23 NC58 J1 M1 NC76 NC102 P11
C11 NC24 NC59 J2 M2 NC77 NC103 P12
C12 J3 M3 P13 MMC_X2 1
A C13
NC25
NC26
NC60
NC61 J12 M7
NC78
NC79
NC104
NC105 P14 MMC_X1 1 DB102
DB104
A
C14 NC27 NC62 J13
MS_PART# MATL REF_DES DESCR. BOM PROPERTY D1 NC28 NC63 J14 MMC_X14 1 DB109 X939723-001 BGA153
X934261-001 IC U3 MEM,8GB,EMMC,FLASH,15NM,BGA153,TOSHIBA EMMC_TOSHIBA_15NM 43 MMC_DATA_R<5> D2 NC29 NC64 K1
ZZ400
I660
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: RJ45,TOSLINK
D D
V_5P0_GATED
J8 CONN
RJ45_10P_4MH
44 42 MDIP0 1 TD1_P
BI MDIN0 2
44 42 BI TD1_N
44 42 MDIP1 3 TD2_P 1
BI MDIN1 4 C9
44 42 BI TD2_N 1 UF J7 CONN
10%
44 42 MDIP2 7 TD3_P 2
6.3 V SPDIF_3P_4MH
BI MDIN2 8
X5R
402 VCC 2
44 42 BI TD3_N
MT1 4
MDIP3 9
C 44 42
44 42
BI
BI MDIN3 10
TD4_P
TD4_N MT1 11
SPDIF_OUT 3
MT2 5
6 C
12 3 IN VIN MT3
MT2 7
RJ45_CT 5 13 MT4
CT1 MT3
1
6 CT2 MT4 14 EG5 1 1
1
C28 X882235-001 C8 GND
0.01 UF X949832-002 EMPTY 22 PF
10% EG9 402 5% X949831-001
16 V TH EMPTY 50 V
2
2 X7R 2 NPO TH
402 SP3010 402
44 42 MDIP2 1 D1A
BI 10 D1B
44 42 MDIN2 2 D2A
BI 9 D2B
44 42 MDIP3 4 D3A
BI 7 D3B
EG8
EMPTY
SP3010
44 42 MDIP0 1 D1A
BI 10 D1B
44 42 MDIN0 2 D2A
BI 9 D2B
44 42 MDIP1 4 D3A
BI 7 D3B
A A
CONNECT As TO Bs
X863136-001
DFN10
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EG26
ESD ARRAY
CONN: USB (FRONT & REAR)
SP3010
1
34 OUT BOUT_P BIN_P 45 EG14
A 0.1 UF 10%
7 BOUT_N BIN_N 5 USB3_FP_P0_RN 45 45 34 BI USB2_FP_P0_DP
USB2_FP_P0_DN
9
11
10
12
X882235-001 A
16 V 45 34 BI
X5R 12 C1 13 14
402 EMPTY
6 C2 GND 9 USB3_FP_P0_TN_CMC 15 16
402
USB3_FP_P0_TP_CMC 17 18
2
C1092
34 OUT USB3_FP_P0_RN_BUFF 1 2 USB3_FP_P0_RN_BUFF_C X949696-001 FILT U80 19 20
0.1 UF 10%
QFN12 ECMF02_2HSMX6
16 V USB3_FP_P0_TP_BUFF 6 D+_IC D+_CONN 1 SM
X5R USB3_BUFF_C1 USB3_BUFF_C2
V_SOC1P8 402
V_SOC1P8 USB3_FP_P0_TN_BUFF 5 D-_IC D-_CONN 2
R608 R345 R341 R343 3 GND NC 4
1 2 1 2 1 2 1 2 NC
10 KOHM 1% 10 KOHM 1% 10 KOHM 1% 10 KOHM 1% X900532-002 MICROSOFT PROJECT NAME PAGE CSA FAB VER
402 EMPTY 402 EMPTY 402 CH 402 EMPTY
DFN6 PAGE
CONFIDENTIAL Cactus 45/82 45/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: WIFI
D D
J18 HDR
2X3HDR_CACTUS
34 USB2_WIFI_DP 1 USB2_DP
BI USB2_WIFI_DN 2
34 BI USB2_DN
3 GND_1
4 GND_2
36 WIFI_RESET_N 5 RESET_N
IN 6 V_3P3STBY
C
1
R183 1
EG10 EG11 EG12
M1007350-001 C
10 KOHM TH
5% EMPTY EMPTY EMPTY
EMPTY 2 402 402 402
402
2
V_3P3STBY
C371 1 C357 1
1 UF 22 UF
10% 20%
6.3 V 6.3 V
X5R 2 X5R 2
402 805
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CONN: HDMI IN
EG7 EG6
ESD ARRAY ESD ARRAY
SP3010 SP3010
35 TMDS_RX_DN1 1 D1A
OUT 10 D1B 35 OUT TMDS_RX_CLKN 1 D1A
10 D1B
35 TMDS_RX_DP1 2 D2A
OUT 9 D2B 35 OUT TMDS_RX_CLKP 2 D2A
9 D2B
35 TMDS_RX_DN2 4 D3A
OUT 7 D3B 35 OUT TMDS_RX_DN0 4 D3A
7 D3B
35 TMDS_RX_DP2 5 D4A GNDA 3
OUT 6 D4B GNDB 8 35 OUT TMDS_RX_DP0 5 D4A GNDA 3
6 D4B GNDB 8
C C
CONNECT As TO Bs
CONNECT As TO Bs
X863136-001 X863136-001
48 35 HDMI_CEC DFN10
BI DFN10
J3 CONN
HDMI_19P_6MH
12 TMDS_CLK_DN
11 TMDS_CLK_SHD
V_3P3STBY 10 TMDS_CLK_DP
9 TMDS_DATA0_DN
8 TMDS_DATA0_SHD
7 TMDS_DATA0_DP
6 TMDS_DATA1_DN
5 TMDS_DATA1_SHD
C474 4 TMDS_DATA1_DP
0.1 UF
1 R14 1 R363 1 R369 10% U74 IC 3 TMDS_DATA2_DN
B 10 KOHM 2 KOHM 2 KOHM
16 V
X5R
402
HDMI2C2_5F2 2
1
TMDS_DATA2_SHD
B
1% 1% 1% TMDS_DATA2_DP
2 CH 2 CH 2 CH C4 VDD_IC CEC A2 13 CEC
402 402 402 14 UTILITY MT1 20
36 HDMI_RX_DDC_CLK A4 SCL_IC SCL A1 HDMI_RX_DDC_CLK_CONN 15 SCL MT2 21
OUT HDMI_RX_DDC_DATA A3 B1 HDMI_RX_DDC_DATA_CONN 16 22
36 BI SDA_IC SDA SDA MT3
17 DDC/CEC_GND MT4 23
36 HDMI_RX_DDC_5V_E C3 ENABLE_IC 5V_IN C1 18 +5V_POWER MT5 24
BI 1 R38 1 R358 19 25
1 R16 47.5 KOHM 47.5 KOHM HOT_PLUG_DET MT6
HPD C2 100 KOHM 1% 1%
C7 1% 2 2 X949828-002 SM
1 UF CH CH
GND B2 10% 2 CH 402 402
16 V 402 HDMI_RX_DDC_5V
X5R
X903998-001 402
FOR R38 AND R358:
WLCSP10 SPEC=47K, 20% TOLERANCE
R15
35 HDMI_RX_HPD 1 2 HDMI_RX_HPD_PIN
IN
1 KOHM 1%
402 CH
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SELECTED A1/A0
--> 00
01
7-BIT ADDRESS
0X5E
0X5D
8-BIT ADDRESS
BC/BD
BA/BB
V_1P1STBY_HDMI U29
TDP158
3 OF 3
POWER
IC
1
V_3P3STBY V_5P0 EG24 HDMI_TX_SDA_CONN 16 SDA MT3 22
X882235-001 17 DDC/CEC_GND MT4 23
V_5P0_HDMI_OUT 18 +5V_POWER MT5 24
DIO HDMI_TX_HPD_CONN 19 HOT_PLUG_DET MT6 25
402
2
1 C25
4.7 UF C478 X949828-002 SM
10%
603
0.1 UF R19
V_3P3STBY X5R 10% 1 2
2 6.3 V 16 V
X5R 0 OHM 5%
CH 402
402
HDMI_TX_SCL_BUF R18
HDMI_TX_SDA_BUF 1 2
1 R50 1 R54
2 KOHM 2 KOHM 0 OHM 5%
R52 1% 1% U21 IC CH 402
36 SB_DDC_CLK 1 2 2 CH 2 CH HDMIDP1_5F6
IN 402 402 C4 E1 1 C14
0 OHM 5% VDD_5V CEC
CH 402 C3 2.2 UF
R51 VDD_IC 20%
36 SB_DDC_DATA 1 2 6.3 V
BI HDMI_TX_SCL_R E5 D2 X5R
0 OHM 5% R_SCL_IC SCL 2 402
CH 402 HDMI_TX_SDA_R D5 C1
R_SDA_IC SDA
SOC_DDC_CLK C24 0.1 UF SOC_AUXP D4 A3
A
3 BI 402
X5R
10%
16 V E4
AUX_P
SCL_IC
5V_OUT
A
HDMI 5V LOAD SWITCH: 5V, 250MA MAX TDC
R382
36 OUT DP0_HPD_SB 1 2 3 BI SOC_DDC_DATA C15
402
0.1 UF SOC_AUXN
10%
D3
E2
AUX_N DP PWR LOAD SWITCH: 3.3V, 500MA MAX TDC
0 OHM 5% X5R 16 V SDA_IC
402 CH HPD A1
B5 HPD_IC
37 HDMIDPOUT_MODE_SEL A2 SELECT_IC GND B1
IN HDMI_V_5P0_EN A5 C2
36 IN ENABLE_IC GND
1
1 R48 1 R148
FT6 FTP 10 KOHM 10 KOHM M1004155-002
1% 1% WLCSP18
2 CH 2 CH
402 402
MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 48/82 48/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_1P1STBY V_1P1STBY_HDMI
R610
1 2
0 OHM 5%
1 402 CH 1
C799 C821
1 UF 1 UF
10% 10% V_5P0_GATED
C 2
6.3 V
X5R 2
6.3 V
X5R C
402 U81 EMPTY 402
NCP458R
VBIAS D1
V_3P3STBY V_3P3STBY_HDMI
R612
1 2
1 R600 0 OHM 5%
1 KOHM 402 CH 1
B 1% 1
C1218 C1219
2 CH
402
1 UF
10%
1 UF
10% B
6.3 V
6.3 V 2 X5R
2 X5R 402
402 U82 EMPTY
STMPS2151
5 IN OUT 1
FAULT_N 3 V_3P3STBY_HDMI_FLT_N 1
DB402
V_3P3STBY_HDMI_EN 4 EN GND 2
X912985-001
1 R633 SOT23-5
1.5 KOHM
1%
2 CH
402
A A
RE-DRIVER U29 R610 R612 U81 U82
PG1.0 M1003966-001 EMPTY EMPTY STUFF STUFF
PG1.1 M1003966-002 STUFF STUFF EMPTY EMPTY
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C379
HDD SATA
J19
1X7SATA_2MH
CONN: ODD & HDD
35 SATA1_HDD_TP 1 2 SATA1_HDD_TP_C 9
IN NO_M2 ODD 12V LOAD SWITCH
D 0.01 UF 10%
16 V
X7R
1
2 Q2 1 R156
NOM.VOLTAGE: 12V D
C378 FET
35 SATA1_HDD_TN 1 2 402 SATA1_HDD_TN_C 3 AON7403L 0 OHM
IN NO_M2 4
V_12P0 5%
X888142-002 EMPTY
0.01 UF 10% 5 2 603
16 V DFN5
X7R 6
402 7 3
C377
35 SATA1_HDD_RN 1 2 SATA1_HDD_RN_C 2 5 V_12P0_ODD 50
OUT NO_M2 8 1
OUT
0.01 UF 10% 1 1 1 R512 1 1 1 1
16 V C675 C247 30.1 KOHM C236 C244 C242 C243
X7R SM 1 UF 10 UF 1% 1 UF 10 UF 10 UF 10 UF
C376 402 10% 10% 10% 10% 10% 10%
SATA1_HDD_RP 1 2 SATA1_HDD_RP_C NO_M2 16 V 16 V 2 CH 25 V 16 V 16 V 16 V
35 OUT 2 X5R 2 X5R 402 X5R 2 2 X5R 2 X5R 2 EMPTY
4
NO_M2
603 805 603 805 805 805
0.01 UF 10%
16 V
ODD_PWR_EN_N_C
X7R ODD_PWR_EN_N_R
402
C222
ODD SATA
35 IN SATA0_ODD_TP 1 2 SATA0_ODD_TP_C J10 R158 R157
1X7SATA_2MH ODD_PWR_EN_N 1 2 1 2
0.01 UF 10% 9 3
16 V 2.49 KOHM 1% 100 OHM 1%
C221 X7R FT59 FTP
1 U44 402 CH 402 CH
C 35 IN SATA0_ODD_TN 1 2 402 SATA0_ODD_TN_C 1
2 36 IN 1
FET
C
0.01 UF 10% 3 2 SOT23-3
X889117-002
16 V
X7R C220 4
35 SATA0_ODD_RN 402 1 2 SATA0_ODD_RN_C 5
OUT 6
0.01 UF 10% 7
16 V
X7R
C219 402 8
35 SATA0_ODD_RP 1 2 SATA0_ODD_RP_C
OUT
0.01 UF 10% SM U45 ODD 5V LOAD SWITCH
16 V NOM.VOLTAGE: 5V
X7R V_5P0 R154 1 FET
ODD_PWR_EN
402 0 OHM SOT23-3
5% X889117-002
J17 EMPTY 2
1X5HDR2 805
3 2 V_5P0_ODD
V_5P0_HDD 1 OUT 50
50 IN 2
1
3
4 HDD POWER C248
1 UF
10%
V_12P0
C74 2
0.1 UF
10%
1
C241
4.7 UF
10%
2
C238
1 UF
1
1
25 V 6.3 V 10%
X5R 2 34.8 KOHM 6.3 V
402 X7R 1 X5R 1 2
R150 1
100 KOHM J9 ODD POWER & GPIOs 402 CH 1%
2
603 603 X5R
402
1% 2X6HDR_5KEY V_1P65_VREF 10
A CH 2
402
76 68 50 IN -
13
HDD_PWR_EN_C A
36 HDD_PWR_EN 11
ODD_WAKE_N 1 2 NC
IN + U34
36 OUT R151 LM339
36 IN ODD_OPEN 3 4 ODD_STATUS_R 1 2 ODD_STATUS
OUT 36 1 R395
6 ODD_3P3V_STBY_PULSE 50 100 OHM 1%
10 KOHM TSSOP14
1 7 8 V_5P0_ODD
IN 402 CH 1 R482 1% X932792-001
IN 50
C218 9 10 V_12P0_ODD 2 CH
75 PF IN 50 100 KOHM 402
5% 11 12 1%
1 1 1
50 V
NPO 2 C239 C235 C237 1 C208 2 CH
402 4.7 UF 1 UF 1 UF 1 UF 402
10% 10% 10% 10%
16 V 16 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
TH 805 603 402 402
MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 50/82 50/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
CONN: FRONT PANEL,FAN, AUDIO D
V_3P3STBY
V_5P0 V_3P3STBY
1
EG16
1
EG23 EG19 V_5P0 X949835-002
X882235-001
X882235-001 X882235-001 TH
EMPTY
1
EMPTY EMPTY EG15
402 R355
1
402 EG18 402 X882235-001 1 1 KOHM
2
2
2
1
EG22 X882235-001
1
EG17 1%
X882235-001 EMPTY EMPTY
X882235-001 2 402
EMPTY 402
2
EMPTY 402
EMPTY
2
402 36 LED_NEXUS
402 IN
1
EG13
R347
1 100 KOHM X882235-001
1%
EMPTY
B AUDIO
R598
CH
2 402 402 B
2
1 2
47 KOHM 1%
V_5P0 402
AUDIO_AMP_VREF EMPTY
1 AUDIO
C451 1 AUDIO 1 AUDIO
10 UF C439 C445
10% 0.1 UF 10 UF
16 V 10% 10%
2 X5R
805 25 V 16 V
2 X7R 2 X5R
AUDIO 603 805
AUDIO AUDIO AUDIO U69 IC V_12P0_GATED
R327 C442 R323
36 AUDIO_PWM_OUT 1 2 AUDIO_PWM_FILT 1 2 AUDIO_PWM_FILT_C 1 2 ISD8104
IN 2 VREF VDD 6
200 OHM 1% 1 UF 10% 6.19 KOHM 1% 1 POS
402 CH 16 V 402 CH 3 5 SPKR_AMP_OUT_VP V_3P3
X5R VIP VOUTP
AUDIO 1 AUDIO AUDIO_PWM_AMP_IN 4 8 SPKR_AMP_OUT_VN
C444 402 V_5P0 VIN VOUTN
1 R484 0.1 UF AUDIO 2 NEG 1 C464 1 C463
10 KOHM 10% R331 GND 7 1 R344 C454 100 UF 100 UF
1% 25 V 1 UF 20% 20%
2 X7R 1 2 AUDIO_AMP_CE 1 CE MPAD 9 4.7 KOHM 10% 16 V 16 V
2 CH 5% 16 V EMPTY
402 603 10 KOHM 1% 2 X5R TH 2 ELEC
TH
AUDIO 2 CH J24
402 CH X936772-001 SPKR1 402 603
SO9 1X4HDR
AUDIO
SPKR 1
C440
X913539-001 R342 2
1 2 36 FAN_TACH_IN 1 2 FAN_TACH_IN_R 3
OUT
A 1000 PF 10% 0 OHM 5% 4 A
50 V 402 CH R140
X7R AUDIO C459 1 36 IN FAN_PWM 1 2 FAN_PWM_R TH
402 R601 4700 PF
10% 33 OHM 1%
1 2 50 V 402 CH
X7R 2
47 KOHM 1% 402
402
EMPTY
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
CONN: POWER D
C C
M1007354-004
TH
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L18
1 2 V_VREG_12P0_NBCORE 61
OUT
0.47 UH IND
SM C462 1
270 UF C443
20% 10 UF
16 V 20%
POLY 25 V
TH 2 X5R
C 1206
C
L8
1 2 V_VREG_12P0_TO_5P0_3P3 62 66
V_GFXCORE
ST8 C1330
54 V_VREG_12P0_GFXCPU_SENSED 1 2 330 UF ST9
OUT 1 2 58 OUT V_VREG_12P0_MEMIOPHY_SENSED 1 2
SHORT 20% 2 V SHORT
EMPTY
SM
C1331
330 UF
1 2
20% 2 V
POLY
SM
C1332
330 UF
A A
20% 2 V
POLY
SM
C1333
330 UF
1 2
20% 2 V
POLY
SM
MICROSOFT PROJECT NAME PAGE CSA FAB VER
PAGE
CONFIDENTIAL Cactus 53/82 53/82 G-R 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D C206 R480
V_GFXCORE
D
VREG_GFXCORE_VDD1 0.8V-1.2V NOMINAL: 1V
1 UF
10% 2.2 OHM TDC: 136A EDC: 175A FSW: 700KHZ
6.3 V 603 CH C207
X7R 1% 1 UF
402 10%
6.3 V
55 GFX_AGND1 X7R VREG_GFXCORE_BST1
402
V_GFXCORE
1
ST_W15
SHORT
V_VREG_12P0_GFXCPU U41 IC C209
ST6
55 53 IN
57 56 1 1 1 MP86945A 1 UF
C211 C213 C210 C600 1 10%
0.47 UF 10 UF 10 UF 10 UF C214 23 VDRV VDD 21 6.3 V
2
V_3P3STBY 10% 10% 10% 10% 10 UF X7R
16 V 25 V 25 V 25 V 10%
25 402
X7R 2 X7R 2 X7R 2 X7R 25 V BST L5
402 1206 1206 1206
2 X7R
R142 1206 VREG_GFXCORE_SW1
1 10 KOHM 1 VIN SW 2
1% 16 VIN SW 3 150 NH IND
EMPTY SW 4 80 A TH
2 402 0.6 MOHM 1 R138
1 KOHM
54 IN VREG_GFXCORE_PWM1 17 PWM AGND 22GFX_AGND1 55 1%
R141 PGND 5 2 CH
R478 56 55 54 IN VREG_GFXCPU_SYNC VREG_GFXCORE_SYNC1 18 SYNC PGND 6 402
10 KOHM 7
C 1% 0 OHM CH PGND
EMPTY
402 5% PGND 8
9
C
402 PGND
PGND 10
54 VREG_GFXCORE_CS1
OUT PGND 11
PGND 12
R618 19 CS PGND 13
57 56 55 54 VREG_GFXCPU_TEMP 1 2 VREG_GFXCPU_TEMP1 20 VTEMP PGND 14
OUT 24 15
0 OHM 5% VREG_GFX_FAULT1 FAULT_N PGND
402 CH
R481 M1010495-002
QFN25
0 OHM 5%
402 CH
V_3P3STBY
ST_W15
SHORT
ST18
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D C226 R504 D
1 UF VREG_GFXCORE_VDD3
10%
6.3 V
X7R
2.2 OHM
402
603 CH C230
1% 1 UF
10%
6.3 V
56 GFX_AGND3 X7R VREG_GFXCORE_BST3
402
V_GFXCORE
1
ST_W15
U46 IC
SHORT
55 53 IN V_VREG_12P0_GFXCPU C231
ST7
57 56 1 1 1 MP86945A 1 UF
C233 C662 C659 C245 1 10%
0.47 UF 10 UF 10 UF 10 UF C246 23 VDRV VDD 21 6.3 V
10 UF X7R
2
10% 10% 10% 10%
16 V 25 V 25 V 25 V 10%
25 402
X7R 2 X7R 2 X7R 2 X7R 25 V BST L6
402 1206 1206 1206
2 X7R
1206 VREG_GFXCORE_SW3
1 VIN SW 2
16 VIN SW 3 150 NH IND
SW 4 80 A TH
0.6 MOHM V_GFXCORE
54 VREG_GFXCORE_PWM3 17 PWM AGND 22GFX_AGND3 56 0.8V-1.2V NOMINAL: 1V
IN 5
PGND
R503 56
54 VREG_GFXCPU_SYNC R152 VREG_GFXCORE_SYNC3 18 SYNC PGND 6 TDC: 136A EDC: 175A FSW: 700KHZ
10 KOHM 55 IN 7
C 1% 0 OHM CH PGND
EMPTY 402 5% PGND 8
9
C
402 PGND
54 VREG_GFXCORE_CS3 PGND 10
OUT 11
PGND
PGND 12
R614 19 CS PGND 13
57 56 55 54 VREG_GFXCPU_TEMP 1 2 VREG_GFXCPU_TEMP3 20 VTEMP PGND 14
OUT 24 15
0 OHM 5% VREG_GFX_FAULT3 FAULT_N PGND
402 CH
M1010495-002
R506 QFN25
0 OHM 5%
402 CH
V_3P3STBY
C259 R521
1 UF VREG_GFXCORE_VDD4
10%
B 6.3 V
X7R
402
2.2 OHM
603 CH C265 B
1% 1 UF
10%
6.3 V
56 GFX_AGND4 X7R VREG_GFXCORE_BST4
402
V_GFXCORE
1
ST_W15
SHORT
ST12
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
VREGS: CPUCORE OUTPUT PHASE D
V_3P3STBY
57 R556 VREG_CPUCORE_VDD1
1 2
2.2 OHM
603 CH
1% 1
C353
1 UF
10% V_CPUCORE
6.3 V
2 X7R
1 402 0.8V-1.2V NOMINAL: 0.95V
C349 57 CPU_AGND1
TDC: 15A EDC: 22A FSW: 700KHZ
1 UF
1
10% ST_W15
SHORT
6.3 V
ST25
2 X7R
402
C C
2
56 55 53 V_VREG_12P0_GFXCPU
IN
V_3P3STBY
1 1 1 1
C373 C992 C989 C372 C369
10 UF 10 UF 10 UF 10 UF 0.47 UF
10% 10% 10% 10% 10%
R191
1 10 KOHM 25 V 25 V 25 V 25 V 16 V U55 IC VREG_CPUCORE_BST
2 2 X7R 2 X7R 2 X7R X7R
1%
X7R
1206 1206 1206 1206 402
MP86905 V_CPUCORE
VDD 20
EMPTY
2 402
VDRV 22 C367
54 VREG_CPUCORE_PWM 1 UF
IN 1
10%
BST 6.3 V
X7R
R555 2 3 402 L13
VIN_1 SW_1
10 KOHM R190 14 VIN_2 SW_2 4 VREG_CPUCORE_SW
1% 54 IN VREG_GFXCPU_EN 1 2 VREG_GFXCPU_EN_R
EMPTY 0 OHM CH 150 NH IND
15 PWM AGND 21 CPU_AGND1 57 80 A TH
402 402 5% 16 5 1 R186
R189 EN PGND 0.6 MOHM
1 KOHM
VREG_CPUCORE_VDD1 VREG_CPUCORE_SYNC 19 6
B 57
0 OHM CH
SYNC PGND
PGND 7 1% B
402 5% 8 2 CH
VREG_CPUCORE_CS PGND 402
54 OUT 9
PGND
PGND 10
R615 17 CS PGND 11
56 55 54 VREG_GFXCPU_TEMP 1 2 VREG_CPU_PH_TEMP 18 VTEMP PGND 12
OUT VREG_CPU_FAULT1 23 13
0 OHM 5% FAULT_N PGND
402 CH R188
1 2 X930303-001
0 OHM 5% QFN23
402 CH
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
2
24 39 VREG_MEMIO_PWM2_R
2
VREG_MEMIOPHY_NB_IREF IREF PWM5
ST101
ST100
DB408 1 1
SHORT
R309 TP FTP FT406
SHORT
VREG_MEMPHY_IMON 21 IMONA
124 KOHM 1% 1
FTP FT407
1
2 22 45
1
402 CH VREG_MEMIO_IMON IMONB TEMP
C1079 SCB_MEMIO_ALT_S
1000 PF 1 R310
10% 50 V 25 ADDR_P MPAD 49 24.9 KOHM
402 X7R 1 1%
C438 1 R315
1 TP 0.01 UF 0 OHM
10% DB410
DB409 M1028736-002 2 CH
16 V TP 1 1 5%
QFN49 402 X7R FTP FT408 2 CH
402 402 R642 SOC_MEMIO_S
R306 2 1 14
IN
0 OHM 5%
124 KOHM 1% EMPTY 402
402 CH 2 R291
C1077 1 2 VREG_MEMPHY_PWM1
OUT 59
1000 PF 0 OHM 5%
10% 50 V R288
402 X7R 402 CH 1 2 VREG_MEMPHY_PWM2
1 OUT 59
0 OHM 5%
402 CH
R286
1 2 VREG_MEMIO_PWM1 60
OUT
A 0 OHM 5%
402 CH R271 A
1 2 VREG_MEMIO_PWM2 60
OUT
0 OHM 5%
402 CH
MP2949A I2C ADDRESS
MP2949A RAIL ASSIGNMENTS VREG_MEMIOPHY_NB_TEMP 59 60 61
7-BIT BASE R/W I2C ADDR 8-BIT HEX IN
RAIL 1: V_MEMPHY (POWER GROUP B)
WRITE 010 0010 0 0X22 0X44
RAIL 2: V_MEMIO (POWER GROUP A)
READ 010 0010 1 0X22 0X45
RAIL 3: V_NBCORE (POWER GROUP B)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C41
1 UF
10%
6.3 V
X5R
402 VREG_MEMPHY_BST2
60 59 53 V_VREG_12P0_MEMIOPHY V_MEMPHY
IN U31 IC C46
1 1 1 1 1 1 1 MP86901C 1 UF
C1277 C1279 C1281 C1282 C54 C506 C507 C59 1 10%
10 UF 10 UF 10 UF 10 UF 1 UF 10 UF 10 UF 10 UF C60 20 VCC BST 21 6.3 V
20% 20% 20% 20% 10% 20% 20% 20% 10 UF X5R
25 V 25 V 25 V 25 V 16 V 25 V 25 V 25 V 20%
1 2 402 L2
2 X5R 2 X5R 2 X5R 2 X5R X5R 2 X5R 2 X5R 2 X5R 25 V VIN_1 SW_1
1206 1206 1206 1206 2 X5R 3 VREG_MEMPHY_SW2
402 1206 1206 1206
1206
SW_2
14 VIN_2 SW_3 4
150 NH IND
R620 40 A SM
C 61 60 59 58 OUT VREG_MEMIOPHY_NB_TEMP 1 2 VREG_MEMPHY_TEMP2 17 VTEMP/FLT PGND_1 5
6
1 MOHM
C
0 OHM 5% PGND_2
58 IN 402 CH 58 OUT VREG_MEMPHY_CS2 18 CS PGND_3 7
PGND_4 8
R63 VREG_MEMPHY_PWM2 15 PWM PGND_5 9
10 KOHM PGND_6 10
1% 16 SYNC PGND_7 11
EMPTY PGND_8 12
402 19 13
AGND PGND_9
R62
61 60 59 58 VREG_MEMIOPHY_NB_SYNC VREG_MEMPHY_SYNC2
IN X901356-001 1
C12441 C12461 C12481 C1250 1 C1252 1 C1254 1 C1256 1 C1258 1 C1260 1 C1262 1 R304
0 OHM 5% QFN21 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 1 KOHM
402 CH 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 1%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 CH
805 805 805 805 805 805 805 805 805 805 402
V_3P3STBY
B V_MEMPHY: 0.9V
C424 B
TDC: 23A EDC: 30A FSW: 700KHZ
1 UF
10%
6.3 V
X5R
402
VREG_MEMPHY_BST1
60 59 53 V_VREG_12P0_MEMIOPHY V_MEMPHY
IN
1 1 1 1
1 1 1 1
U62 IC C425
C1275 C1276 C1278 C1280 1 UF
10 UF 10 UF 10 UF 10 UF C427
1 UF
C1074
10 UF
C1071
10 UF
C429
10 UF
C430
10 UF
MP86901C 10%
20% 20% 20% 20% 20 VCC BST 21 6.3 V
25 V 25 V 25 V 25 V 10% 20% 20% 20% 20%
2 2 2 2 16 V 25 V 25 V 25 V 25 V X5R
X5R X5R X5R X5R 2 2 2 2 402 L16
1206 1206 1206 1206 X5R X5R X5R X5R X5R 1 VIN_1 SW_1 2
402 1206 1206 1206 1206
SW_2 3 VREG_MEMPHY_SW1
14 VIN_2 SW_3 4
150 NH IND
R621 40 A SM
61 60 59 58 VREG_MEMIOPHY_NB_TEMP 1 2 VREG_MEMPHY_TEMP1 17 VTEMP/FLT PGND_1 5 1 MOHM
OUT 6
0 OHM 5% PGND_2
58 IN 402 CH 58 OUT VREG_MEMPHY_CS1 18 CS PGND_3 7
PGND_4 8
R267 VREG_MEMPHY_PWM1 15 PWM PGND_5 9
10 KOHM PGND_6 10
1% 16 SYNC PGND_7 11
EMPTY PGND_8 12
402 19 13
1
C12451 C12471 C12491 C1251 1 C1253 1 C1255 1 C1257 1 C1259 1 C1261 1 C1263
AGND PGND_9
R266 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
61 60 59 58 VREG_MEMIOPHY_NB_SYNC VREG_MEMPHY_SYNC1 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
IN X901356-001
A 0 OHM 5%
402 CH QFN21 2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
2
6.3 V
X5R
805
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C69
1 UF
10%
6.3 V
X5R
402 VREG_MEMIO_BST1
V_MEMIO
V_VREG_12P0_MEMIOPHY U32 IC C77
60 59 53 IN 1 UF
MP86901C 10%
1 1 1 1 1 1 1 1 20 21 6.3 V
C1268 C1270 C1272 C1274 C61 C508 C66 C509 C75 VCC BST X5R
10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 UF 402
20% 20% 20% 20% 20% 20% 20% 20% 10% 1 VIN_1 SW_1 2 L3
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 16 V 3 VREG_MEMIO_SW1
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R X5R SW_2
1206 1206 1206 1206 1206 1206 1206 1206 402 14 VIN_2 SW_3 4
150 NH IND
R617 40 A SM
VREG_MEMIO_TEMP1 17 VTEMP/FLT PGND_1 5 1 MOHM
61 60 59 58 VREG_MEMIOPHY_NB_TEMP 1 2
OUT PGND_2 6
C 58 IN
0 OHM 5%
402 CH 58 OUT VREG_MEMIO_CS1 18 CS PGND_3 7
8 C
PGND_4
R72 VREG_MEMIO_PWM1 15 PWM PGND_5 9
10 KOHM PGND_6 10
1% 16 SYNC PGND_7 11
EMPTY PGND_8 12
402 19 13
AGND PGND_9
R73
61 60 59 58 VREG_MEMIOPHY_NB_SYNC VREG_MEMIO_SYNC1
IN X901356-001
0 OHM 5% QFN21
402 CH
1
C12241 C12261 C12281 C1230 1 C1232 1 C1234 1 C12361 C12381 C12401 C12421 R79
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 1 KOHM
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
6.3 V
2 X5R
1%
805 805 805 805 805 805 805 805 805 805 2 CH
402
V_3P3STBY
V_MEMIO
1.35-1.5V NOMINAL: 1.5V
TDC(RETAIL): 20A EDC(RETAIL): 23A FSW: 700KHZ
B TDC(XDK): 25A EDC(XDK): 30A FSW: 700KHZ B
C423
1 UF
10%
6.3 V V_MEMIO
X5R
402 VREG_MEMIO_BST2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: NBCORE
D D
R591
VREG_NBCORE_S_RTN 1 2 SOC_NBCORE_S_RTN 14
U64 IC IN
TP
DB413 1 1 0 OHM 5%
MP2949A FTP FT100 402 CH
2 OF 2 1 R647
VORTNC 17 100 OHM
16 VREG_NBCORE_S 1%
VOSENC
2 CH
402
VFBC 15 VREG_NBCORE_VFB
R638 1 R646
1 2 VREG_NBCORE_PWM_R 38 PWM6 VDIFFC 14 VREG_NBCORE_VDIFF 200 OHM V_NBCORE
0 OHM 5% 1%
402 CH VREG_NBCORE_CS_SUM 20 CS_SUMC 2 CH R487
1 R645 402 1 2 SOC_NBCORE_S
IN 14
1.5 KOHM 0 OHM 5%
1% 402 CH
2 CH
402
VREG_NBCORE_CS 48 CS6
R257 ST400
V_3P3STBY PCB_NBCORE_S 1 2
R644 100 OHM 1%
1 2 VREG_NBCORE_IMON 23 IMONC SHORT
C 1 R658 402 CH
110 KOHM 1%
402 CH 2
FT411 FTP
DB416 M1028736-002
1 2 61 VREG_NBCORE_VDD C
C1300 TP 1 QFN49 2.2 OHM C1334 NEEDS TO BE GROUNDED TO THE GND CLOSE TO U59.21 (AGND)
1000 PF 603 CH 1
C1334
10% 50 V C401 1% 1 UF
1 402 X7R 1 UF 10%
10% 6.3 V NO SHORT BETWEEN C1334 AND GND IS NEEDED IF
6.3 V 2 X7R
X7R 402 C1334 IS GROUNDED TO THE SPECIFIC PLACE ON BOARD
402 MENTIONED ABOVE
53 V_VREG_12P0_NBCORE
IN U59 IC V_NBCORE
1 C393
C420 1
C416 1
C1064 1 C1061 1 C402 1 C405 1 C411 1 C1073 1
C1299 MP86905 1 2
10 UF VDD 20
20% 10 UF 10 UF 10 UF 1 UF 10 UF
10 UF 10 UF 10 UF
25 V 20% 20% 20% 10% 20% 20% 20% 20% 1 UF 10%
2 X5R 25 V 25 V 25 V 16 V 25 V 25 V 25 V 25 V 6.3 V 1
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R VDRV 22 FT73 FTP
1206 X7R
1206 1206 1206
B 402 1206 1206 1206 1206
BST 1 VREG_NBCORE_BST
402
DB128
1 B
L14
2 VIN_1 SW_1 3 VREG_NBCORE_SW
14 VIN_2 SW_2 4
VREG_NBCORE_PWM 150 NH IND 1 1
R654 15 PWM AGND 21
40 A
1 MOHM SM C1066
22 UF
C1283 1 C1284 1 C383 1 C382 1 C386 1 C381 R241
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 1 KOHM
58 VREG_MEMIOPHY_NB_EN 1 2 VREG_MEMIOPHY_NB_EN_R 16 EN PGND 5 20% 20% 20% 20% 20% 20% 20% 1%
R643 1 IN 19 6 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
0 OHM CH SYNC PGND 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S CH
10 KOHM 402 5% PGND 7 805 805 805 805 805 805 805 402
1% PGND 8
EMPTY 2 R256 PGND 9
402 60 59 58 IN VREG_MEMIOPHY_NB_SYNC 1 2 VREG_NBCORE_SYNC 10
PGND
0 OHM 5% 17 11 1K RESISTOR FOR LOAD WHEN SOC NOT POPULATED
R655 402 EMPTY CS PGND
61 VREG_NBCORE_VDD 1 2 VREG_NBCORE_TEMP 18 VTEMP PGND 12
0 OHM 5% 23 FAULT_N PGND 13
402 CH
X930303-001
R259 QFN23
60 59 58 VREG_MEMIOPHY_NB_TEMP 1 2
OUT
0 OHM 5%
402 CH R657
58 54 36 VREG_PWRGPAB_CPUGFX_PWRGD 1 2 VREG_NBCORE_FAULT_N
74 64 OUT
0 OHM 5%
402 EMPTY
A A
V_NBCORE
0.8V-1.2V NOMINAL: 0.95V
TDC: 16A EDC: 25A FSW: 700KHZ
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V5P0
D D
V_5P0
NOM. VOLTAGE: 5.1
R548 R547
C 36 OUT VREG_V5P0_PWRGD 1 2 VREG_V5P0_PWRGD_R 1 2
C
1 KOHM 1% 100 KOHM 1%
1
C1266 402 CH 402 CH
0.1 UF
10%
16 V
2 X5R
402
VREG_V5P0_VCC
V_VREG_12P0_TO_5P0_3P3 1 DB64
53 IN TP
66 C315
1 22 UF VREG_V5P0_BST_C
20%
6.3 V
1 1 1
U51 IC X5R 1 R177
C326 C969 C985 1 C363 1 C368 1
C346 1 C953 1 C341 1 C934 MP8759 2 805 3.32 OHM
1%
1
C301 V_5P0
0.1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 3 PG VCC 9 0.22 UF
10% 20% 20% 20% 20% 20% 20% 20% 20% 2 CH 10%
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 603 25 V
2 X7R 2 EMPTY 2 EMPTY 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 1 8 VREG_V5P0_BST 2 X7R
603 1206 1206 1206 1206 1206 1206 1206 1206 VIN BST 603 1
L10 DB60
1 2 1
SW 7 VREG_V5P0_SW FTP FT69
R549 1 ST19 V_5P0 2.2 UH IND SM
2
100 KOHM NC 4 NC VOUT 5 VREG_V5P0_VO 1 2 1 C325 1 C955 1 C347 1 C342 1 C332 1 C942 1 C917
SHORT
SHORT
1%
ST16
ST17
11 VREG_V5P0_FB 1 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
FB SHORT 10% 20% 20%
CH 2 12 20% 20% 20% 20%
B FT70 FTP
1
402 EN
AGND 10 VREG_V5P0_AGND 2
6.3 V
X5R
6.3 V
2 X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
2
6.3 V
2
6.3 V
B
1
VREG_V5P0_COMP_SW 402 805 805 805 X5R X5R X5R
6 MODE PGND 2 805 805 805
R546 R172 C324 1
VREG_V5P0_EN_R
VREG_V5P0_MODE
36 VREG_V5P0_EN 1 2 M1003845-001 200 KOHM 4700 PF FTP FT71
IN 10%
1
DB65
0 OHM 5% QFN12 1%
50 V
402 CH C897 1 R552 1 CH X7R C364 C365 C971 C970
0.1 UF 47.5 KOHM 402 402 22 UF 22 UF 22 UF 22 UF
1%
VREG_V5P0_SNS
10% VREG_V5P0_COMP 20% 20% 20% 20%
16 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R CH 2 X5R X5R X5R X5R
2 402
402 R180 805 805 805 805
VENABLE
499 OHM 1%
402 CH
R181 R178
R182
ENABLE START VOLTAGE = 3.86V 1 R609 5.76 KOHM 1% 54.9 KOHM 1% 0 OHM 5%
1
0 OHM 402 CH 402 CH 402 EMPTY
SHORT
5%
ST20
2 CH
402
2
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_5P0 V_3P3
U16 IC 1 DB9
1 R4 C3
1 UF AP7365 1
100 KOHM 10% FTP FT11
1% 16 V 3 VIN VOUT 4
2 EMPTY X5R
402 402 5 6
NC ADJ
R3 X897496-001 C2 1 1 R2
0 OHM DFN6 4.7 UF
31.6 KOHM
5% 10% 1%
CH 6.3 V
2
2 CH
VREG_3P3_EN
402 X5R
603
402
C 40 36 IN
C
VREG_3P3_ADJUST
1 R1
10 KOHM
1%
2 CH
402
V_3P3STBY
B V_SOC1P8 B
U71 IC 1
DB76
1
C1090 1 R602 LDF 1
FTP FT79
1 UF
10 KOHM 2 VIN VOUT 4
10% 5%
6.3 V 2 EMPTY 5
2 X5R 402 ADJ
402 1 R330
ldf
VREG_SOC1P8_ADJUST
1 R333
1.15 KOHM
1%
2 CH
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
VREGS: VSOCPHY/VFUSE D
V_SOCPHY
V_3P3STBY NOM. VOLTAGE: 0.95
U27 IC V_SOCPHY
RT8071A
2 VCC
L1
1 1 1 1 2
C483 C497 C490 3 VIN SW1 6 VREG_SOCPHY_SW
1 UF 10 UF 10 UF SW2 7
10% 20% 20% 1.5 UH IND 40 MOHM
6.3 V 6.3 V 6.3 V 3.3 A SM 1
2 X5R 2 X5R 2 X5R FB 1 C493 C486 1
C503 1
FTP FT14
402 603 603 22 UF 22 UF DB7
9 PGOOD 20% 20% 22 UF
6.3 V 6.3 V 20%
R381 X5R X5R 2
6.3 V
NC 8 1 2 VREG_SOCPHY_COMP_C 805 805 X5R
4 805
VREG_PWRGPAB_CPUGFX_PWRGD GND1 4.7 KOHM 5%
74 61 58 54 36 OUT 5
GND2 402 EMPTY
54 36 VREG_PWRGPB_EN 10 EN MPAD 11
IN 1
FTP FT13
1
C X865086-001 1
C40
2 1
C489 DB5
C
DFN11 2200 PF R497
220 PF 5% 10% 100 OHM
50 V 50 V 1%
NPO 402 2 EMPTY
402 CH
402
R68 R66
VREG_SOCPHY_FB 1 2 1 2 SOC_SOCPHY_S 14
IN
47.5 KOHM 1% 0 OHM 5%
R64 1 402 CH 805 EMPTY 1
82.5 KOHM TP
1% VENABLE DB415
CH 2
402
B B
V_3P3STBY
V_3P3 V_FUSE
1 VREG_PWRGPC_EN_R 3 2 C441
1 1 R596 1 C1084 1 R597
DB75 SHDN_N GND
4.7 UF
249 OHM 0.022 UF 1 KOHM
2 10%
1% 10%
25 V
1%
D9 1 R599 M1030948-001 6.3 V 2 CH EMPTY 2 EMPTY
20 KOHM X5R 2 402 2 402
1% SOT23-5 603
402
SOD123
2 2 EMPTY
1 MBR130L 402
36 VREG_PWRGPC_EN D7
IN VREG_VFUSE_ADJ
A
SOD123
1 MBR130L
A
39 IN V12P0_PWRGD 1 R595
10 KOHM
1%
2 CH
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3STBY
1
V_SB1P8
C116 1 R398 U33 IC
1 UF
10% 10 KOHM CAT6243DC
2
6.3 V 5% 4 VIN VOUT 2 1
X5R 2 EMPTY FTP FT16
402 1
402 1 1 R75 DB101
ADJ
R396 3 1.47 KOHM 1
C 63 58 36 IN VREG_PWRGPA_EN VREG_PWRGPA_EN_SB1P8 5 EN
GND1
GND2 6 1% C521
4.7 UF C
2 CH 10%
0 OHM 5% R397 402 6.3 V
402 CH 10 KOHM X854310-002 VREG_SB1P8_ADJ 2 X5R
5% DPAK-6 1 R76 603
EMPTY 1.15 KOHM
402 1%
2 CH
402
B B
V_3P3STBY
1
V_SB1P1
C232 U42 IC
1 UF
10% 1 R147 CAT6243DC
2
6.3 V
X5R
10 KOHM 4 VIN VOUT 2 1
402
5% 1
FTP FT55
2 EMPTY DB56
402 ADJ 1 1 R144 2
R143 GND1 3 825 OHM C234
68 36 VREG_1P1_ACTIVE_EN VREG_1P1_ACTIVE_EN_R 5 EN GND2 6 1% 4.7 UF
IN 2 CH 10%
0 OHM 5% 1 R146 402 1
6.3 V
X5R
402 CH 10 KOHM X854310-002 VREG_SB1P1_ADJ
603
5% DPAK-6
2 EMPTY 1 1 R145
402 C216 2 KOHM
0.1 UF 1%
10%
6.3 V 2 CH
2 EMPTY 402
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3STBY
NOM. VOLTAGE: 3.32
62 53 V_VREG_12P0_TO_5P0_3P3
IN
R195 R199
66 VREG_3P3STBY_AGND 66 2 1 VREG_3P3STBY_MODE 2 1 VREG_3P3STBY_VR5
C 49.9 KOHM 1%
CH 402
78.7 KOHM 1%
CH 402 C
C352
4.7 UF
1 R204 20%
10 KOHM 10 V
X5R
1% 402
2 CH V_3P3STBY
402
1 DB66
TP U54 IC
TPS56C215 C916
1 0.1 UF
C915 1 C912 1 C330 1 C327 1 C334 1 C333 1 C914 1
C329 1
C913 1 C328 17 VREG5 BOOT 1 VREG_3P3STBY_BST
10%
25 V
10 UF 10 UF 10 UF 10 UF 0.1 UF 0.1 UF 10 UF 10 UF 10 UF 10 UF 1
20% 20% 20% 20% 10% 10% 20% 20% 20% 20% 2 VIN_1 SW 6 X7R L11 DB57
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 603 1 2 1
2 EMPTY 2 EMPTY 2 X5R 2 X5R 2 X7R 2 X7R 2 X5R 2 X5R 2 X5R 2 X5R 11 VIN_2 SW 7 VREG_3P3STBY_SW FTP FT62
1206 1206 1206 1206 603 603 1206 1206 1206 1206 R192 1.5 UH IND SM
FB 13 VREG_3P3STBY_FB 1 C303 1 1 1 1 1 1
1 UF C284 C275 C268 C290 C289 C300
2
88.7 KOHM 1% 10% 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
SHORT
V_1P8STBY VREG_3P3STBY_SS 14 SS PGND 3 402 CH 20% 20% 20% 20% 20% 20%
ST26
6.3 V
PGND 4 C350 2 X5R 6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
1 2 402
2 X5R X5R X5R X5R X5R X5R
C351 1 15 EN PGND 5
8
805 805 805 805 805 805
1
0.015 UF PGND R193 1000 PF 10%
1 R202 +/-10% 16 9 50 V 1
B 0 OHM
5%
25 V
X7R 2
PGOOD PGND
PGND 10
19.6 KOHM
1% X7R
402 1
FTP FT68
DB61 B
VREG_3P3STBY_VO
402 66 VREG_3P3STBY_MODE 18 MODE AGND 12 CH
2 CH 1 1 1 1
402
402 C285 C299 C274 C267
22 UF 22 UF 22 UF 22 UF
M1002952-001 20% 20% 20% 20%
QFN18 66 VREG_3P3STBY_AGND 6.3 V 6.3 V 6.3 V 6.3 V
VREG_3P3STBY_EN 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805
1
2
FT72 FTP 1 1 R194
SHORT
1
ST23
DB67 C982 20 KOHM VENABLE
0.01 UF 1%
10%
16 V 2 EMPTY R201
2 X7R 402 1 2
1
402
0 OHM 5%
402 EMPTY
R203
67 VREG_3P3STBY_PG 2 1 VREG_3P3STBY_PG_R
OUT
100 OHM 1%
402 CH
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOD123 U36
V_5P0 MBR130L FET
V_1P1STBY
SOT23
D2 X889118-002 U38 IC
L4
2 VINMP2161ASW 3 VREG_1P1STBY_SW
2 1 VREG_1P1_1P8_STBY_FET 2 3
1 UH IND
OUT 5 8.7 A SM 1 1
SOD123 C203 C202
MBR130L 1 C175 1 C176 10 UF 10 UF 1
10 UF R115 8 EN FB 7 10% 10% FTP FT40
10% 10 UF 1 2 6.3 V 6.3 V
10% 2 X5R 2 EMPTY
6.3 V 6.3 V 4
EMPTY X5R 100 KOHM 1% PGND 805 805 1
2 805
402 CH 1 6 DB48
VREG_3P3STBY_PG 805 PG AGND
66 IN 1 R116
100 KOHM 1
1
X912372-001 FT45 FTP
C 1% C178
SHORT
SOT23-8 1 2 VREG_1P1STBY_FB_S C
ST3
2 CH 1
DB55
402 VREG_1P1STBY_EN
1 22 PF 5%
DB38 50 V
2
EMPTY
1 R106 1 402
10 KOHM C169
5% 4.7 UF R113 R114 R119
10% 1 2 VREG_1P1STBY_FB 1 2 1 2
VREG_1P8STBY_EN
2 EMPTY 6.3 V
402 2 EMPTY 226 KOHM 1% 196 KOHM 1% 0 OHM 5%
603 402 CH 402 CH 805 EMPTY
VENABLE
V_1P1STBY
FT37 FTP
1
V_1P8STBY
NOM. VOLTAGE: 1.13
VREG_1P1_1P8_STBY_VIN
C179 1
1 UF
10%
U39 IC 1
DB50
B 16 V AP2127KADJ 1
X5R
603 2 1 VIN VOUT 5 FTP FT44 B
4 C186
V_1P8STBY
ADJ
4.7 UF
10%
1 1 R474
23.2 KOHM
NOM. VOLTAGE: 1.83
3 SHDN_N GND 2 6.3 V 1
X5R 1% C588
603 2 CH 1000 PF
M1030948-001 2 10%
402 50 V
C185 1
1 R124 SOT23-5 1 2 X7R
0.1 UF
100 KOHM DB54 402
10% 1% FT46 FTP
1
25 V 2 EMPTY
EMPTY 2
603
402
VREG_1P8STBY_ADJ
1 R475
18 KOHM
1%
2 CH
402
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
STANDBY GATES
D D
4
603 805 603 805 805 805
V_12P0_GATED_EN_N_R
V_12P0_GATED_EN_N_C
C C
V_12P0
11.5 KOHM 1 UF
1% 10%
CH 6.3 V
V_5P0 2 402 2 X5R
U23 1 R60 V_5P0_GATED 402
FET
SOT23-3
0 OHM
5%
X889117-002
2 EMPTY
603
3 2
B C33 1 V_12P0 B
1 UF C29 2 C26 2 1
10% 0.1 UF 4.7 UF C13
6.3 V 10% 1 10% 1 UF
X5R R47 1 25 V 6.3 V 10%
402 2 34.8 KOHM X7R X5R 6.3 V
402 CH 1% 603
1 603
1 X5R 2
402
2
76 68 50 V_1P65_VREF 8
IN -
14 5P0_GATED_EN_C
9 + U34
LM339
TSSOP14
X932792-001
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IR BLASTER
D D
V_5P0
RT11
PTC
1206
X882908-001
V_3P3STBY 2
IR_BLAST_TIP_R
C V_3P3STBY C
1
C494
0.1 UF 1
1 R46
10%
16 V
C495
4.99 KOHM U24 IC 2 X5R
4700 PF
10%
1% SN74LVC1G08 402 50 V
2 X7R
2 CH VCC 5
402 FRONT_P_IR_EN 1 A 402 R56
Y 4 FRONT_P_IR_OUT 1 2 FRONT_P_IR_OUT_R
1 FB400
R371 1 FRONT_P_IR_IN 2 B
OUT 51 1000 OHM
10 KOHM 1 R57 0 OHM 5% 200 MA
1% 1 R372 GND 3 10 KOHM 402 CH
EMPTY 2 1% BEAD
402
0 OHM 2 402 J6 CONN
5% X864784-001 2 CH C19 R41 IR_JACK_3P
2 CH SOT23-5 402 0.01 UF 10%
10 OHM 1% 1 1
402 50 V 805 CH MH1 4
R58 1 2 IR_BLAST_SNUB 1 2 IR_BLAST_TIP 2 2 MH2 5
36 IR_BLAST_SMC_OUT 1 2
IN 805 MH3 6
0 OHM 5% X7R
IR_BLAST_SLEEVE 3 3 MH4 7
402 EMPTY
EG1 X949830-001
3
R362 TH
1 2 IR_BLAST_G1 1 U19 1 1
1
B C476 1 1 1
1
C1 C6
1.47 KOHM 1%
CH
XSTR 10 UF
10%
C5
10 PF
C23
10 PF
10 PF
5%
10 PF
5%
EG2 B
402 2 5% 5% X882235-001
1 R45 U20 16 V DIO 50 V 50 V
50 V 50 V 2 2 DIO
2
X5R 2 2 2 EMPTY EMPTY
10 KOHM XSTR 402
2
805 EMPTY EMPTY 402 402
1% 3 R359 402 402 402
2 CH 1 IR_BLAST_G2 1 2
402 221 OHM 1%
2 402 CH
R13
1 2 IR_BLAST_E1
15.8 OHM 1%
805 CH
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
I2C D
C C
V_3P3STBY
R169
DEBUG V_5P0
0 OHM 5%
J14 402 EMPTY
2X2HDR
78 73 58 54 48 36 SMBUS_CLK 1 2 R173
IN SMBUS_DATA 3 4 I2C_2X2_HDR_VDD 1 2
78 73 58 54 48 36 BI
0 OHM 5%
TH 402 EMPTY
X817161-001
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MARGIN: SOCPHY,SOC1P8
D D
C C
BLANK
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MONITOR: VSOC1P8,VSOCPHY,V12P0
D D
C C
BLANK
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3STBY
C 1
C1001 1
C1000 C
1 UF 1 UF
10% 10%
6.3 V 6.3 V
2 X5R 2 X5R
402 402
DEBUG_FACET
R207
39 36 OUT SMC_RST_N 1 2 J22
100 OHM 1% 2X13HDR
R206 402 CH SMC_RST_N_FACET 1 2
37 SPI_MISO 1 2 SPI_MISO_FACET 3 4 SPI_MOSI 37
IN SPI_SS_N 5 6
OUT
0 OHM 5% 37 OUT
402 CH 37 SPI_CLK 7 8 R404
OUT SB_TDI 9 10 SB_TDO_FACET 1 2 SB_TDO
R559 37 OUT IN 37
36 SMC_DBG_LED0_SWO 1 2 37 SB_TMS 11 12 33 OHM 1%
IN OUT SB_TCK 13 14 402 CH
33 OHM 1% 37 OUT
R560 402 CH SMC_DBG_LED0_SWO_FACET 15 16 KER_DBG_CTS 37 R485
KER_DBG_TXD 1 2 KER_DBG_TXD_FACET 17 18 KER_DBG_RTS_FACET
OUT 1 2 KER_DBG_RTS
37 IN IN 37
KER_DBG_RXD 19 20 FTDI_SMC_CTS
B 33 OHM 1%
402 CH
37
DB129
OUT 1 FTDI_SMC_TXD_FACET 21 22 FTDI_SMC_RTS
33 OHM 1%
402 CH B
R209 1 FTDI_SMC_RXD_FACET 23 24 R210
DB130
78 70 58 54 48 36 SMBUS_CLK 1 2 SMBUS_CLK_FACET 25 26 SMBUS_DATA_FACET 1 2 SMBUS_DATA 36 48 54 58 70 78
BI BI
0 OHM 5% 0 OHM 5%
402 CH SM 402 CH
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: SWITCHES
D D
DEBUG
SW1 V_5P0
TACT DEBUG
DEBUG
R185
1 2 EJECTSW_N_SW EJECTSW_N
OUT 36 51 DEBUG D4
DEBUG 2.49 KOHM 1% R513
402 CH 1 2 V_5P0STBY_LED_R 1 2
J15 C331
0.01 UF 2 KOHM 1%
1X2HDR 10% 402 CH GREEN
1 16 V
EMPTY SM
2 402 LED
TH
V_12P0
DEBUG
DEBUG D5
C 1
R187
2 V_12P0_LED_R 1 2 C
DEBUG 6.04 KOHM 1%
SW2 402 CH GREEN
SM
TACT DEBUG
LED
R184
1 2 74 PWRSW_N_SW PWRSW_N 36 51
OUT
2.49 KOHM 1%
402 CH V_5P0_GATED
C335
0.01 UF DEBUG
10%
16 V D6
EMPTY DEBUG
402 R250
1 2 CPUGFX_PWRGD_LED_R 1 2 CPUGFX_PWRGD_LED_R_D
2 KOHM 1%
402 CH GREEN
SM 3 DEBUG
LED
U58
FET
64 61 58 54 36 VREG_PWRGPAB_CPUGFX_PWRGD 1
IN
2 SOT23-3
B B
J20
2X3HDR
75 WARM_RESET_N 1 2
BI COLD_RESET_N 3 4
75 36 BI
74 PWRSW_N_SW 5 6
SM
DEBUG_HDT
X876507-001
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: HDT
D NOTE: INSTALL HEADER IF NEEDED
D
TITAN POWER CONNECTOR
V_3P3STBY
DEBUG_HDT
J12
1X2HDR
1
2
V_SOC1P8
TH
EMPTY
B V_SOC1P8 V_SOC1P8 B
V_SOC1P8
DEBUG_HDT DEBUG_HDT DEBUG_HDT DEBUG_HDT
1 V_SOC1P8 1
C865 C864 1 R535 1 R532
DEBUG_HDT DEBUG_HDT 0.22 UF DEBUG_HDT 0.22 UF 1 KOHM 1 KOHM
10% DEBUG_HDT 10% 1% 1%
DEBUG_HDT R179 1 U53 IC 6.3 V U49 IC U50 IC 6.3 V
47 KOHM 2 X5R 2 X5R 2 CH 2 CH
SW3 1% SN74AUP1G17 402 74LVC1G07 SN74AUP2G07 402 402 402
TACT CH 2 VCC 5 VCC 5 14 36 VCC 5
402
OUT
1 2 WARM_RESET_N 2 A Y 4 WARM_RESET_N_DEBOUNCE 2 A Y 4 SOC_RST_N 1 1A 1Y 6
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
CONN: M.2 D
MTG5
SPACER_1P
1
M1008483-001
TH
M2_ONLY
R325 SSD LOAD SWITCH SSD MOUNTING HARDWARE
1 2
NOM.VOLTAGE: 3.3V
0 OHM 5% PEAK CURRENT: 2.5A
805 EMPTY
X889324-001
NTTFS4C50N
M2_ONLY
DFN5
NOTE: R328 AND D8 ARE DEBUG COMPONENTS AND
FET
V_3P3STBY NEED TO BE REMOVED FROM RETAIL CONFIGS
Q3
M2_ONLY
J32
C 3
V_3P3_M2
PCIE_M2_M_RCPT_67P_2MH
2 1 C
5 2
M2_ONLY M2_ONLY 4 3
V_12P0 C434 C437
1
6 5 PEX_L3_M2_SOC_TN
OUT 2
1 UF 0.1 UF
M2_ONLY M2_ONLY M2_ONLY M2_ONLY M2_ONLY M2_ONLY
M2_ONLY 8 7 PEX_L3_M2_SOC_TP 2
10% 10%
C448 C1075 C1078 C449 C446
R637 1
M2_LED 10 9
OUT
6.3 V 25 V C450 10 KOHM
X5R 4.7 UF 1 UF 1 UF 1 UF 1 UF 22 UF 12 11 PEX_L3_SOC_M2_TN_C
4
X7R 1% 2
402 603 10% 10% 10% 10% 10% 20%
14 13 PEX_L3_SOC_M2_TP_C
IN
1 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V CH 2 IN 2
C519 X5R X5R X5R X5R X5R X5R 402 16 15
0.1 UF 603 402 402 402 402 805
18 17 PEX_L2_M2_SOC_TN 2
10% M2_ONLY 20 19 PEX_L2_M2_SOC_TP
OUT
25 V OUT 2
X7R 2 M2_ONLY 22 21
603 R78 1 R328
D8
24 23 PEX_L2_SOC_M2_TN_C
34.8 KOHM 1 2 M2_LED_R 1 2 IN 2
402 CH 1% 26 25 PEX_L2_SOC_M2_TP_C 2
511 OHM 1% 28 27
IN
3
2 402 CH
V_1P65_VREF 4 GREEN 30 29 PEX_L1_M2_SOC_TN
68 50 IN - V+ OUT 2
2 M2_ENABLE_C SM 32 31 PEX_L1_M2_SOC_TP
OUT 2
V_3P3 5 LED 34 33
+ V- U34 36 35 PEX_L1_SOC_M2_TN_C 2
LM339 38 37 PEX_L1_SOC_M2_TP_C
IN
12
3
1% 56 55 M2_PEX_SS_100M_CLKP
REF CLK CONTROLLED BY SSD IN 77
CH 2 U63 58 57
402 TO SUPPORT POWER MODE
FET EXPERIMENTS
RST_G_C 1
SOT23-3
3
2
M2_ONLY
U66 68 67
R318 FET
42 36 PCIE_RST_N 1 2 1 70 69
IN SOT23-3 72 71
100 OHM 1% 1 74 73
2
A
ISOLATION OF SIGNAL PCIE_RST_N IS NEEDED TO ISOLATE
SOUTHBRIDGE OUTPUT FROM SSD PULLUP
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D NOTES:
CLOCK BUFFER D
1.TO ENABLE ENET2 CLOCK ON J28 HEADER, UNSTUFF R85. U35 HAS INTERNAL PULL DOWN.
2.SEE PAGES 2 AND 79 FOR ADDITIONAL PCIE SPARE LANE INFORMATION V_SOC1P8
FB1
M2_ONLY1 2
U35 M2_ONLY IC 1000 OHM BEAD
R99 200 MA 402
39 ENET_CLKP 1 2 CLKP_BUFF_R 9DBV0541
IN 9
V_CLKBUFF V_SOC1P8
0 OHM 5% M2_ONLY VDDDIG1P8
V_SOC1P8 402 CH 1 M2_ONLY 1 M2_ONLY 1 M2_ONLY 1 M2_ONLY 1 M2_ONLY
VDDO1P8_1 16 C564 C550 C181 C568 C581
R95 25 0.1 UF 0.1 UF 0.1 UF 0.1 UF 10 UF
ENET_CLKN 1 2 CLKN_BUFF_R VDDO1P8_2 10% 10% 10% 10% 20%
M2_ONLY 39 IN 16 V 16 V 16 V 16 V 6.3 V 1 M2_ONLY 1 M2_ONLY
R85 1 0 OHM 5% M2_ONLY 5 4 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R C552 C125
402 CH CLK_IN_P VDDR1P8
10 KOHM 6 CLK_IN_N
402 402 402 402 603 0.1 UF 1 UF
1% VDDO1P8_3 21
10%
16 V
10%
6.3 V
CH 2 PLACE 0.1UF CAPS CLOSE TO EACH POWER PINS 2 2 X5R X5R
402 CLKBUFF_OE0_N 12 13 ENET2_PEX_SS_100M_CLKP 402 402
OE0_N DIF0_P OUT 79
DIF0_N 14 ENET2_PEX_SS_100M_CLKN
OUT 79
M2_ONLY R92
CLKBUFF_OE1_N 17 18 DIF1_P_R 1 2 ENET_PEX_SS_100M_CLKP
77 OE1_N DIF1_P OUT 39 42
19 DIF1_N_R
C DIF1_N 0 OHM 5%
402 CH 1
R96
2
M2_ONLY
ENET_PEX_SS_100M_CLKN C
CLKBUFF_OE2_N 24 22 DIF2_P_R OUT 39 42
77 OE2_N DIF2_P
V_SOC1P8 23 DIF2_N_R 0 OHM 5%
DIF2_N
M2_ONLY R101 402 CH
CLKBUFF_OE3_N 1 2 SOC_PEX_SS_100M_CLKP 2 39
77 29 OE3_N DIF3_P 27 DIF3_P_R OUT
DIF3_N 28 DIF3_N_R 0 OHM 5%
402 CH R104 M2_ONLY
CLKBUFF_OE4_N 1 2 SOC_PEX_SS_100M_CLKN 2 39
77 1 OE4_N DIF4_P 2 DIF4_P_R OUT
2 M2_ONLY M2_ONLY 3 DIF4_N_R 0 OHM 5%
2 DIF4_N
R87 R91 M2_ONLY R117 402 CH
10 KOHM 10 KOHM CKPWRGD_PD_N 1 2 SOC_NB_PEX_SS_100M_CLKP 2 39
1 77 31 CKPWRGD_PD_N GNDDIG 8 OUT
1% 402 1 1% 402 GNDA 20 0 OHM 5%
CH CH CLKBUFF_SCLK 10 SCLK_3P3 GNDR 7 402 CH R118 M2_ONLY
1 2 SOC_NB_PEX_SS_100M_CLKN 2 39
GND_1 15 OUT
CLKBUFF_SDATA 11 26 0 OHM 5%
SDATA_3P3 GND_2 M2_ONLY R103 402 CH
GND_3 30 1 2 M2_PEX_SS_100M_CLKP 76
CLKBUFF_ADDR 32 33
OUT
77 SADR_TRI MPAD 0 OHM 5% R100 M2_ONLY
402 CH 1 2 M2_PEX_SS_100M_CLKN
OUT 76
M1002304-002 QFN33 0 OHM 5%
402 CH
B B
R290 1 R295 1
10 KOHM M2_ONLY 10 KOHM M2_ONLY
1% 1% CLKBUFF_OE1_N 77
EMPTY 2 EMPTY 2
V_3P3STBY 402 402
CLKBUFF_OE4_N 77 V_SOC1P8
1 R574 CLKBUFF_OE2_N V_SOC1P8
3
77
M2_ONLY U65 10 KOHM
1%
R296 1 EMPTY 2 CH
10 KOHM REQ_G_C 1 CLKBUFF_OE3_N 77
1% SOT23-3 402 1 R594 1 R625
M2_ONLY 1 R624
3
10 KOHM 10 KOHM
2
2 CH
A M2_ONLY C435
0.022 UF 402 1 R623
10 KOHM CKPWRGD_PD_N
10% M2_ONLY 1% 77
50 V
2 EMPTY 2 CH
SSD CLOCK REQUEST LEVEL SHIFTER 402 402
M2_ONLY CLKBUFF_ADDR
M2_ONLY 77
R300
1 2 REQ_G_R
100 OHM 1%
402 EMPTY
M2_ONLY
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3STBY
1 DB124
X938523-001 QFP48
A
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_12P0 V_5P0
DEBUG
DEBUG
TP17 TP11 PCIE CONNECTORS
1
1
SM SM
V_3P3 V_1P8STBY J29
1X3HDR
DEBUG DEBUG ENET_PEX_SS_100M_CLKN
77 42 39 IN 1
TP1 TP7 2
1 1 77 42 39 ENET_PEX_SS_100M_CLKP 3
IN
SM SM SM EMPTY
V_SOC1P8 V_1P1STBY
DEBUG DEBUG
TP16 TP6
C 1 1 J28 EMPTY C
SM SM 2 PEX_SOC_SPARE_TP_C 1 1
IN PEX_SOC_SPARE_TN_C 2
2 IN 2
V_SOCPHY V_BAT 3 3
DEBUG DEBUG 2 PEX_SPARE_SOC_TP 4 4
OUT PEX_SPARE_SOC_TN 5
TP2 TP3 2 OUT 5
6 6
1 1
77 ENET2_PEX_SS_100M_CLKP 1 R630
2 ENET2_CLKP_R 7 7
IN ENET2_CLKN_R 8
0 OHM 5% 8
SM SM 402 EMPTY 9 9
10 10
V_SB1P1 V_FUSE 11 11
DEBUG DEBUG R356 1 R631 1 12 12
TP8 TP15 10 KOHM 49.9 OHM 13 13
1% 1% 14 14
1 1 EMPTY 2 EMPTY 2 15 15
402 402
16 16
SM SM
V_SB1P8 R629
DEBUG DEBUG 77 ENET2_PEX_SS_100M_CLKN 1 2 X900666-001
IN TH
TP5 TP12 0 OHM 5% R632 1
402 EMPTY
B 1 1 49.9 OHM
1% B
EMPTY 2
SM SM 402
V_3P3STBY
DEBUG DEBUG
TP10 TP18
1 1
NOTES: TO ENABLE 100 MHZ REF CLOCK ON HEADER J28:
SM SM
1.WHEN CLOCK BUFFER U35 IS INSTALLED: POPULATE R629 AND R630.
V_GFXCORE V_CPUCORE 2.WITHOUT CLOCK BUFFER INSTALLED:
DEBUG
DEBUG
TP9 TP19 A.POPULATE R631 AND R632.
1
1
V_NBCORE
B.WIRE JUMPER ETHERNET 100 MHZ CLOCK FROM HEADER J29.1 AND
SM SM DEBUG
J29.3 TO J28.8 AND J28.7 RESPECTIVELY.
V_MEMIO V_MEMPHY TP13
1 3.SEE PAGES 2 AND 77 FOR ADDITIONAL PCIE SPARE LANE INFORMATION.
DEBUG DEBUG
TP4 TP14 SM
1 1
SM SM
A A
NOTE: THESE TEST POINTS ARE NOT
TO BE USED FOR VOLTAGE REGULATOR
QUALIFICATION TEST POINTS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MT1
MTG_HOLE
PTH 1
EMPTY
HEAT SINK MOUNTING HOLES MT2
MTG_HOLE
SCREW BOSS
PTH 1
STD STD EMPTY
MTG2
C MTG_HOLE
MTG3
MTG_HOLE MT3
J25 CONN C
NC9 9 MTG_HOLE
SCREW_BOSS_3P
NC9 9 1 1
PTH 1
EMPTY EMPTY 2 2
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 EMPTY
3 3
STD MT4
MTG4
STD MTG_HOLE X900629-001
MTG_HOLE
MTG1
PTH 1 TH
MTG_HOLE
NC9 9 NC9 9 EMPTY
EMPTY EMPTY J23 CONN
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 SCREW_BOSS_3P
1 1
2 2
3 3
B X900629-001 B
TH
LB1
M1024596-331
GND PADS FOR HEATSINK ALIGNMENT PINS LABEL
1
1 1
DB400 DB401 35P23X7P03_TARGET
A
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
FRONT PANEL USB - NESTED PCB
FRONT_USB
J1B FRONT_USB
2X10RCPT SW
81 GND_USB 1 2 F_BINDSW_N 81 1
SW1B
81 F_USB3_RXN_CMC 3 4
81 F_USB3_RXP_CMC 5 6
81 GND_USB 2
7 8
4
81 F_USB2_DP 9 10
81 F_BINDSW_N 3 5 GND_USB 81
81 F_USB2_DN 11 12 GND_USB 81
C 13 14
FRONT_USB
X817806-001 C
F_USB3_TXN 15 16 SM
1
81 EG2B
81 F_USB3_TXP 17 18
F_VBUS 19 20 F_VBUS
X882235-001
81 81
DIO
SM 402
2
M1012628-001
GND_USB 81
FRONT_USB
MTG1B
STANDOFF
FRONT_USB GND_USB 1
81
J2B CONN
USB3_9P_7MH M1015027-002
B 81 F_VBUS
F_USB2_DN
1
2
VBUS
SM B
81 D-
FRONT_USB F_USB2_DP 3 10
81 D+ MH1
FILT U1B 4 11 FRONT_USB
GND MH2
ECMF02_2HSMX6 F_USB3_RXN 5 STDA_SSRX_N MH3 12 MTG2B
81 F_USB3_RXP_CMC 6 D+_IC D+_CONN 1 F_USB3_RXP 6 STDA_SSRX_P MH4 13 STANDOFF
7 GND_DRAIN MH5 14
81 F_USB3_RXN_CMC 5 D-_IC D-_CONN 2 81 F_USB3_TXN 8 STDA_SSTX_N MH6 15 81 GND_USB 1
81 F_USB3_TXP 9 STDA_SSTX_P MH7 16
81 GND_USB 3 GND NC 4 NC
X949833-004 GND_USB 81 M1015027-002
X900532-002 TH SM
DFN6 81 GND_USB
FRONT_USB
FRONT_USB EG1B
LB1B ESD ARRAY
M1023564-301 SP3010
LABEL
1 D1A
1
81 F_USB3_TXP 10 D1B
A 6P5X6P5_TARGET 2 D2A
81 F_USB3_TXN 9 D2B A
4 D3A
81 F_USB2_DN 7 D3B
5 D4A GNDA 3
81 F_USB2_DP 6 D4B GNDB 8 GND_USB 81
MS_PART# MATL REF_DES DESCR. BOM PROPERTY
M1033394-001 FR4 PCB1B PCB,CACTUS,FAB E RETAIL,FRONT USB,8 LAYERS,GI FRONT_USB
ZZ406
I14
CONNECT As TO Bs
X863136-001
DFN10
MICROSOFT PROJECT NAME PAGE CSA VER
PAGE
CONFIDENTIAL Cactus 81/82 81/82 0.991
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM DEFINITIONS
BOM DEFINTION D
D
AUDIO INCLUDES COMPONENTS FOR THE STANDARD AUDIO SOLUTION
AUDIO_PREM INCLUDES COMPONENTS FOR THE PREMIUM SE/LE SPEAKER SOLUTION
COMMON ALL COMPONENTS WITH NO BOM PROPERTY
DEBUG COMPONENTS REQUIRED FOR BRING UP & DEBUG
DEBUG_HDT HDT-RELATED DEBUG COMPONENTS
DEBUG_SHUNT COMPONENTS WHICH ARE ON DEBUG BOARDS, BUT ARE REMOVED/SHORTED ON RETAIL
EMMC_BASE DUMMY PLACE HOLDER FOR EMMC DEVICE & RESISTORS. NEVER USE THIS IN THE RECIPE FILE. SELECT ONE OF THESE INSTEAD: EMMC_HYNIX_16NM, EMMC TOSHIBA_15NM, EMMC SAMSUNG_14NM
EMMC_HYNIX_16NM HYNIX EMMC DEVICE
EMMC_SAMSUNG_14NM SAMSUNG EMMC DEVICE
EMMC_TOSHIBA_15NM TOSHIBA EMMC DEVICE
GDDR5_BASE DUMMY PLACE HOLDER FOR GDDR5. NEVER USE THIS IN THE RECIPE FILE. SELECT ONE OF THESE INSTEAD: EMMC_HYNIX_16NM, EMMC TOSHIBA_15NM, EMMC SAMSUNG_14NM
C GDDR5_HYNIX HYNIX GDDR5 MEMORY C
GDDR5_SAMSUNG SAMSUNG GDDR5 MEMORY
FRONT_USB COMPONENTS ON THE FRONT PANEL USB
KIC_BASE DUMMY PLACE HOLDER FOR KIC. NEVER USE THIS IN THE RECIPE FILE. USE ONE OF THESE INSTEAD: KIC_DEV OR KIC_RETAIL
KIC_DEV DEBUG VERSION OF KRAKEN
KIC_RETAIL RETAIL VERSION OF KRAKEN
M2_ONLY POPULATE TO SUPPORT AN M.2 INTERFACE
NO_M2 POPULATE WHEN THERE IS NO M2. INTERFACE
PCB_GI FAB TYPE: GOLD
PCB_OSP FAB TYPE: ORGANIC SOLDERABILITY PRESERVATIVE GREEN SOLDERMASK
PCB_OSP_BLACK FAB TYPE: ORGANIC SOLDERABILITY PRESERVATIVE BLACK SOLDERMASK
B RTC_RETAIL RTC CIRCUIT IMPLEMENTATION FOR RETAIL BOARDS B
RTC_XDK RTC CIRCUIT IMPLEMENTATION FOR XDK BOARDS
SOC_BASE DUMMY PLACE HOLDER FOR SOC. NEVER USE THIS IN THE RECIPE FILE. SELECT ONE OF THESE INSTEAD: EMMC_HYNIX_16NM, EMMC TOSHIBA_15NM, EMMC SAMSUNG_14NM
SOC_EMPTY DOES NOT STUFF ANUBIS
SOC_INCLUDE STUFFS ANUBIS
VR_FIXED SET ALL VRS TO FIXED VOLTAGES (NON-MARGINED). EXCLUDES V_MEMIO. MUST BE USED IN CONJUNCTION WITH NOT VR_MM
VR_MM ALLOWS MOST VRS TO BE MARGINED FOR M&M BOARDS. EXCLUDES V_MEMIO. MUST BE USED IN CONJUNCTION WITH NOT VR_FIXED
A
A
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