Toledo - Soc - Fabe - Retail (Series X pt2)

8 7 6 5 4 3 2 1
D
PAGE CONTENTS
1 COVER PAGE
PAGE CONTENTS
41 VREGS: V_GFXCORE OUTPUT PHASE 5 & 6
Toledo SoC D
2 SOC: PCIEX, CLOCKS 42 VREGS: V_GFXCORE OUTPUT PHASE 7 FAB E Retail
3
4
SOC: AUDIO, VIDEO
SOC: POWER: MEMIO,MEMPHY,SOC,MISC
43
44
VREGS: V_CPUCORE OUTPUT
VREGS: V_MEMIO, V_MEMPHY, V_SOC CONTROLLER
REV 1.03
5 SOC: POWER: GFXCORE 45 VREGS: V_MEMIO, V_MEMPHY, V_SOC SENSE
6 SOC: POWER: CPUCORE 46 VREGS: V_MEMPHY OUTPUT
7 SOC: POWER: VSS 47 VREGS: V_MEMIO OUTPUT
8 SOC: POWER: VSS 48 VREGS: V_SOC OUTPUT
9 SOC: POWER: VSS 49 VREGS: V_3P3STBY_SOC
10 SOC: MEMORY: PARTITION A & B 50 VREGS: V_SOC1P8, V_DRAM1P8
11 SOC: MEMORY: PARTITION C & D 51 VREGS: V_SOCPHY, V_FUSE
12 SOC: MEMORY: PARTITION E & F 52 CLOCK: PCIE 100MHZ SS
C 13 SOC: MEMORY: PARTITION G & H 53 CLOCK: PCIE 100MHZ NS C
14 SOC: MEMORY: PARTITION I & J 54 MARGIN: V_SOCPHY,V_SOC1P8, V_DRAM1P8
15 SOC: DEBUG, SB SIGNALS, VOLTAGE SENSE 55 MONITOR: V_SOC1P8, V_SOCPHY, V_12P0_SOC, V_DRAM1P8
16 SOC: DECOUPLING 56 MONITOR: M.2, CFEXPRESS
17 SOC: DECOUPLING 57 DEBUG: VR HEADERS, TEST POINTS, CONNECTORS
18 SOC: DECOUPLING 58 LABELS AND MOUNTING
19 MEMORY: GDDR6 CHANNEL A: 8GB 59 BOM DEFINITIONS
20 MEMORY: GDDR6 CHANNEL B: 16GB
21 MEMORY: GDDR6 CHANNEL C: 8GB RULES: (APPLIED WHEN POSSIBLE)
22 MEMORY: GDDR6 CHANNEL D: 16GB 1. MSB TO LSB IS TOP TO BOTTOM
2. WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
23 MEMORY: GDDR6 CHANNEL E: 16GB 3. ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
4. AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
B 24 MEMORY: GDDR6 CHANNEL F: 16GB 5. LANED SIGNALS ARE GROUPED ON SYMBOLS
6. TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS B
25 MEMORY: GDDR6 CHANNEL G: 16GB 7. SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8. SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
26 MEMORY: GDDR6 CHANNEL H: 8GB 9. UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
27 MEMORY: GDDR6 CHANNEL I: 16GB 12.SUFFIX _P FOR P JUNCTION
13.SUFFIX _EN FOR ENABLE
28 MEMORY: GDDR6 CHANNEL J: 8GB 14.'CLK' FOR CLOCKS, 'RST' FOR RESETS
15.PWRGD FOR POWER GOOD
29 MEMORY: SPI FLASH 16.REV AND FAB ARE SET USING CUSTOM VARIABLES
TOOLS>OPTIONS>VARIABLES
30 HDMI: VIDEO OUT
31 HDMI: LOAD SWITCHES
32 CONN: BOARD TO BOARD
33 CONN: POWER
34 CONN: M.2
35 CONN: SPDIF, CFEXPRESS
36 VREGS: V_3P3_GATED, V_3P3_CFX
37 VREGS: INPUT FILTERS
38 VREGS: V_CPUCORE, V_GFXCORE CONTROLLER A
A
DRAWING
Mon Nov 05 16:42:32 2018
MICROSOFT PROJECT NAME PAGE CSA FAB VER

PAGE
CONFIDENTIAL Toledo SoC 1/59 1/59 E Retail
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: PCIEX, CLOCKS

D D
C215
1 2 PEX_SOC_SPARE_TP_C
OUT
0.22 UF 10%
10 V
EMPTY
201 C217
1 2 PEX_SOC_SPARE_TN_C
OUT
0.22 UF 10%
10 V
EMPTY
C48 201
U1 1 2 PEX_SOC_ENET_TP_C
IC OUT 32
ARDEN 0.22 UF 10%
2 OF 35 10 V
X5R C53
PCI-EXPRESS 201 1 2 PEX_SOC_ENET_TN_C 32
IN PEX_SPARE_SOC_TP BM11 P_GPP_RX3_P P_GPP_TX3_P BL10 PEX_SOC_SPARE_TP OUT
PEX_SPARE_SOC_TN BN11 P_GPP_RX3_N P_GPP_TX3_N BM10 PEX_SOC_SPARE_TN 0.22 UF 10%
IN PEX_ENET_SOC_TP_C BK9 BN8 PEX_SOC_ENET_TP 10 V
32 IN P_GPP_RX2_P P_GPP_TX2_P X5R
32 PEX_ENET_SOC_TN_C BL9 P_GPP_RX2_N P_GPP_TX2_N BM8 PEX_SOC_ENET_TN 201 C629
IN PEX_L1_SB_SOC_TP_C BP6 BR8 PEX_L1_SOC_SB_TP 1 2 PEX_L1_SOC_SB_TP_C
C 32
32
IN
IN PEX_L1_SB_SOC_TN_C BR6
P_GPP_RX1_P
P_GPP_RX1_N
P_GPP_TX1_P
P_GPP_TX1_N BT8 PEX_L1_SOC_SB_TN
OUT 32
C
PEX_L0_SB_SOC_TP_C BN9 BP10 PEX_L0_SOC_SB_TP 0.22 UF 10%
32 IN P_GPP_RX0_P P_GPP_TX0_P 10 V
32 PEX_L0_SB_SOC_TN_C BP9 P_GPP_RX0_N P_GPP_TX0_N BR10 PEX_L0_SOC_SB_TN X5R
IN 201
PEX_L1_CFX_SOC_TP BN53 P_GPP_RX7_P P_GPP_TX7_P BP52 PEX_L1_SOC_CFX_TP C637
35 IN 1 2 PEX_L1_SOC_SB_TN_C 32
35 IN PEX_L1_CFX_SOC_TN BM53 P_GPP_RX7_N P_GPP_TX7_N BN52 PEX_L1_SOC_CFX_TN OUT
35 PEX_L0_CFX_SOC_TP BL55 P_GPP_RX6_P P_GPP_TX6_P BM56 PEX_L0_SOC_CFX_TP 0.22 UF 10%
IN PEX_L0_CFX_SOC_TN BL54 BM55 PEX_L0_SOC_CFX_TN 10 V
35 IN P_GPP_RX6_N P_GPP_TX6_N X5R
34 PEX_L1_M2_SOC_TP BR46 P_GPP_RX5_P P_GPP_TX5_P BT49 PEX_L1_SOC_M2_TP 201
IN PEX_L1_M2_SOC_TN BT46 BR49 PEX_L1_SOC_M2_TN C649
34 IN P_GPP_RX5_N P_GPP_TX5_N 1 2 PEX_L0_SOC_SB_TP_C
PEX_L0_M2_SOC_TP BP47 BR51 PEX_L0_SOC_M2_TP OUT 32
34 IN P_GPP_RX4_P P_GPP_TX4_P
34 PEX_L0_M2_SOC_TN BR47 P_GPP_RX4_N P_GPP_TX4_N BP51 PEX_L0_SOC_M2_TN 0.22 UF 10%
IN 10 V
PEX_CAL_VSS BN56 X5R
PEX_CAL_VSS 201 C658
1 2 PEX_L0_SOC_SB_TN_C 32
1 R500
OUT
200 OHM
M1090982-001 BGA2963 0.22 UF 10%
1% 10 V
X5R
2 CH 201
402 C1085
1 2 PEX_L1_SOC_CFX_TP_C 35
NOTE: OUT
THE FOLLOWING SIGNALS HAVE BEEN POLARITY 0.22 UF 10%
B SWAPPED AT THE CFX CONNECTOR C1087
10 V
X5R B
PINS 2,3: PEX_L1_CFX_SOC 1 2 201 PEX_L1_SOC_CFX_TN_C 35
PINS 5,6: PEX_L1_SOC_CFX OUT
PINS 16,17: PEX_L0_CFX_SOC 0.22 UF 10%
10 V
X5R C1082
201 1 2 PEX_L0_SOC_CFX_TP_C 35
OUT
U1 SOC_BASE IC 0.22 UF 10%
10 V
ARDEN 1
C1083
2
X5R
201
1 OF 35 PEX_L0_SOC_CFX_TN_C 35
OUT
CLOCKS 0.22 UF 10%
52 SOC_PEX_SS_100M_CLKP BP13 CLKIN_P
IN 10 V
X5R C1080
52 SOC_PEX_SS_100M_CLKN BN13 CLKIN_N 201 1 2 PEX_L1_SOC_M2_TP_C 34
IN OUT
0.22 UF 10%
10 V
53 SOC_PEX_NS_100M_CLKP BT11 CLKIN_NOSS_P C1081 X5R
IN 1 2 201 PEX_L1_SOC_M2_TN_C
OUT 34
53 SOC_PEX_NS_100M_CLKN BR11 CLKIN_NOSS_N
IN 0.22 UF 10%
10 V
M1090982-001 X5R
201 1
C1067
2
BGA2963 PEX_L0_SOC_M2_TP_C 34
OUT
0.22 UF 10%
10 V
C1068 X5R
1 2 201 PEX_L0_SOC_M2_TN_C 34
OUT
0.22 UF 10%
10 V
A X5R
201
A
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY

ZZ1008
I105
M1090982-001 IC U1 PROCSR, SOC, SM, 1100 BGA, ARDEN A0 SOC_INCLUDE
M1090982-001 EMPTY U1 PROCSR, SOC, SM, 1100 BGA, ARDEN A0 SOC_EMPTY
ZZ5
I107

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AUDIO, VIDEO

D D
C U1 IC
C
ARDEN
13 OF 35
VIDEO AND AUDIO
NC DP1_TX0_P BH5 DP1_TX0_P DP0_TX0_P BM46 TMDS_TX_DP2 30
DP1_TX0_N BH4 BN46 TMDS_TX_DN2
OUT
NC DP1_TX0_N DP0_TX0_N OUT 30
NC DP1_TX1_P BJ4 DP1_TX1_P DP0_TX1_P BL47 TMDS_TX_DP1 30
DP1_TX1_N BJ3 BM47 TMDS_TX_DN1
OUT
NC DP1_TX2_P BJ6 DP1_TX2_P DP0_TX2_P BN48 TMDS_TX_DP0 30
DP1_TX2_N BJ7 BP48 TMDS_TX_DN0
OUT
NC DP1_TX3_P BH8 DP1_TX3_P DP0_TX3_P BL48 TMDS_TX_CLKP 30
DP1_TX3_N BH9 BK48 TMDS_TX_CLKN
OUT
NC DP1_AUX_P BK11 DP1_AUX_P DP0_AUX_P BN49 SOC_DDC_CLK 30

DP1_AUX_N BJ11 BM49 SOC_DDC_DATA
BI
NC DP1_AUX_N DP0_AUX_N BI 30
NC 3V3_DP1_HPD BM6 3P3V_DP1_HPD 3P3V_DP0_HPD BT5 DP0_HPD 30

IN
NC DP2_TX0_P BM14 DP2_TX0_P HDA_SYNC BG16 HDA_SYNC NC
1
NC DP2_TX0_N BL14 DP2_TX0_N HDA_BCLK BH15 HDA_BCLK NC DB79 V_SOC1P8
NC DP2_TX1_P BR14 DP2_TX1_P HDA_SDI BG15 HDA_SDI NC
NC DP2_TX1_N BP14 DP2_TX1_N HDA_SDO BF15 HDA_SDO NC
DP2_TX2_P BK13 BL15 HDA_XI
B NC
NC DP2_TX2_N BL13
DP2_TX2_P
DP2_TX2_N
HDA_XI
HDA_RSTN BC14 HDA_RSTN
NC
NC
1 R1
1 KOHM B
NC DP2_TX3_P BG13 DP2_TX3_P 1%
NC DP2_TX3_N BH13 DP2_TX3_N HDA_XO BK15 HDA_XO NC 2 CH
DP_CAL_ZVSS BN4 DP_CAL_ZVSS 201
NC DP2_AUX_P BH14 DP2_AUX_P HDMI_EN_PIN_STRP BL5 HDMI_EN_PIN_STRP
NC DP2_AUX_N BJ14 DP2_AUX_N 1 R687 1 R163
3P3V_SPDIF BR42 SPDIF_OUT 35
3V3_DP2_HPD BK8 BT42 SPDIF_DETECT
OUT 200 OHM 1 KOHM
NC 3P3V_DP2_HPD 3P3V_SPDIF_DETECT IN 35 1% 1%
2 CH 2 EMPTY
M1090982-001 BGA2963 402 201
HDMI TO DP SIGNAL MAPPING

DVI PCB DP PCB
ROUTING ROUTING
ORDERING ORDERING PIN NAME
TMDS CLOCK - DP LANE 3 - DP0_TX3_N
TMDS CLOCK + DP LANE 3 + DP0_TX3_P
TMDS DATA0 - DP LANE 2 - DP0_TX2_N
TMDS DATA0 + DP LANE 2 + DP0_TX2_P
A TMDS DATA1 - DP LANE 1 - DP0_TX1_N A

TMDS DATA2 - DP LANE 0 - DP0_TX0_N

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: MEMIO,MEMPHY,SOC,MISC

V_3P3_GATED
D D
POPULATE R268 IF FILTER IS USED V_SOCPHY
VR SENSE NET
R268
1 2 VREG_SOC1P8_SNS 50
OUT 1
C972 C980
1
C977
0 OHM 5%
201 EMPTY 1 UF 1 UF 1 UF
20% 20% 20%
6.3 V 6.3 V 6.3 V
2 X5R X5R 2 X5R 1 1 1 1 1 1
201 201 201 C107 C108 C111 C112 C113 C114
1 R272 U1 IC 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
0 OHM 20% 20% 20% 20% 20% 20%
5%
ARDEN 2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
24 OF 35 X5R X5R X5R X5R X5R X5R
V_SOC1P8 2 CH V_SOC1P8_VDD 201 201 201 201 201 201
201 VDD_MISC
BN2 VDD_33_BN2 VDD_C_BT55 BT55
BM1 VDD_33_BM1 VDD_C_BR55 BR55
ST11 VDD_C_BR56 BR56
1 2 BT4 VDD_18_BT4
BT2 VDD_18_BT2
1 SHORT 1 1 1 1 1 1 BR1
C712 C715 C717 C987 C101 C990 C983 C32 VDD_18_BR1 V_BAT
22 UF FB714 22 UF 22 UF 22 UF 1 UF 1 UF 1 UF 1 UF BR2 VDD_18_BR2
20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 1 2 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 EMPTY 2 EMPTY 2 EMPTY 2 X5R 2 X5R 2 X5R X5R 2 X5R
BT53 VDD_C_EFUSE VDD_RTC BR4
603
8.5 OHM EMPTY 603 603 603 201 201 201 201
8 A 603
C 0.004 MOHM
M1090982-001 BGA2963 1
C645 C
1 UF
FB713 V_FUSE 20%
6.3 V
1 2 2 X5R
201
80 OHM EMPTY
5 A 805
0.01 OHM 1
C604
FB714, FB713 ARE FILTER STUFFING OPTIONS 1 UF
20%
IN CASE VDD18/SOC1P8 IS SENSITIVE TO RIPPLE VOLTAGE 6.3 V
2 X5R
THIS IS NOT EXPECTED TO BE NEEDED AS AMD HAS SINCE 201
PROVIDED A RIPPLE VOLTAGE REQUIREMENT OF <30MV PK-PK

U1 IC
V_MEMPHY ARDEN U1 IC U1 IC
23 OF 35 V_MEMPHY V_SOC V_SOC V_MEMIO
VDD_MEMP ARDEN ARDEN V_MEMIO
AA13 VDD_MEMP_AA13
16 OF 35 22 OF 35
AA43 VDD_MEMP_AA43 VDD_MEMP_N15 N15 VDD_SOC VDD_MEM
W15 VDD_SOC_W15 VDD_SOC_U28 U28 VDD_MEM_K9 K9
AB14 VDD_MEMP_AB14 VDD_MEMP_N16 N16
W16 VDD_SOC_W16 VDD_SOC_U31 U31 BF9 VDD_MEM_BF9 VDD_MEM_T10 T10
AB44 VDD_MEMP_AB44 VDD_MEMP_N18 N18
W19 VDD_SOC_W19 VDD_SOC_U32 U32 BF47 VDD_MEM_BF47 VDD_MEM_K41 K41
AC13 N20
B AC43
VDD_MEMP_AC13
VDD_MEMP_AC43
VDD_MEMP_N20
VDD_MEMP_N22 N22
W20
W23
VDD_SOC_W20 VDD_SOC_U35 U35
U36
BD45
AY10
VDD_MEM_BD45 VDD_MEM_R47 R47
L10 B
AD14 N24 VDD_SOC_W23 VDD_SOC_U36 VDD_MEM_AY10 VDD_MEM_L10
VDD_MEMP_AD14 VDD_MEMP_N24 W24 U39 AV47 K16
AD44 N26 VDD_SOC_W24 VDD_SOC_U39 VDD_MEM_AV47 VDD_MEM_K16
VDD_MEMP_AD44 VDD_MEMP_N26 W27 U40 AW47 K22
AE13 N28 VDD_SOC_W27 VDD_SOC_U40 VDD_MEM_AW47 VDD_MEM_K22
VDD_MEMP_AE13 VDD_MEMP_N28 W28 T15 AA11 K28
AE43 N30 VDD_SOC_W28 VDD_SOC_T15 VDD_MEM_AA11 VDD_MEM_K28
VDD_MEMP_AE43 VDD_MEMP_N30 W31 T17 AP10 K34
AF14 N32 VDD_SOC_W31 VDD_SOC_T17 VDD_MEM_AP10 VDD_MEM_K34
VDD_MEMP_AF14 VDD_MEMP_N32 W32 T18 AG11 R11
AF44 N34 VDD_SOC_W32 VDD_SOC_T18 VDD_MEM_AG11 VDD_MEM_R11
VDD_MEMP_AF44 VDD_MEMP_N34 W35 T21 AN47 K47
AG13 N36 VDD_SOC_W35 VDD_SOC_T21 VDD_MEM_AN47 VDD_MEM_K47
VDD_MEMP_AG13 VDD_MEMP_N36 W36 T22 AH46 Y45
AG43 N38 VDD_SOC_W36 VDD_SOC_T22 VDD_MEM_AH46 VDD_MEM_Y45
VDD_MEMP_AG43 VDD_MEMP_N38 W39 T25 AH10 L15
AH14 N40 VDD_SOC_W39 VDD_SOC_T25 VDD_MEM_AH10 VDD_MEM_L15
VDD_MEMP_AH14 VDD_MEMP_N40 W40 T26 AM45 L21
AH44 N41 VDD_SOC_W40 VDD_SOC_T26 VDD_MEM_AM45 VDD_MEM_L21
VDD_MEMP_AH44 VDD_MEMP_N41 V17 T29 AG47 L27
AJ13 P14 VDD_SOC_V17 VDD_SOC_T29 VDD_MEM_AG47 VDD_MEM_L27
VDD_MEMP_AJ13 VDD_MEMP_P14 V18 T30 AB10 L33
AJ43 P15 VDD_SOC_V18 VDD_SOC_T30 VDD_MEM_AB10 VDD_MEM_L33
VDD_MEMP_AJ43 VDD_MEMP_P15 V21 T33 AN11 J39
AK14 P17 VDD_SOC_V21 VDD_SOC_T33 VDD_MEM_AN11 VDD_MEM_J39
VDD_MEMP_AK14 VDD_MEMP_P17 V22 T34 AW11 J46
AK44 P19 VDD_SOC_V22 VDD_SOC_T34 VDD_MEM_AW11 VDD_MEM_J46
VDD_MEMP_AK44 VDD_MEMP_P19 V25 T37 AA47 P45
AL13 P21 VDD_SOC_V25 VDD_SOC_T37 VDD_MEM_AA47 VDD_MEM_P45
VDD_MEMP_AL13 VDD_MEMP_P21 V26 T38
AL43 P23 VDD_SOC_V26 VDD_SOC_T38
VDD_MEMP_AL43 VDD_MEMP_P23 V29 T41
AM14 VDD_MEMP_AM14 VDD_MEMP_P25 P25 VDD_SOC_V29 VDD_SOC_T41 M1090982-001 BGA2963
V30 VDD_SOC_V30 VDD_SOC_T42 T42
AM44 VDD_MEMP_AM44 VDD_MEMP_P27 P27
V33 VDD_SOC_V33 VDD_SOC_R15 R15
AN13 VDD_MEMP_AN13 VDD_MEMP_P29 P29
AN43 VDD_MEMP_AN43 VDD_MEMP_P31 P31
AP14 VDD_MEMP_AP14 VDD_MEMP_P33 P33
AP44 VDD_MEMP_AP44 VDD_MEMP_P35 P35
AR13 VDD_MEMP_AR13 VDD_MEMP_P37 P37
AR43 VDD_MEMP_AR43 VDD_MEMP_P39 P39
U15 VDD_SOC_U15 VDD_SOC_R28 R28
AT14 VDD_MEMP_AT14 VDD_MEMP_P42 P42
AT44 VDD_MEMP_AT44 VDD_MEMP_R13 R13
AU13 VDD_MEMP_AU13 VDD_MEMP_R42 R42
U20 R35
A AU43
AV14
VDD_MEMP_AU43 VDD_MEMP_R43 R43
T14
U23
VDD_SOC_U20
VDD_SOC_U23
VDD_SOC_R35
VDD_SOC_R36 R36 A
VDD_MEMP_AV14 VDD_MEMP_T14 U24 R39
AV44 T44 VDD_SOC_U24 VDD_SOC_R39
VDD_MEMP_AV44 VDD_MEMP_T44 U27 R40
AW13 U13 VDD_SOC_U27 VDD_SOC_R40
VDD_MEMP_AW13 VDD_MEMP_U13
AW43 VDD_MEMP_AW43 VDD_MEMP_U43 U43
AY14 VDD_MEMP_AY14 VDD_MEMP_V14 V14 M1090982-001 BGA2963
AY44 VDD_MEMP_AY44 VDD_MEMP_V44 V44
BA13 VDD_MEMP_BA13 VDD_MEMP_W13 W13
BA43 VDD_MEMP_BA43 VDD_MEMP_W43 W43
BB14 VDD_MEMP_BB14 VDD_MEMP_Y14 Y14
BB44 VDD_MEMP_BB44 VDD_MEMP_Y44 Y44
M1090982-001 BGA2963 PROJECT NAME PAGE CSA FAB VER

MICROSOFT PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: GFXCORE

V_GFXCORE
D V_GFXCORE D
U1 IC
ARDEN
V_GFXCORE U1 IC V_GFXCORE V_GFXCORE U1 IC V_GFXCORE 19 OF 35
ARDEN ARDEN VDD_GFX
17 OF 35 18 OF 35 AE22 VDD_GFX_AE22 VDD_GFX_AK26 AK26
VDD_GFX VDD_GFX AE24 VDD_GFX_AE24 VDD_GFX_AK28 AK28
BT21 VDD_GFX_BT21 VDD_GFX_BL25 BL25 BF38 VDD_GFX_BF38 VDD_GFX_AY27 AY27 AE26 VDD_GFX_AE26 VDD_GFX_AK30 AK30
BT23 VDD_GFX_BT23 VDD_GFX_BL27 BL27 BF40 VDD_GFX_BF40 VDD_GFX_AY29 AY29 AE28 VDD_GFX_AE28 VDD_GFX_AK32 AK32
BT25 VDD_GFX_BT25 VDD_GFX_BL29 BL29 BE22 VDD_GFX_BE22 VDD_GFX_AY31 AY31 AE30 VDD_GFX_AE30 VDD_GFX_AK34 AK34
BT35 VDD_GFX_BT35 VDD_GFX_BL39 BL39 BE32 VDD_GFX_BE32 VDD_GFX_AY41 AY41 AE40 VDD_GFX_AE40 VDD_GFX_AL21 AL21
BT37 VDD_GFX_BT37 VDD_GFX_BL41 BL41 BE34 VDD_GFX_BE34 VDD_GFX_AW21 AW21 AE42 VDD_GFX_AE42 VDD_GFX_AL23 AL23
BT39 VDD_GFX_BT39 VDD_GFX_BK22 BK22 BE36 VDD_GFX_BE36 VDD_GFX_AW23 AW23 AF22 VDD_GFX_AF22 VDD_GFX_AL25 AL25
BR21 VDD_GFX_BR21 VDD_GFX_BK24 BK24 BE38 VDD_GFX_BE38 VDD_GFX_AW25 AW25 AF24 VDD_GFX_AF24 VDD_GFX_AL27 AL27
BR22 VDD_GFX_BR22 VDD_GFX_BK26 BK26 BE40 VDD_GFX_BE40 VDD_GFX_AW27 AW27 AF26 VDD_GFX_AF26 VDD_GFX_AL29 AL29
BR23 VDD_GFX_BR23 VDD_GFX_BK28 BK28 BD21 VDD_GFX_BD21 VDD_GFX_AW29 AW29 AF28 VDD_GFX_AF28 VDD_GFX_AL31 AL31
C BR29
BR30
VDD_GFX_BR29 VDD_GFX_BK36 BK36
BK38
BD29
BD31
VDD_GFX_BD29 VDD_GFX_AW37 AW37
AW39
AF36
AF38
VDD_GFX_AF36 VDD_GFX_AL39 AL39
AL41 C
VDD_GFX_BR30 VDD_GFX_BK38 VDD_GFX_BD31 VDD_GFX_AW39 VDD_GFX_AF38 VDD_GFX_AL41
BR31 VDD_GFX_BR31 VDD_GFX_BK40 BK40 BD33 VDD_GFX_BD33 VDD_GFX_AW41 AW41 AF40 VDD_GFX_AF40 VDD_GFX_AM21 AM21
BR33 VDD_GFX_BR33 VDD_GFX_BJ22 BJ22 BD35 VDD_GFX_BD35 VDD_GFX_AV22 AV22 AF42 VDD_GFX_AF42 VDD_GFX_AM23 AM23
BR34 VDD_GFX_BR34 VDD_GFX_BJ24 BJ24 BD37 VDD_GFX_BD37 VDD_GFX_AV24 AV24 AG21 VDD_GFX_AG21 VDD_GFX_AM25 AM25
BR38 VDD_GFX_BR38 VDD_GFX_BJ30 BJ30 BC21 VDD_GFX_BC21 VDD_GFX_AV30 AV30 AG27 VDD_GFX_AG27 VDD_GFX_AM31 AM31
BP22 VDD_GFX_BP22 VDD_GFX_BJ36 BJ36 BC27 VDD_GFX_BC27 VDD_GFX_AV36 AV36 AG33 VDD_GFX_AG33 VDD_GFX_AM37 AM37
BP28 VDD_GFX_BP28 VDD_GFX_BH21 BH21 BC33 VDD_GFX_BC33 VDD_GFX_AV42 AV42 AG39 VDD_GFX_AG39 VDD_GFX_AN22 AN22
BP30 VDD_GFX_BP30 VDD_GFX_BH23 BH23 BC35 VDD_GFX_BC35 VDD_GFX_AU22 AU22 AG41 VDD_GFX_AG41 VDD_GFX_AN24 AN24
BP32 VDD_GFX_BP32 VDD_GFX_BH25 BH25 BC37 VDD_GFX_BC37 VDD_GFX_AU24 AU24 AH21 VDD_GFX_AH21 VDD_GFX_AN26 AN26
BP38 VDD_GFX_BP38 VDD_GFX_BH31 BH31 BB22 VDD_GFX_BB22 VDD_GFX_AU30 AU30 AH27 VDD_GFX_AH27 VDD_GFX_AN32 AN32
BP40 VDD_GFX_BP40 VDD_GFX_BH33 BH33 BB24 VDD_GFX_BB24 VDD_GFX_AU32 AU32 AH29 VDD_GFX_AH29 VDD_GFX_AN34 AN34
BN22 VDD_GFX_BN22 VDD_GFX_BH35 BH35 BB26 VDD_GFX_BB26 VDD_GFX_AU34 AU34 AH31 VDD_GFX_AH31 VDD_GFX_AN36 AN36
BN24 VDD_GFX_BN24 VDD_GFX_BH37 BH37 BB28 VDD_GFX_BB28 VDD_GFX_AU36 AU36 AH33 VDD_GFX_AH33 VDD_GFX_AN38 AN38
BN26 BH39 BB30 AU38 AH35 AN40
B BN28
VDD_GFX_BN26
VDD_GFX_BN28
VDD_GFX_BH39
VDD_GFX_BH41 BH41 BB32
VDD_GFX_BB30
VDD_GFX_BB32
VDD_GFX_AU38
VDD_GFX_AU40 AU40 AH37
VDD_GFX_AH35
VDD_GFX_AH37
VDD_GFX_AN40
VDD_GFX_AN42 AN42 B
BN30 VDD_GFX_BN30 VDD_GFX_BG21 BG21 BB34 VDD_GFX_BB34 VDD_GFX_AU42 AU42 AH39 VDD_GFX_AH39 VDD_GFX_AP22 AP22
BN32 VDD_GFX_BN32 VDD_GFX_BG23 BG23 BB36 VDD_GFX_BB36 VDD_GFX_AT21 AT21 AH41 VDD_GFX_AH41 VDD_GFX_AP24 AP24
BN34 VDD_GFX_BN34 VDD_GFX_BG25 BG25 BB38 VDD_GFX_BB38 VDD_GFX_AT23 AT23 AJ22 VDD_GFX_AJ22 VDD_GFX_AP26 AP26
BN40 VDD_GFX_BN40 VDD_GFX_BG31 BG31 BA22 VDD_GFX_BA22 VDD_GFX_AT29 AT29 AJ28 VDD_GFX_AJ28 VDD_GFX_AP32 AP32
BM21 VDD_GFX_BM21 VDD_GFX_BG33 BG33 BA24 VDD_GFX_BA24 VDD_GFX_AT31 AT31 AJ30 VDD_GFX_AJ30 VDD_GFX_AP34 AP34
BM31 VDD_GFX_BM31 VDD_GFX_BF22 BF22 BA34 VDD_GFX_BA34 VDD_GFX_AT41 AT41 AJ40 VDD_GFX_AJ40 VDD_GFX_AR35 AR35
BM33 VDD_GFX_BM33 VDD_GFX_BF24 BF24 BA36 VDD_GFX_BA36 VDD_GFX_AR21 AR21 AJ42 VDD_GFX_AJ42 VDD_GFX_AR37 AR37
BM35 VDD_GFX_BM35 VDD_GFX_BF26 BF26 BA38 VDD_GFX_BA38 VDD_GFX_AR23 AR23 AK22 VDD_GFX_AK22 VDD_GFX_AR39 AR39
BM37 VDD_GFX_BM37 VDD_GFX_BF28 BF28 BA40 VDD_GFX_BA40 VDD_GFX_AR25 AR25 AK24 VDD_GFX_AK24 VDD_GFX_AR41 AR41
BM39 VDD_GFX_BM39 VDD_GFX_BF30 BF30 BA42 VDD_GFX_BA42 VDD_GFX_AR27 AR27
BM41 VDD_GFX_BM41 VDD_GFX_BF32 BF32 AY21 VDD_GFX_AY21 VDD_GFX_AR29 AR29 M1090982-001 BGA2963
BL21 VDD_GFX_BL21 VDD_GFX_BF34 BF34 AY23 VDD_GFX_AY23 VDD_GFX_AR31 AR31
BL23 VDD_GFX_BL23 VDD_GFX_BF36 BF36 AY25 VDD_GFX_AY25 VDD_GFX_AR33 AR33
M1090982-001 BGA2963 M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: CPUCORE

D D
U1 IC U1 IC
V_CPUCORE V_CPUCORE V_CPUCORE ARDEN V_CPUCORE
ARDEN 21 OF 35
20 OF 35 VDD_CPU
VDD_CPU AA15 VDD_CPU_AA15 VDD_CPU_AC32 AC32
AF16 VDD_CPU_AF16 VDD_CPU_BJ16 BJ16
AA16 VDD_CPU_AA16 VDD_CPU_AC35 AC35
AF18 VDD_CPU_AF18 VDD_CPU_BK16 BK16
AF20 VDD_CPU_AF20 VDD_CPU_AY17 AY17
AG15 VDD_CPU_AG15 VDD_CPU_AY19 AY19
AG17 VDD_CPU_AG17 VDD_CPU_BA16 BA16
AA24 VDD_CPU_AA24 VDD_CPU_AD15 AD15
AG19 VDD_CPU_AG19 VDD_CPU_BA18 BA18
AH15 VDD_CPU_AH15 VDD_CPU_BA20 BA20
AH17 VDD_CPU_AH17 VDD_CPU_BB16 BB16
AH19 VDD_CPU_AH19 VDD_CPU_BB18 BB18
AJ16 VDD_CPU_AJ16 VDD_CPU_BB20 BB20
AJ18 VDD_CPU_AJ18 VDD_CPU_BC17 BC17
AJ20 VDD_CPU_AJ20 VDD_CPU_BC19 BC19
AK16 VDD_CPU_AK16 VDD_CPU_BD17 BD17
AK18 VDD_CPU_AK18 VDD_CPU_BD19 BD19
AB17 VDD_CPU_AB17 VDD_CPU_AD33 AD33
AK20 BE16
C AL15
VDD_CPU_AK20
VDD_CPU_AL15
VDD_CPU_BE16
VDD_CPU_BE18 BE18
AB18
AB21
VDD_CPU_AB18 VDD_CPU_AD34 AD34
AD37 C
AL17 BE20 VDD_CPU_AB21 VDD_CPU_AD37
VDD_CPU_AL17 VDD_CPU_BE20 AB22 AD38
AL19 BF16 VDD_CPU_AB22 VDD_CPU_AD38
VDD_CPU_AL19 VDD_CPU_BF16 AB25 AD41
AM15 BF18 VDD_CPU_AB25 VDD_CPU_AD41
VDD_CPU_AM15 VDD_CPU_BF18 AB26 AD42
AM17 BF20 VDD_CPU_AB26 VDD_CPU_AD42
VDD_CPU_AM17 VDD_CPU_BF20 AB29 AE16
AM19 BG17 VDD_CPU_AB29 VDD_CPU_AE16
VDD_CPU_AM19 VDD_CPU_BG17 AB30 AE18
AN16 BG19 VDD_CPU_AB30 VDD_CPU_AE18
VDD_CPU_AN16 VDD_CPU_BG19 AB33 AE20
AN18 BH17 VDD_CPU_AB33 VDD_CPU_AE20
VDD_CPU_AN18 VDD_CPU_BH17 AB34 Y17
AN20 BH19 VDD_CPU_AB34 VDD_CPU_Y17
VDD_CPU_AN20 VDD_CPU_BH19 AB37 Y18
AP16 BJ18 VDD_CPU_AB37 VDD_CPU_Y18
VDD_CPU_AP16 VDD_CPU_BJ18 AB38 Y21
AP18 BJ20 VDD_CPU_AB38 VDD_CPU_Y21
VDD_CPU_AP18 VDD_CPU_BJ20 AB41 Y22
AP20 BK18 VDD_CPU_AB41 VDD_CPU_Y22
VDD_CPU_AP20 VDD_CPU_BK18 AB42 Y25
AR15 BK20 VDD_CPU_AB42 VDD_CPU_Y25
VDD_CPU_AR15 VDD_CPU_BK20 AC15 Y26
AR17 BL17 VDD_CPU_AC15 VDD_CPU_Y26
VDD_CPU_AR17 VDD_CPU_BL17 AC16 Y29
AR19 BL19 VDD_CPU_AC16 VDD_CPU_Y29
VDD_CPU_AR19 VDD_CPU_BL19 AC19 Y30
AT15 BM17 VDD_CPU_AC19 VDD_CPU_Y30
VDD_CPU_AT15 VDD_CPU_BM17 AC20 Y33
AT17 BM19 VDD_CPU_AC20 VDD_CPU_Y33
VDD_CPU_AT17 VDD_CPU_BM19 AC23 Y34
AT19 BN16 VDD_CPU_AC23 VDD_CPU_Y34
VDD_CPU_AT19 VDD_CPU_BN16 AC24 Y37
AU16 BN18 VDD_CPU_AC24 VDD_CPU_Y37
VDD_CPU_AU16 VDD_CPU_BN18 AC27 Y38
AU18 BN20 VDD_CPU_AC27 VDD_CPU_Y38
VDD_CPU_AU18 VDD_CPU_BN20 AC28 Y41
AU20 BP16 VDD_CPU_AC28 VDD_CPU_Y41
VDD_CPU_AU20 VDD_CPU_BP16 AC31 Y42
AV16 BP18 VDD_CPU_AC31 VDD_CPU_Y42
VDD_CPU_AV16 VDD_CPU_BP18
B AV18
AV20
VDD_CPU_AV18 VDD_CPU_BP20 BP20
BR17 M1090982-001 BGA2963 B
VDD_CPU_AV20 VDD_CPU_BR17
VDD_CPU_BR19 BR19
AW17 VDD_CPU_AW17 VDD_CPU_BT17 BT17
AW19 VDD_CPU_AW19 VDD_CPU_BT19 BT19
M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: VSS

D D
U1 IC U1 IC U1 IC U1 IC
ARDEN ARDEN ARDEN ARDEN
25 OF 35 26 OF 35 27 OF 35 28 OF 35
VSS VSS VSS VSS
BT6 VSS_BT6 VSS_BN17 BN17 BK17 VSS_BK17 VSS_BG2 BG2 BE37 VSS_BE37 VSS_BB19 BB19 AY38 VSS_AY38 VSS_AU3 AU3
BT16 VSS_BT16 VSS_BN23 BN23 BK23 VSS_BK23 VSS_BG8 BG8 BD2 VSS_BD2 VSS_BB25 BB25 AT13 VSS_AT13 VSS_AU9 AU9
BT18 VSS_BT18 VSS_BN25 BN25 BK25 VSS_BK25 VSS_BG11 BG11 BD4 VSS_BD4 VSS_BB27 BB27 AY46 VSS_AY46 VSS_AU10 AU10
BT22 VSS_BT22 VSS_BN29 BN29 BK29 VSS_BK29 BD8 VSS_BD8 VSS_BB31 BB31 AY50 VSS_AY50 VSS_AU15 AU15
BT30 VSS_BT30 VSS_BN37 BN37 BK37 VSS_BK37 VSS_BG24 BG24 BD20 VSS_BD20 VSS_BB39 BB39 AW1 VSS_AW1 VSS_AU23 AU23
C BT43
BT47
VSS_BT43 VSS_BN54 BN54
BM2
BJ2
BJ5
VSS_BJ2 VSS_BG36 BG36
BG38
BD32
BD34
VSS_BD32 VSS_BB52 BB52
BB54
AW16
AW18
VSS_AW16 VSS_AU35 AU35
AU37 C
VSS_BT47 VSS_BM2 VSS_BJ5 VSS_BG38 VSS_BD34 VSS_BB54 VSS_AW18 VSS_AU37
BT48 VSS_BT48 VSS_BM5 BM5 BJ9 VSS_BJ9 VSS_BG40 BG40 BD36 VSS_BD36 VSS_BB56 BB56 AW20 VSS_AW20 VSS_AU39 AU39
BT51 VSS_BT51 VSS_BM9 BM9 BJ13 VSS_BJ13 VSS_BG42 BG42 BD38 VSS_BD38 VSS_BA1 BA1 AW22 VSS_AW22 VSS_AU41 AU41
BR5 VSS_BR5 VSS_BM13 BM13 BJ15 VSS_BJ15 VSS_BG47 BG47 BD40 VSS_BD40 VSS_BA3 BA3 AW24 VSS_AW24 VSS_AY43 AY43
BR9 VSS_BR9 BJ17 VSS_BJ17 VSS_BG48 BG48 BD42 VSS_BD42 VSS_BA5 BA5 AW26 VSS_AW26 VSS_AU46 AU46
BR13 VSS_BR13 VSS_BM18 BM18 BJ19 VSS_BJ19 VSS_BG50 BG50 BD48 VSS_BD48 VSS_BA7 BA7 AW28 VSS_AW28 VSS_AU49 AU49
BR20 VSS_BR20 VSS_BM24 BM24 BJ25 VSS_BJ25 VSS_BG56 BG56 BD54 VSS_BD54 VSS_AY13 AY13 AW34 VSS_AW34 VSS_AU55 AU55
BR24 VSS_BR24 VSS_BM26 BM26 BJ27 VSS_BJ27 VSS_BF1 BF1 BD56 VSS_BD56 VSS_BA15 BA15 AW36 VSS_AW36 VSS_AT2 AT2
BR28 VSS_BR28 VSS_BM28 BM28 BJ29 VSS_BJ29 VSS_BF3 BF3 BC1 VSS_BC1 VSS_BA17 BA17 AW38 VSS_AW38 VSS_AT4 AT4
BR48 VSS_BR48 VSS_BM36 BM36 BJ37 VSS_BJ37 BC9 VSS_BC9 VSS_BA25 BA25 AW49 VSS_AW49 VSS_AT43 AT43
NC BR52 VSS_BR52 VSS_BM38 BM38 BJ39 VSS_BJ39 VSS_BF17 BF17 BC10 VSS_BC10 VSS_BA27 BA27 AW51 VSS_AW51 VSS_AT16 AT16
BP3 VSS_BP3 VSS_BM40 BM40 BJ41 VSS_BJ41 VSS_BF19 BF19 BC13 VSS_BC13 VSS_BA29 BA29 AW53 VSS_AW53 VSS_AT18 AT18
BP4 VSS_BP4 VSS_BM42 BM42 BJ43 VSS_BJ43 VSS_BF21 BF21 BC16 VSS_BC16 VSS_BA31 BA31 AW55 VSS_AW55 VSS_AT20 AT20
BP8 VSS_BP8 VSS_BM44 BM44 BJ44 VSS_BJ44 VSS_BF23 BF23 BC18 VSS_BC18 VSS_BA33 BA33 AV2 VSS_AV2 VSS_AT22 AT22
BP17 BL1 BJ54 BF29 BC24 BA39 AV8 AT28
B BP19
VSS_BP17
VSS_BP19
VSS_BL1
VSS_BL8 BL8 BH3
VSS_BJ54
VSS_BH3
VSS_BF29
VSS_BF31 BF31 BC26
VSS_BC24
VSS_BC26
VSS_BA39
VSS_BA41 BA41 AV12
VSS_AV8
VSS_AV12
VSS_AT28
VSS_AT30 AT30 B
BP21 VSS_BP21 VSS_BL11 BL11 BL4 VSS_BL4 VSS_BF33 BF33 BC28 VSS_BC28 VSS_BA14 BA14 AV13 VSS_AV13 VSS_AT32 AT32
BP23 VSS_BP23 VSS_BL16 BL16 BH7 VSS_BH7 VSS_BF35 BF35 BC30 VSS_BC30 VSS_BA45 BA45 AV15 VSS_AV15 VSS_AT34 AT34
BP33 VSS_BP33 VSS_BL26 BL26 BH22 VSS_BH22 VSS_BF44 BF44 BC40 VSS_BC40 VSS_AY2 AY2 AV25 VSS_AV25 VSS_AU14 AU14
BP35 VSS_BP35 VSS_BL28 BL28 BH24 VSS_BH24 VSS_BF49 BF49 BC42 VSS_BC42 VSS_AY4 AY4 AV27 VSS_AV27 VSS_AT47 AT47
BP43 VSS_BP43 VSS_BL36 BL36 BH32 VSS_BH32 VSS_BE15 BE15 BC51 VSS_BC51 VSS_AY16 AY16 AV35 VSS_AV35 VSS_AT54 AT54
BP46 VSS_BP46 VSS_BL38 BL38 BH34 VSS_BH34 VSS_BE17 BE17 BC53 VSS_BC53 VSS_AY18 AY18 AV37 VSS_AV37 VSS_AT56 AT56
BP49 VSS_BP49 VSS_BL40 BL40 BH36 VSS_BH36 VSS_BE19 BE19 BC55 VSS_BC55 VSS_AY20 AY20 AV39 VSS_AV39 VSS_AR1 AR1
BP53 VSS_BP53 VSS_BL42 BL42 BH38 VSS_BH38 VSS_BE21 BE21 BB2 VSS_BB2 VSS_AY22 AY22 AV41 VSS_AV41 VSS_AR3 AR3
BP54 VSS_BP54 VSS_BL46 BL46 BH40 VSS_BH40 VSS_BE23 BE23 BB4 VSS_BB4 VSS_AY24 AY24 AV43 VSS_AV43 VSS_AR5 AR5
BN1 VSS_BN1 VSS_BL49 BL49 BH42 VSS_BH42 VSS_BE25 BE25 BB6 VSS_BB6 VSS_AY26 AY26 AV45 VSS_AV45 VSS_AR7 AR7
BN10 VSS_BN10 VSS_BK10 BK10 BH51 VSS_BH51 VSS_BE31 BE31 BB13 VSS_BB13 VSS_AY32 AY32 AV54 VSS_AV54 VSS_AR14 AR14
BN14 VSS_BN14 VSS_BK14 BK14 BH53 VSS_BH53 VSS_BE33 BE33 BB15 VSS_BB15 VSS_AY34 AY34 AV56 VSS_AV56 VSS_AR16 AR16
BN15 VSS_BN15 BH55 VSS_BH55 VSS_BE35 BE35 BB17 VSS_BB17 VSS_AY36 AY36 AU1 VSS_AU1 VSS_AR18 AR18
M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: VSS

D D
U1 IC U1 IC U1 IC U1 IC
ARDEN ARDEN ARDEN ARDEN
29 OF 35 30 OF 35 31 OF 35 32 OF 35
VSS VSS VSS VSS
AR20 VSS_AR20 VSS_AM13 AM13 AK6 VSS_AK6 VSS_AH26 AH26 AF45 VSS_AF45 VSS_AC9 AC9 AA30 VSS_AA30 VSS_W49 W49
AR22 VSS_AR22 VSS_AN14 AN14 AK8 VSS_AK8 VSS_AH28 AH28 AF50 VSS_AF50 VSS_AC12 AC12 AA33 VSS_AA33 VSS_W51 W51
AR24 VSS_AR24 VSS_AM43 AM43 AK11 VSS_AK11 VSS_AH30 AH30 AF52 VSS_AF52 VSS_AC14 AC14 AA34 VSS_AA34 VSS_W53 W53
AR26 VSS_AR26 VSS_AN44 AN44 AK13 VSS_AK13 VSS_AH32 AH32 AF54 VSS_AF54 VSS_AB24 AB24 AA37 VSS_AA37 VSS_W55 W55
AR28 VSS_AR28 VSS_AN51 AN51 AK15 VSS_AK15 VSS_AH34 AH34 AF56 VSS_AF56 VSS_AC18 AC18 AA38 VSS_AA38 VSS_V2 V2
AR30 VSS_AR30 VSS_AN53 AN53 AK17 VSS_AK17 VSS_AH36 AH36 AE1 VSS_AE1 VSS_AB16 AB16 AA41 VSS_AA41 VSS_V4 V4
AR32 VSS_AR32 VSS_AN55 AN55 AK19 VSS_AK19 VSS_AH38 AH38 AE3 VSS_AE3 VSS_AC22 AC22 AA42 VSS_AA42 VSS_V6 V6
AR34 VSS_AR34 VSS_AM2 AM2 AK21 VSS_AK21 VSS_AH40 AH40 AE5 VSS_AE5 VSS_AC25 AC25 AA44 VSS_AA44 VSS_V8 V8
AR38 VSS_AR38 VSS_AM6 AM6 AK25 VSS_AK25 VSS_AJ44 AJ44 AE9 VSS_AE9 VSS_AC29 AC29 AA51 VSS_AA51 VSS_V13 V13
AR40 VSS_AR40 VSS_AM8 AM8 AK27 VSS_AK27 VSS_AG9 AG9 AE10 VSS_AE10 VSS_AC30 AC30 AA53 VSS_AA53 VSS_V15 V15
AR44 VSS_AR44 VSS_AN41 AN41 AK31 VSS_AK31 VSS_AH50 AH50 AE15 VSS_AE15 VSS_AC34 AC34 Y2 VSS_Y2 VSS_V19 V19
AR45 VSS_AR45 VSS_AM16 AM16 AK33 VSS_AK33 VSS_AH52 AH52 AE17 VSS_AE17 VSS_AC37 AC37 Y4 VSS_Y4 VSS_V20 V20
AR53 AM22 AK39 AG1 AE23 AC42 Y12 V27
C AR55
VSS_AR53
VSS_AR55
VSS_AM22
VSS_AM24 AM24 AK41
VSS_AK39
VSS_AK41
VSS_AG1
VSS_AG3 AG3 AE25
VSS_AE23
VSS_AE25
VSS_AC42
VSS_AC44 AC44 U14
VSS_Y12
VSS_U14
VSS_V27
VSS_V28 V28 C
AP2 VSS_AP2 VSS_AM26 AM26 AK43 VSS_AK43 VSS_AG5 AG5 AE27 VSS_AE27 VSS_AC45 AC45 Y15 VSS_Y15 VSS_V31 V31
AP6 VSS_AP6 VSS_AM30 AM30 AK48 VSS_AK48 VSS_AF48 AF48 AE31 VSS_AE31 VSS_AC51 AC51 Y19 VSS_Y19 VSS_V35 V35
AP15 VSS_AP15 VSS_AM36 AM36 AK54 VSS_AK54 VSS_AG18 AG18 AE37 VSS_AE37 VSS_AB2 AB2 Y24 VSS_Y24 VSS_V40 V40
AP17 VSS_AP17 VSS_AM38 AM38 AK56 VSS_AK56 VSS_AG20 AG20 AE39 VSS_AE39 VSS_AB4 AB4 Y27 VSS_Y27 VSS_V43 V43
AP19 VSS_AP19 VSS_AM40 AM40 AJ1 VSS_AJ1 VSS_AG22 AG22 AE41 VSS_AE41 VSS_AB6 AB6 Y28 VSS_Y28 VSS_V47 V47
AP21 VSS_AP21 VSS_AM42 AM42 AJ3 VSS_AJ3 VSS_AG24 AG24 AA14 VSS_AA14 VSS_AB8 AB8 Y31 VSS_Y31 VSS_V48 V48
AP23 VSS_AP23 VSS_AN49 AN49 AJ5 VSS_AJ5 VSS_AG26 AG26 AE46 VSS_AE46 VSS_AB13 AB13 Y32 VSS_Y32 VSS_V50 V50
AP25 VSS_AP25 VSS_AN9 AN9 AJ7 VSS_AJ7 VSS_AG28 AG28 AE49 VSS_AE49 VSS_AB15 AB15 Y35 VSS_Y35 VSS_V52 V52
AP31 VSS_AP31 VSS_AM54 AM54 AH13 VSS_AH13 VSS_AG34 AG34 AE55 VSS_AE55 VSS_AC17 AC17 Y40 VSS_Y40 VSS_U1 U1
AP33 VSS_AP33 VSS_AM56 AM56 AJ15 VSS_AJ15 VSS_AG36 AG36 AD2 VSS_AD2 VSS_AB23 AB23 U44 VSS_U44 VSS_U3 U3
AP35 VSS_AP35 VSS_AL1 AL1 AJ17 VSS_AJ17 VSS_AG38 AG38 AD4 VSS_AD4 VSS_AB27 AB27 Y48 VSS_Y48 VSS_U5 U5
AP43 VSS_AP43 VSS_AL9 AL9 AJ25 VSS_AJ25 VSS_AG49 AG49 AA18 VSS_AA18 VSS_AB35 AB35 Y56 VSS_Y56 VSS_Y13 Y13
AP46 VSS_AP46 VSS_AL10 AL10 AJ27 VSS_AJ27 VSS_AG51 AG51 AD16 VSS_AD16 VSS_AB36 AB36 W1 VSS_W1 VSS_U17 U17
B AP48
AP50
VSS_AP48 VSS_AL14 AL14
AL16
AJ29
AJ31
VSS_AJ29 VSS_AG53 AG53
AG55
AD18
AD20
VSS_AD18 VSS_AB39 AB39
AB40
W3
W5
VSS_W3 VSS_U18 U18
U21 B
VSS_AP50 VSS_AL16 VSS_AJ31 VSS_AG55 VSS_AD20 VSS_AB40 VSS_W5 VSS_U21
AP52 VSS_AP52 VSS_AL18 AL18 AJ33 VSS_AJ33 VSS_AF2 AF2 AA22 VSS_AA22 VSS_AB43 AB43 W7 VSS_W7 VSS_U22 U22
AP54 VSS_AP54 VSS_AL20 AL20 AJ35 VSS_AJ35 VSS_AF4 AF4 AD24 VSS_AD24 VSS_AB46 AB46 W9 VSS_W9 VSS_U25 U25
AP56 VSS_AP56 VSS_AL22 AL22 AJ37 VSS_AJ37 VSS_AF6 AF6 AD27 VSS_AD27 VSS_AB48 AB48 W10 VSS_W10 VSS_U26 U26
AN1 VSS_AN1 VSS_AL24 AL24 AJ39 VSS_AJ39 VSS_AF8 AF8 AD28 VSS_AD28 VSS_AB50 AB50 W14 VSS_W14 VSS_U29 U29
AN5 VSS_AN5 VSS_AL28 AL28 AH43 VSS_AH43 VSS_AF13 AF13 AD32 VSS_AD32 VSS_AB54 AB54 W18 VSS_W18 VSS_U33 U33
AM48 VSS_AM48 VSS_AL32 AL32 AJ49 VSS_AJ49 VSS_AF17 AF17 AD36 VSS_AD36 VSS_AA1 AA1 W22 VSS_W22 VSS_U37 U37
AN39 VSS_AN39 VSS_AL34 AL34 AJ51 VSS_AJ51 VSS_AF19 AF19 AD39 VSS_AD39 VSS_AA3 AA3 W25 VSS_W25 VSS_U38 U38
AN17 VSS_AN17 VSS_AL38 AL38 AJ55 VSS_AJ55 VSS_AF23 AF23 AA7 VSS_AA7 VSS_AC21 AC21 W29 VSS_W29 VSS_U42 U42
AN19 VSS_AN19 VSS_AL40 AL40 AH2 VSS_AH2 VSS_AF25 AF25 AD47 VSS_AD47 VSS_AA9 AA9 W30 VSS_W30 VSS_Y43 Y43
AN21 VSS_AN21 VSS_AL42 AL42 AH4 VSS_AH4 VSS_AF27 AF27 AD48 VSS_AD48 VSS_AD13 AD13 W33 VSS_W33 VSS_U45 U45
AN23 VSS_AN23 VSS_AL44 AL44 AH6 VSS_AH6 VSS_AF29 AF29 AD50 VSS_AD50 VSS_AA17 AA17 W34 VSS_W34 VSS_U49 U49
AN31 VSS_AN31 VSS_AL53 AL53 AH18 VSS_AH18 VSS_AF37 AF37 AC1 VSS_AC1 VSS_AA25 AA25 W42 VSS_W42 VSS_T2 T2
AN33 VSS_AN33 VSS_AL55 AL55 AH20 VSS_AH20 VSS_AF39 AF39 AC3 VSS_AC3 VSS_AA26 AA26 W44 VSS_W44 VSS_T4 T4
AN35 VSS_AN35 VSS_AK2 AK2 AH22 VSS_AH22 VSS_AF41 AF41 AC5 VSS_AC5 VSS_AA29 AA29 W45 VSS_W45 VSS_T6 T6
AN37 VSS_AN37 VSS_AK4 AK4 AH24 VSS_AH24 VSS_AF43 AF43 AC7 VSS_AC7 VSS_AE14 AE14 W46 VSS_W46 VSS_T8 T8
M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963

M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: POWER: VSS

D D
U1 IC U1 IC U1 IC
ARDEN ARDEN ARDEN
33 OF 35 34 OF 35 35 OF 35
VSS VSS VSS
VSS_P30 P30 K1 VSS_K1 VSS_G13 G13 E39 VSS_E39
T16 VSS_T16 VSS_J33 J33 K3 VSS_K3 VSS_G15 G15 E41 VSS_E41 VSS_C51 C51
T19 VSS_T19 VSS_P50 P50 K5 VSS_K5 VSS_G17 G17 E43 VSS_E43 VSS_C53 C53
T20 VSS_T20 VSS_P52 P52 K7 VSS_K7 VSS_G19 G19 E46 VSS_E46 VSS_C54 C54
T23 VSS_T23 VSS_P54 P54 K13 VSS_K13 VSS_G21 G21 E48 VSS_E48 VSS_B1 B1
T24 VSS_T24 VSS_P56 P56 K19 VSS_K19 VSS_G23 G23 E51 VSS_E51 VSS_B2 B2
T27 VSS_T27 VSS_N1 N1 K25 VSS_K25 VSS_G25 G25 E53 VSS_E53 VSS_B4 B4
T28 VSS_T28 VSS_N3 N3 K31 VSS_K31 VSS_G27 G27 E55 VSS_E55 VSS_B6 B6
T31 VSS_T31 VSS_N5 N5 K37 VSS_K37 VSS_G29 G29 D1 VSS_D1 VSS_B9 B9
T36 VSS_T36 VSS_P38 P38 K51 VSS_K51 VSS_G35 G35 D6 VSS_D6 VSS_B16 B16
T13 VSS_T13 VSS_N33 N33 J2 VSS_J2 VSS_G41 G41 D14 VSS_D14 VSS_B22 B22
C T50
T52
VSS_T50 VSS_N27 N27
P18
J8
J13
VSS_J8 VSS_G48 G48
F2
D20
D22
VSS_D20 VSS_B28 B28
B30 C
VSS_T52 VSS_P18 VSS_J13 VSS_F2 VSS_D22 VSS_B30
T54 VSS_T54 VSS_N31 N31 J17 VSS_J17 VSS_F4 F4 D24 VSS_D24 VSS_B32 B32
T56 VSS_T56 VSS_P22 P22 J19 VSS_J19 VSS_F6 F6 D26 VSS_D26 VSS_B34 B34
R1 VSS_R1 VSS_N35 N35 J23 VSS_J23 VSS_F9 F9 D28 VSS_D28 VSS_B36 B36
R3 VSS_R3 VSS_P26 P26 J25 VSS_J25 VSS_F11 F11 D30 VSS_D30 VSS_B38 B38
J15 VSS_J15 VSS_N43 N43 J35 VSS_J35 VSS_F18 F18 D36 VSS_D36 VSS_B44 B44
R26 VSS_R26 VSS_M14 M14 J52 VSS_J52 VSS_F30 F30 D49 VSS_D49 VSS_A2 A2
R33 VSS_R33 VSS_M23 M23 H1 VSS_H1 VSS_F36 F36 D54 VSS_D54 VSS_A8 A8
R34 VSS_R34 VSS_M26 M26 H3 VSS_H3 VSS_F38 F38 D56 VSS_D56 VSS_A10 A10
R37 VSS_R37 VSS_M32 M32 H5 VSS_H5 VSS_F40 F40 C5 VSS_C5 VSS_A13 A13
R44 M41 H11 F47 C13 A19
B R49
VSS_R44
VSS_R49
VSS_M41
VSS_M44 M44 H14
VSS_H11
VSS_H14
VSS_F47
VSS_F49 F49 C15
VSS_C13
VSS_C15
VSS_A19
VSS_A21 A21 B
R51 VSS_R51 VSS_L2 L2 H16 VSS_H16 VSS_F52 F52 C17 VSS_C17 VSS_A23 A23
P2 VSS_P2 VSS_L8 L8 H22 VSS_H22 VSS_E1 E1 C23 VSS_C23 VSS_A29 A29
P6 VSS_P6 VSS_P48 P48 H26 VSS_H26 VSS_E5 E5 C27 VSS_C27 VSS_A33 A33
P12 VSS_P12 VSS_R9 R9 H30 VSS_H30 VSS_E10 E10 C31 VSS_C31 VSS_A37 A37
P34 VSS_P34 VSS_J21 J21 H34 VSS_H34 VSS_E15 E15 C35 VSS_C35 VSS_A41 A41
N17 VSS_N17 VSS_J27 J27 H38 VSS_H38 VSS_E19 E19 C39 VSS_C39 VSS_A46 A46
N21 VSS_N21 VSS_L39 L39 H42 VSS_H42 VSS_E23 E23 C43 VSS_C43 VSS_A51 A51
N25 VSS_N25 VSS_L46 L46 H47 VSS_H47 VSS_E27 E27 C48 VSS_C48 VSS_A55 A55
P32 VSS_P32 VSS_L48 L48 H51 VSS_H51 VSS_E29 E29
P41 VSS_P41 VSS_L50 L50 H53 VSS_H53 VSS_E31 E31 M1090982-001 BGA2963
P36 VSS_P36 VSS_L52 L52 H55 VSS_H55 VSS_E33 E33
T43 VSS_T43 VSS_L54 L54 G8 VSS_G8 VSS_E35 E35
P40 VSS_P40 VSS_L56 L56 G10 VSS_G10 VSS_E37 E37
M1090982-001 BGA2963 M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: MEMORY: PARTITION A & B

D D
U1 IC U1 IC
ARDEN ARDEN
3 OF 35 4 OF 35
MEMORY CHANNEL A0-A1 MEMORY CHANNEL B0-B1
19 A0_CKE_N BC43 A0_CKE_N A1_CKE_N BF46 A1_CKE_N 19 20 B0_CKE_N AN46 B0_CKE* B1_CKE* AR48 B1_CKE_N 20
OUT OUT OUT OUT
19 A0_CABI BB46 A0_CABI A1_CABI BC50 A1_CABI 19 20 B0_CABI AK45 B0_CABI B1_CABI AM47 B1_CABI 20
BI A0_CA9 BA46 AW48 A1_CA9
BI BI B0_CA9 AK46 AH49 B1_CA9
BI
19 BI A0_CA9 A1_CA9 BI 19 20 BI B0_CA9 B1_CA9 BI 20
19 A0_CA8 BB45 A0_CA8 A1_CA8 BC48 A1_CA8 19 20 B0_CA8 AL45 B0_CA8 B1_CA8 AL48 B1_CA8 20
BI A0_CA7 BD43 BF48 A1_CA7
BI BI B0_CA7 AP45 AP47 B1_CA7
BI
19 A0_CA6 BE43 A0_CA6 A1_CA6 BH47 A1_CA6 19 20 B0_CA6 AT45 B0_CA6 B1_CA6 AU47 B1_CA6 20
BI A0_CA5 BD46 BG49 A1_CA5
BI BI B0_CA5 AN45 AR47 B1_CA5
BI
19 A0_CA4 BC45 A0_CA4 A1_CA4 BA47 A1_CA4 19 20 B0_CA4 AM46 B0_CA4 B1_CA4 AL47 B1_CA4 20
BI A0_CA3 BE44 BG46 A1_CA3
BI BI B0_CA3 AU45 AT46 B1_CA3
BI
A0_CA2 AW46 AY47 A1_CA2 B0_CA2 AG45 AJ47 B1_CA2
C 19
19
BI
BI A0_CA1 BG44
A0_CA2
A0_CA1
A1_CA2
A1_CA1 BH48 A1_CA1
BI
BI
19
19
20
20
BI
BI B0_CA1 AV46
B0_CA2
B0_CA1
B1_CA2
B1_CA1 AR46 B1_CA1
BI
BI
20
20 C
19 A0_CA0 AW45 A0_CA0 A1_CA0 AY49 A1_CA0 19 20 B0_CA0 AH45 B0_CA0 B1_CA0 AJ48 B1_CA0 20
BI BI BI BI
19 A0_WCK0_P BB49 A0_WCK0_P A1_WCK0_P BB55 A1_WCK0_P 19 20 B0_WCK0_P AL52 B0_WCK0_P B1_WCK0_P AH53 B1_WCK0_P 20
OUT A0_WCK0_N BA48 BA56 A1_WCK0_N
OUT OUT B0_WCK0_N AK51 AJ54 B1_WCK0_N
OUT
19 OUT A0_WCK0_N A1_WCK0_N OUT 19 20 OUT B0_WCK0_N B1_WCK0_N OUT 20
19 A0_WCK1_P BB51 A0_WCK1_P A1_WCK1_P BB53 A1_WCK1_P 19 20 B0_WCK1_P AL50 B0_WCK1_P B1_WCK1_P AH55 B1_WCK1_P 20
OUT A0_WCK1_N BC52 BC54 A1_WCK1_N
OUT OUT B0_WCK1_N AM49 AG56 B1_WCK1_N
OUT
19 OUT A0_WCK1_N A1_WCK1_N OUT 19 20 OUT B0_WCK1_N B1_WCK1_N OUT 20
19 A0_EDC_0 AW52 A0_EDC_0 A1_EDC_0 AV55 A1_EDC_0 19 20 B0_EDC_0 AG52 B0_EDC_0 B1_EDC_0 AM55 B1_EDC_0 20
BI A0_EDC_1 BG53 BF56 A1_EDC_1
BI BI B0_EDC_1 AR50 AE54 B1_EDC_1
BI
19 BI A0_EDC_1 A1_EDC_1 BI 19 20 BI B0_EDC_1 B1_EDC_1 BI 20
19 A0_DBI_0 AY51 A0_DBI_0 A1_DBI_0 AU56 A1_DBI_0 19 20 B0_DBI_0 AH51 B0_DBI_0 B1_DBI_0 AM53 B1_DBI_0 20
BI A0_DBI_1 BG51 BG55 A1_DBI_1
BI BI B0_DBI_1 AP53 AD53 B1_DBI_1
BI
19 BI A0_DBI_1 A1_DBI_1 BI 19 20 BI B0_DBI_1 B1_DBI_1 BI 20
19 A0_DQ15 BF50 A0_DQ15 A1_DQ15 BJ56 A1_DQ15 19 20 B0_DQ15 AN52 B0_DQ15 B1_DQ15 AB55 B1_DQ15 20
BI A0_DQ14 BD51 BJ55 A1_DQ14
BI BI B0_DQ14 AN50 AC54 B1_DQ14
BI
19 BI A0_DQ14 A1_DQ14 BI 19 20 BI B0_DQ14 B1_DQ14 BI 20
19 A0_DQ13 BF52 A0_DQ13 A1_DQ13 BH54 A1_DQ13 19 20 B0_DQ13 AP51 B0_DQ13 B1_DQ13 AD55 B1_DQ13 20
BI A0_DQ12 BD49 BH56 A1_DQ12
BI BI B0_DQ12 AM51 AC56 B1_DQ12
BI
19 A0_DQ11 BH52 A0_DQ11 A1_DQ11 BF54 A1_DQ11 19 20 B0_DQ11 AT49 B0_DQ11 B1_DQ11 AE56 B1_DQ11 20
BI A0_DQ10 BH50 BD55 A1_DQ10
BI BI B0_DQ10 AR52 AF53 B1_DQ10
BI
19 A0_DQ9 BJ52 A0_DQ9 A1_DQ9 BD53 A1_DQ9 19 20 B0_DQ9 AU50 B0_DQ9 B1_DQ9 AF55 B1_DQ9 20
BI A0_DQ8 BJ50 BC56 A1_DQ8
BI BI B0_DQ8 AT51 AG54 B1_DQ8
BI
B 19 BI A0_DQ7
A0_DQ6
BA50
BA54
A0_DQ7 A1_DQ7 AR56
AT55
A1_DQ7
A1_DQ6
BI 19 20 BI B0_DQ7
B0_DQ6
AJ52
AK49
B0_DQ7 B1_DQ7 AR54
AP55
B1_DQ7
B1_DQ6
BI 20
B
19 A0_DQ5 AY53 A0_DQ5 A1_DQ5 AU54 A1_DQ5 19 20 B0_DQ5 AJ50 B0_DQ5 B1_DQ5 AN54 B1_DQ5 20
BI A0_DQ4 BA52 AT53 A1_DQ4
BI BI B0_DQ4 AK53 AN56 B1_DQ4
BI
19 A0_DQ3 AV51 A0_DQ3 A1_DQ3 AV53 A1_DQ3 19 20 B0_DQ3 AF51 B0_DQ3 B1_DQ3 AL56 B1_DQ3 20
BI A0_DQ2 AW50 AW56 A1_DQ2
BI BI B0_DQ2 AG50 AK55 B1_DQ2
BI
19 A0_DQ1 AU52 A0_DQ1 A1_DQ1 AW54 A1_DQ1 19 20 B0_DQ1 AE52 B0_DQ1 B1_DQ1 AL54 B1_DQ1 20
BI A0_DQ0 AV49 AY55 A1_DQ0
BI BI B0_DQ0 AF49 AJ56 B1_DQ0
BI
19 A_CK_P BD47 A_CK_P 20 B_CK_P AP49 B_CK_P

OUT A_CK_N BC47
OUT B_CK_N AN48
19 OUT A_CK_N 20 OUT B_CK_N
19 A_DRAM_RESET AY45 A_DRAM_RESET 20 B_DRAM_RESET AJ46 B_DRAM_RESET
OUT ABCDE_MEM_VREF AU48
OUT
ABCDE_MEM_VREF
ABCD_MEM_CALR AV48 ABCD_MEM_CALR M1090982-001 BGA2963
1 R117 M1090982-001 BGA2963
118 OHM
1%
2 CH
201
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: MEMORY: PARTITION C & D

D D
U1 IC U1 IC
ARDEN ARDEN
5 OF 35 6 OF 35
MEMORY CHANNEL C0-C1 MEMORY CHANNEL D0-D1
21 C0_CKE_N AC46 C0_CKE* C1_CKE* AE48 C1_CKE_N 21 22 D0_CKE_N L44 D0_CKE_N D1_CKE_N T47 D1_CKE_N 22
OUT OUT OUT OUT
21 C0_CABI Y46 C0_CABI C1_CABI AB47 C1_CABI 21 22 D0_CABI L43 D0_CABI D1_CABI K48 D1_CABI 22
BI C0_CA9 V46 W47 C1_CA9
BI BI D0_CA9 M42 J44 D1_CA9
BI
21 BI C0_CA9 C1_CA9 BI 21 22 BI D0_CA9 D1_CA9 BI 22
21 C0_CA8 AA45 C0_CA8 C1_CA8 AA46 C1_CA8 21 22 D0_CA8 M43 D0_CA8 D1_CA8 N47 D1_CA8 22
BI C0_CA7 AD46 AC47 C1_CA7
BI BI D0_CA7 N45 P47 D1_CA7
BI
21 C0_CA6 AE45 C0_CA6 C1_CA6 AH47 C1_CA6 21 22 D0_CA6 P46 D0_CA6 D1_CA6 U48 D1_CA6 22
BI C0_CA5 AD45 AE47 C1_CA5
BI BI D0_CA5 K46 R48 D1_CA5
BI
21 C0_CA4 AB45 C0_CA4 C1_CA4 AA48 C1_CA4 21 22 D0_CA4 K44 D0_CA4 D1_CA4 L47 D1_CA4 22
BI C0_CA3 AF46 AG48 C1_CA3
BI BI D0_CA3 R45 U47 D1_CA3
BI
C0_CA2 T45 Y47 C1_CA2 D0_CA2 M39 J47 D1_CA2
C 21
21
BI
BI C0_CA1 AG46
C0_CA2
C0_CA1
C1_CA2
C1_CA1 AF47 C1_CA1
BI
BI
21
21
22
22
BI
BI D0_CA1 R46
D0_CA2
D0_CA1
D1_CA2
D1_CA1 T49 D1_CA1
BI
BI
22
22 C
21 C0_CA0 U46 C0_CA0 C1_CA0 W48 C1_CA0 21 22 D0_CA0 L41 D0_CA0 D1_CA0 H46 D1_CA0 22
BI BI BI BI
21 C0_WCK0_P W50 C0_WCK0_P C1_WCK0_P R54 C1_WCK0_P 21 22 D0_WCK0_P D48 D0_WCK0_P D1_WCK0_P D51 D1_WCK0_P 22
OUT C0_WCK0_N Y49 P53 C1_WCK0_N
OUT OUT D0_WCK0_N E49 C49 D1_WCK0_N
OUT
21 OUT C0_WCK0_N C1_WCK0_N OUT 21 22 OUT D0_WCK0_N D1_WCK0_N OUT 22
21 C0_WCK1_P W52 C0_WCK1_P C1_WCK1_P R56 C1_WCK1_P 21 22 D0_WCK1_P F48 D0_WCK1_P D1_WCK1_P B51 D1_WCK1_P 22
OUT C0_WCK1_N V51 T55 C1_WCK1_N
OUT OUT D0_WCK1_N G47 A52 D1_WCK1_N
OUT
21 OUT C0_WCK1_N C1_WCK1_N OUT 21 22 OUT D0_WCK1_N D1_WCK1_N OUT 22
21 C0_EDC_0 AC50 C0_EDC_0 C1_EDC_0 L55 C1_EDC_0 21 22 D0_EDC_0 J51 D0_EDC_0 D1_EDC_0 E44 D1_EDC_0 22
BI C0_EDC_1 R52 W54 C1_EDC_1
BI BI D0_EDC_1 H43 E52 D1_EDC_1
BI
21 BI C0_EDC_1 C1_EDC_1 BI 21 22 BI D0_EDC_1 D1_EDC_1 BI 22
21 C0_DBI_0 AB53 C0_DBI_0 C1_DBI_0 K56 C1_DBI_0 21 22 D0_DBI_0 J49 D0_DBI_0 D1_DBI_0 C44 D1_DBI_0 22
BI C0_DBI_1 T51 W56 C1_DBI_1
BI BI D0_DBI_1 G44 E54 D1_DBI_1
BI
21 BI C0_DBI_1 C1_DBI_1 BI 21 22 BI D0_DBI_1 D1_DBI_1 BI 22
21 C0_DQ15 U50 C0_DQ15 C1_DQ15 AA56 C1_DQ15 21 22 D0_DQ15 F46 D0_DQ15 D1_DQ15 H54 D1_DQ15 22
BI C0_DQ14 U52 AA54 C1_DQ14
BI BI D0_DQ14 E47 F53 D1_DQ14
BI
21 BI C0_DQ14 C1_DQ14 BI 21 22 BI D0_DQ14 D1_DQ14 BI 22
21 C0_DQ13 T53 C0_DQ13 C1_DQ13 Y55 C1_DQ13 21 22 D0_DQ13 D46 D0_DQ13 D1_DQ13 E56 D1_DQ13 22
BI C0_DQ12 V49 Y53 C1_DQ12
BI BI D0_DQ12 C47 F55 D1_DQ12
BI
21 C0_DQ11 P51 C0_DQ11 C1_DQ11 V53 C1_DQ11 21 22 D0_DQ11 D43 D0_DQ11 D1_DQ11 D55 D1_DQ11 22
BI C0_DQ10 R50 U56 C1_DQ10
BI BI D0_DQ10 F43 F51 D1_DQ10
BI
21 C0_DQ9 N52 C0_DQ9 C1_DQ9 V55 C1_DQ9 21 22 D0_DQ9 H41 D0_DQ9 D1_DQ9 B53 D1_DQ9 22
BI C0_DQ8 P49 U54 C1_DQ8
BI BI D0_DQ8 G42 C52 D1_DQ8
BI
B 21 BI C0_DQ7
C0_DQ6
AA52
AA50
C0_DQ7 C1_DQ7 H56
J55
C1_DQ7
C1_DQ6
BI 21 22 BI D0_DQ7
D0_DQ6
H50
H48
D0_DQ7 D1_DQ7 C42
E42
D1_DQ7
D1_DQ6
BI 22
B
21 C0_DQ5 AB51 C0_DQ5 C1_DQ5 K54 C1_DQ5 21 22 D0_DQ5 H52 D0_DQ5 D1_DQ5 A44 D1_DQ5 22
BI C0_DQ4 Y51 J53 C1_DQ4
BI BI D0_DQ4 G49 B43 D1_DQ4
BI
21 C0_DQ3 AD49 C0_DQ3 C1_DQ3 L53 C1_DQ3 21 22 D0_DQ3 K50 D0_DQ3 D1_DQ3 B46 D1_DQ3 22
BI C0_DQ2 AC52 N56 C1_DQ2
BI BI D0_DQ2 K52 B48 D1_DQ2
BI
21 C0_DQ1 AE50 C0_DQ1 C1_DQ1 N54 C1_DQ1 21 22 D0_DQ1 N50 D0_DQ1 D1_DQ1 A47 D1_DQ1 22
BI C0_DQ0 AD51 P55 C1_DQ0
BI BI D0_DQ0 L51 A49 D1_DQ0
BI
21 C_CK_P AC48 C_CK_P 22 D_CK_P N48 D_CK_P

OUT C_CK_N AB49
OUT D_CK_N L49
21 OUT C_CK_N 22 OUT D_CK_N
21 C_DRAM_RESET V45 C_DRAM_RESET 22 D_DRAM_RESET K42 D_DRAM_RESET
OUT OUT
M1090982-001 BGA2963 M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: MEMORY: PARTITION E & F

D D
U1 IC U1 IC
ARDEN ARDEN
7 OF 35 8 OF 35
MEMORY CHANNEL E0-E1 MEMORY CHANNEL F0-F1
23 E0_CKE_N M34 E0_CKE_N E1_CKE_N K40 E1_CKE_N 23 24 F0_CKE_N L23 F0_CKE_N F1_CKE_N K21 F1_CKE_N 24
OUT OUT OUT OUT
23 E0_CABI L32 E0_CABI E1_CABI L37 E1_CABI 23 24 F0_CABI L26 F0_CABI F1_CABI L25 F1_CABI 24
BI E0_CA9 M31 J32 E1_CA9
BI BI F0_CA9 M27 K29 F1_CA9
BI
23 BI E0_CA9 E1_CA9 BI 23 24 BI F0_CA9 F1_CA9 BI 24
23 E0_CA8 M33 E0_CA8 E1_CA8 K36 E1_CA8 23 24 F0_CA8 M25 F0_CA8 F1_CA8 J26 F1_CA8 24
BI E0_CA7 M36 H39 E1_CA7
BI BI F0_CA7 M22 K23 F1_CA7
BI
23 E0_CA6 M37 E0_CA6 E1_CA6 J42 E1_CA6 23 24 F0_CA6 M21 F0_CA6 F1_CA6 L19 F1_CA6 24
BI E0_CA5 L35 J40 E1_CA5
BI BI F0_CA5 L22 J22 F1_CA5
BI
23 E0_CA4 L34 E0_CA4 E1_CA4 K35 E1_CA4 23 24 F0_CA4 M24 F0_CA4 F1_CA4 K26 F1_CA4 24
BI E0_CA3 J38 M40 E1_CA3
BI BI F0_CA3 L20 K20 F1_CA3
BI
E0_CA2 M30 J34 E1_CA2 F0_CA2 L29 K27 F1_CA2
C 23
23
BI
BI E0_CA1 L38
E0_CA2
E0_CA1
E1_CA2
E1_CA1 L40 E1_CA1
BI
BI
23
23
24
24
BI
BI F0_CA1 M19
F0_CA2
F0_CA1
F1_CA2
F1_CA1 J20 F1_CA1
BI
BI
24
24 C
23 E0_CA0 K30 E0_CA0 E1_CA0 K33 E1_CA0 23 24 F0_CA0 L28 F0_CA0 F1_CA0 J28 F1_CA0 24
BI BI BI BI
23 E0_WCK0_P F35 E0_WCK0_P E1_WCK0_P A36 E1_WCK0_P 23 24 F0_WCK0_P F23 F0_WCK0_P F1_WCK0_P A24 F1_WCK0_P 24
OUT E0_WCK0_N E34 B35 E1_WCK0_N
OUT OUT F0_WCK0_N E24 B25 F1_WCK0_N
OUT
23 OUT E0_WCK0_N E1_WCK0_N OUT 23 24 OUT F0_WCK0_N F1_WCK0_N OUT 24
23 E0_WCK1_P H35 E0_WCK1_P E1_WCK1_P C36 E1_WCK1_P 23 24 F0_WCK1_P H23 F0_WCK1_P F1_WCK1_P C24 F1_WCK1_P 24
OUT E0_WCK1_N G36 D37 E1_WCK1_N
OUT OUT F0_WCK1_N G22 B23 F1_WCK1_N
OUT
23 OUT E0_WCK1_N E1_WCK1_N OUT 23 24 OUT F0_WCK1_N F1_WCK1_N OUT 24
23 E0_EDC_0 H31 E0_EDC_0 E1_EDC_0 E32 E1_EDC_0 23 24 F0_EDC_0 D27 F0_EDC_0 F1_EDC_0 E28 F1_EDC_0 24
BI E0_EDC_1 D39 B39 E1_EDC_1
BI BI F0_EDC_1 D19 A20 F1_EDC_1
BI
23 BI E0_EDC_1 E1_EDC_1 BI 23 24 BI F0_EDC_1 F1_EDC_1 BI 24
23 E0_DBI_0 G32 E0_DBI_0 E1_DBI_0 C32 E1_DBI_0 23 24 F0_DBI_0 G26 F0_DBI_0 F1_DBI_0 C28 F1_DBI_0 24
BI E0_DBI_1 G38 A40 E1_DBI_1
BI BI F0_DBI_1 G20 C20 F1_DBI_1
BI
23 BI E0_DBI_1 E1_DBI_1 BI 23 24 BI F0_DBI_1 F1_DBI_1 BI 24
23 E0_DQ15 F37 E0_DQ15 E1_DQ15 A42 E1_DQ15 23 24 F0_DQ15 F21 F0_DQ15 F1_DQ15 C18 F1_DQ15 24
BI E0_DQ14 J36 B41 E1_DQ14
BI BI F0_DQ14 D21 A18 F1_DQ14
BI
23 BI E0_DQ14 E1_DQ14 BI 23 24 BI F0_DQ14 F1_DQ14 BI 24
23 E0_DQ13 H37 E0_DQ13 E1_DQ13 C40 E1_DQ13 23 24 F0_DQ13 H21 F0_DQ13 F1_DQ13 E20 F1_DQ13 24
BI E0_DQ12 E36 E40 E1_DQ12
BI BI F0_DQ12 E22 B19 F1_DQ12
BI
23 E0_DQ11 G40 E0_DQ11 E1_DQ11 E38 E1_DQ11 23 24 F0_DQ11 H19 F0_DQ11 F1_DQ11 B21 F1_DQ11 24
BI E0_DQ10 F39 A38 E1_DQ10
BI BI F0_DQ10 F19 A22 F1_DQ10
BI
23 E0_DQ9 F41 E0_DQ9 E1_DQ9 C38 E1_DQ9 23 24 F0_DQ9 F17 F0_DQ9 F1_DQ9 C22 F1_DQ9 24
BI E0_DQ8 D41 B37 E1_DQ8
BI BI F0_DQ8 G18 D23 F1_DQ8
BI
B 23 BI E0_DQ7
E0_DQ6
F33
D33
E0_DQ7 E1_DQ7 C30
E30
E1_DQ7
E1_DQ6
BI 23 24 BI F0_DQ7
F0_DQ6
F25
D25
F0_DQ7 F1_DQ7 A30
B29
F1_DQ7
F1_DQ6
BI 24
B
23 E0_DQ5 H33 E0_DQ5 E1_DQ5 A32 E1_DQ5 23 24 F0_DQ5 H25 F0_DQ5 F1_DQ5 A28 F1_DQ5 24
BI E0_DQ4 G34 B31 E1_DQ4
BI BI F0_DQ4 G24 D29 F1_DQ4
BI
23 E0_DQ3 F31 E0_DQ3 E1_DQ3 B33 E1_DQ3 23 24 F0_DQ3 H27 F0_DQ3 F1_DQ3 B27 F1_DQ3 24
BI E0_DQ2 D31 C34 E1_DQ2
BI BI F0_DQ2 F27 C26 F1_DQ2
BI
23 E0_DQ1 H29 E0_DQ1 E1_DQ1 A34 E1_DQ1 23 24 F0_DQ1 F29 F0_DQ1 F1_DQ1 A26 F1_DQ1 24
BI E0_DQ0 G30 D35 E1_DQ0
BI BI F0_DQ0 G28 E26 F1_DQ0
BI
23 E_CK_P K39 E_CK_P 24 F_CK_P J24 F_CK_P

OUT E_CK_N K38
OUT F_CK_N K24
23 OUT E_CK_N 24 OUT F_CK_N
23 E_DRAM_RESET L31 E_DRAM_RESET 24 F_DRAM_RESET M28 F_DRAM_RESET
OUT TM_IO J30
OUT F_MEM_CALR M29
TM_IO F_MEM_CALR
E_MEM_CALR K32 E_MEM_CALR 1 R78
1 R112 118 OHM M1090982-001 BGA2963
118 OHM M1090982-001 BGA2963 1%
1% 2 CH
2 CH 201
201
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: MEMORY: PARTITION G & H

D D
U1 IC U1 IC
ARDEN ARDEN
9 OF 35 10 OF 35
MEMORY CHANNEL G0-G1 MEMORY CHANNEL H0-H1
25 G0_CKE_N M13 G0_CKE_N G1_CKE_N J10 G1_CKE_N 25 26 H0_CKE_N AB11 H0_CKE_N H1_CKE_N AA10 H1_CKE_N 26
OUT OUT OUT OUT
25 G0_CABI M15 G0_CABI G1_CABI K14 G1_CABI 25 26 H0_CABI Y11 H0_CABI H1_CABI V7 H1_CABI 26
BI G0_CA9 M16 J18 G1_CA9
BI BI H0_CA9 W12 N10 H1_CA9
BI
25 BI G0_CA9 G1_CA9 BI 25 26 BI H0_CA9 H1_CA9 BI 26
25 G0_CA8 J14 G0_CA8 G1_CA8 K15 G1_CA8 25 26 H0_CA8 AA12 H0_CA8 H1_CA8 V9 H1_CA8 26
BI G0_CA7 P11 F10 G1_CA7
BI BI H0_CA7 AD12 Y9 H1_CA7
BI
25 G0_CA6 P10 G0_CA6 G1_CA6 N11 G1_CA6 25 26 H0_CA6 AE12 H0_CA6 H1_CA6 AD9 H1_CA6 26
BI G0_CA5 N12 J11 G1_CA5
BI BI H0_CA5 AC11 Y10 H1_CA5
BI
25 G0_CA4 L14 G0_CA4 G1_CA4 J16 G1_CA4 25 26 H0_CA4 AB12 H0_CA4 H1_CA4 U10 H1_CA4 26
BI G0_CA3 R12 L9 G1_CA3
BI BI H0_CA3 AE11 AC10 H1_CA3
BI
G0_CA2 M18 K17 G1_CA2 H0_CA2 T11 T9 H1_CA2
C 25
25
BI
BI G0_CA1 T12
G0_CA2
G0_CA1
G1_CA2
G1_CA1 K10 G1_CA1
BI
BI
25
25
26
26
BI
BI H0_CA1 AF11
H0_CA2
H0_CA1
H1_CA2
H1_CA1 AB9 H1_CA1
BI
BI
26
26 C
25 G0_CA0 L17 G0_CA0 G1_CA0 K18 G1_CA0 25 26 H0_CA0 U11 H0_CA0 H1_CA0 R10 H1_CA0 26
BI BI BI BI
25 G0_WCK0_P H10 G0_WCK0_P G1_WCK0_P A11 G1_WCK0_P 25 26 H0_WCK0_P U6 H0_WCK0_P H1_WCK0_P L3 H1_WCK0_P 26
OUT G0_WCK0_N G9 B13 G1_WCK0_N
OUT OUT H0_WCK0_N V5 K4 H1_WCK0_N
OUT
25 OUT G0_WCK0_N G1_WCK0_N OUT 25 26 OUT H0_WCK0_N H1_WCK0_N OUT 26
25 G0_WCK1_P D10 G0_WCK1_P G1_WCK1_P C11 G1_WCK1_P 25 26 H0_WCK1_P U8 H0_WCK1_P H1_WCK1_P L1 H1_WCK1_P 26
OUT G0_WCK1_N E11 B10 G1_WCK1_N
OUT OUT H0_WCK1_N T7 N2 H1_WCK1_N
OUT
25 OUT G0_WCK1_N G1_WCK1_N OUT 25 26 OUT H0_WCK1_N H1_WCK1_N OUT 26
25 G0_EDC_0 F5 G0_EDC_0 G1_EDC_0 E16 G1_EDC_0 25 26 H0_EDC_0 AA6 H0_EDC_0 H1_EDC_0 H2 H1_EDC_0 26
BI G0_EDC_1 H15 A6 G1_EDC_1
BI BI H0_EDC_1 P5 T3 H1_EDC_1
BI
25 BI G0_EDC_1 G1_EDC_1 BI 25 26 BI H0_EDC_1 H1_EDC_1 BI 26
25 G0_DBI_0 H6 G0_DBI_0 G1_DBI_0 C16 G1_DBI_0 25 26 H0_DBI_0 AA8 H0_DBI_0 H1_DBI_0 F1 H1_DBI_0 26
BI G0_DBI_1 G14 C6 G1_DBI_1
BI BI H0_DBI_1 P9 T1 H1_DBI_1
BI
25 BI G0_DBI_1 G1_DBI_1 BI 25 26 BI H0_DBI_1 H1_DBI_1 BI 26
25 G0_DQ15 D13 G0_DQ15 G1_DQ15 D5 G1_DQ15 25 26 H0_DQ15 R4 H0_DQ15 H1_DQ15 V1 H1_DQ15 26

BI G0_DQ14 H13 C4 G1_DQ14
BI BI H0_DQ14 R8 V3 H1_DQ14
BI
25 BI G0_DQ14 G1_DQ14 BI 25 26 BI H0_DQ14 H1_DQ14 BI 26
25 G0_DQ13 F13 G0_DQ13 G1_DQ13 E6 G1_DQ13 25 26 H0_DQ13 R6 H0_DQ13 H1_DQ13 U2 H1_DQ13 26
BI G0_DQ12 G11 B5 G1_DQ12
BI BI H0_DQ12 T5 U4 H1_DQ12
BI
25 G0_DQ11 D15 G0_DQ11 G1_DQ11 B8 G1_DQ11 25 26 H0_DQ11 N6 H0_DQ11 H1_DQ11 R2 H1_DQ11 26
BI G0_DQ10 F15 C9 G1_DQ10
BI BI H0_DQ10 P7 P3 H1_DQ10
BI
25 G0_DQ9 H17 G0_DQ9 G1_DQ9 E9 G1_DQ9 25 26 H0_DQ9 L5 H0_DQ9 H1_DQ9 P1 H1_DQ9 26
BI G0_DQ8 G16 A9 G1_DQ8
BI BI H0_DQ8 N8 N4 H1_DQ8
BI
B 25 BI G0_DQ7
G0_DQ6
J9
F8
G0_DQ7 G1_DQ7 E18
B17
G1_DQ7
G1_DQ6
BI 25 26 BI H0_DQ7
H0_DQ6
Y7
W6
H0_DQ7 H1_DQ7 D3
E2
H1_DQ7
H1_DQ6
BI 26
B
25 G0_DQ5 J7 G0_DQ5 G1_DQ5 A16 G1_DQ5 25 26 H0_DQ5 Y5 H0_DQ5 H1_DQ5 F3 H1_DQ5 26
BI G0_DQ4 D8 D17 G1_DQ4
BI BI H0_DQ4 W8 E4 H1_DQ4
BI
25 G0_DQ3 K8 G0_DQ3 G1_DQ3 B15 G1_DQ3 25 26 H0_DQ3 AB7 H0_DQ3 H1_DQ3 H4 H1_DQ3 26
BI G0_DQ2 J5 C14 G1_DQ2
BI BI H0_DQ2 AA4 J1 H1_DQ2
BI
25 G0_DQ1 L7 G0_DQ1 G1_DQ1 A14 G1_DQ1 25 26 H0_DQ1 AC8 H0_DQ1 H1_DQ1 J3 H1_DQ1 26
BI G0_DQ0 K6 E14 G1_DQ0
BI BI H0_DQ0 AB5 K2 H1_DQ0
BI
25 G_CK_P K11 G_CK_P 26 H_CK_P W11 H_CK_P

OUT G_CK_N L13
OUT H_CK_N V10
25 OUT G_CK_N 26 OUT H_CK_N
25 G_DRAM_RESET L16 G_DRAM_RESET 26 H_DRAM_RESET V12 H_DRAM_RESET
OUT FGHIJ_MEM_VREF AT9
OUT
FGHIJ_MEM_VREF
GHIJ_MEM_CALR AR10 GHIJ_MEM_CALR M1090982-001 BGA2963
1 R111 M1090982-001 BGA2963
118 OHM
1%
2 CH
201
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: MEMORY: PARTITION I & J

D D
U1 U1 IC
IC ARDEN
ARDEN 12 OF 35
11 OF 35 MEMORY CHANNEL J0-J1
MEMORY CHANNEL I0-I1 28 J0_CKE_N BB9 J0_CKE_N J1_CKE_N BD9 J1_CKE_N 28
I0_CKE_N AN12 AM9 I1_CKE_N
OUT OUT
27 OUT I0_CKE_N I1_CKE_N OUT 27
28 J0_CABI AY11 J0_CABI J1_CABI BA10 J1_CABI 28
I0_CABI AK12 AH9 I1_CABI
BI J0_CA9 AW12 AT10 J1_CA9
BI
27 BI I0_CABI I1_CABI BI 27 28 BI J0_CA9 J1_CA9 BI 28
27 I0_CA9 AJ11 I0_CA9 I1_CA9 AD10 I1_CA9 27 28 J0_CA8 AY12 J0_CA8 J1_CA8 BA8 J1_CA8 28
BI I0_CA8 AL12 AG10 I1_CA8
BI BI J0_CA7 BC12 BD12 J1_CA7
BI
27 BI I0_CA8 I1_CA8 BI 27 28 BI J0_CA7 J1_CA7 BI 28
27 I0_CA7 AP11 I0_CA7 I1_CA7 AK10 I1_CA7 27 28 J0_CA6 BD11 J0_CA6 J1_CA6 BG9 J1_CA6 28
BI I0_CA6 AR11 AP9 I1_CA6
BI BI J0_CA5 BB12 BD10 J1_CA5
BI
27 I0_CA5 AP12 I0_CA5 I1_CA5 AL11 I1_CA5 27 28 J0_CA4 BA11 J0_CA4 J1_CA4 AY9 J1_CA4 28
BI I0_CA4 AM11 AF10 I1_CA4
BI BI J0_CA3 BF11 BF8 J1_CA3
BI
I0_CA3 AT12 AN10 I1_CA3 J0_CA2 AU11 AW10 J1_CA2
C 27
27
BI
BI I0_CA2 AG12
I0_CA3
I0_CA2
I1_CA3
I1_CA2 AF9 I1_CA2
BI
BI
27
27
28
28
BI
BI J0_CA1 BG10
J0_CA2
J0_CA1
J1_CA2
J1_CA1 BF10 J1_CA1
BI
BI
28
28 C
27 I0_CA1 AU12 I0_CA1 I1_CA1 AM10 I1_CA1 27 28 J0_CA0 AV10 J0_CA0 J1_CA0 AV9 J1_CA0 28
BI I0_CA0 AH12 AE8 I1_CA0
BI BI BI
27 BI I0_CA0 I1_CA0 BI 27
28 J0_WCK0_P AY5 J0_WCK0_P J1_WCK0_P AV3 J1_WCK0_P 28
I0_WCK0_P AJ6 AE4 I1_WCK0_P
OUT J0_WCK0_N AW4 AU4 J1_WCK0_N
OUT
27 OUT I0_WCK0_P I1_WCK0_P OUT 27 28 OUT J0_WCK0_N J1_WCK0_N OUT 28
27 I0_WCK0_N AH5 I0_WCK0_N I1_WCK0_N AF3 I1_WCK0_N 27 28 J0_WCK1_P AY7 J0_WCK1_P J1_WCK1_P AV1 J1_WCK1_P 28
OUT I0_WCK1_P AJ8 AE2 I1_WCK1_P
OUT OUT J0_WCK1_N BA6 AW2 J1_WCK1_N
OUT
27 OUT I0_WCK1_P I1_WCK1_P OUT 27 28 OUT J0_WCK1_N J1_WCK1_N OUT 28
27 I0_WCK1_N AK7 I0_WCK1_N I1_WCK1_N AD1 I1_WCK1_N 27
OUT OUT J0_EDC_0 AU8 AR2 J1_EDC_0
28 BI J0_EDC_0 J1_EDC_0 BI 28
27 I0_EDC_0 AF7 I0_EDC_0 I1_EDC_0 AJ2 I1_EDC_0 27 28 J0_EDC_1 BC8 J0_EDC_1 J1_EDC_1 BB1 J1_EDC_1 28
BI I0_EDC_1 AN8 AB3 I1_EDC_1
BI BI BI
27 BI I0_EDC_1 I1_EDC_1 BI 27
28 J0_DBI_0 AU6 J0_DBI_0 J1_DBI_0 AP1 J1_DBI_0 28
I0_DBI_0 AF5 AJ4 I1_DBI_0
BI J0_DBI_1 BC6 BC2 J1_DBI_1
BI
27 BI I0_DBI_0 I1_DBI_0 BI 27 28 BI J0_DBI_1 J1_DBI_1 BI 28
27 I0_DBI_1 AM5 I0_DBI_1 I1_DBI_1 AA2 I1_DBI_1 27
BI BI J0_DQ15 BB7 BG3 J1_DQ15
28 BI J0_DQ15 J1_DQ15 BI 28
27 I0_DQ15 AL6 I0_DQ15 I1_DQ15 W2 I1_DQ15 27 28 J0_DQ14 BB5 J0_DQ14 J1_DQ14 BF2 J1_DQ14 28
BI I0_DQ14 AL8 W4 I1_DQ14
BI BI J0_DQ13 BC4 BD3 J1_DQ13
BI
27 BI I0_DQ14 I1_DQ14 BI 27 28 BI J0_DQ13 J1_DQ13 BI 28
27 I0_DQ13 AM7 I0_DQ13 I1_DQ13 Y1 I1_DQ13 27 28 J0_DQ12 BA4 J0_DQ12 J1_DQ12 BD1 J1_DQ12 28
BI I0_DQ12 AK5 Y3 I1_DQ12
BI BI J0_DQ11 BD7 BB3 J1_DQ11
BI
27 I0_DQ11 AN4 I0_DQ11 I1_DQ11 AB1 I1_DQ11 27 28 J0_DQ10 BD5 J0_DQ10 J1_DQ10 AY1 J1_DQ10 28
BI I0_DQ10 AN6 AC4 I1_DQ10
BI BI J0_DQ9 BF6 BA2 J1_DQ9
BI
27 I0_DQ9 AP5 I0_DQ9 I1_DQ9 AC2 I1_DQ9 27 28 J0_DQ8 BF4 J0_DQ8 J1_DQ8 AY3 J1_DQ8 28
BI BI BI BI
B 27 BI I0_DQ8
I0_DQ7
AP7
AG6
I0_DQ8 I1_DQ8 AD3
AL4
I1_DQ8
I1_DQ7
BI 27 28 BI J0_DQ7
J0_DQ6
AV5
AW8
J0_DQ7 J1_DQ7 AM3
AM1
J1_DQ7
J1_DQ6
BI 28
B
27 I0_DQ6 AG4 I0_DQ6 I1_DQ6 AL2 I1_DQ6 27 28 J0_DQ5 AV7 J0_DQ5 J1_DQ5 AP3 J1_DQ5 28
BI I0_DQ5 AG8 AK3 I1_DQ5
BI BI J0_DQ4 AW6 AN2 J1_DQ4
BI
27 I0_DQ4 AH7 I0_DQ4 I1_DQ4 AK1 I1_DQ4 27 28 J0_DQ3 AT7 J0_DQ3 J1_DQ3 AR4 J1_DQ3 28
BI I0_DQ3 AD5 AH1 I1_DQ3
BI BI J0_DQ2 AT5 AT1 J1_DQ2
BI
27 I0_DQ2 AE6 I0_DQ2 I1_DQ2 AG2 I1_DQ2 27 28 J0_DQ1 AR6 J0_DQ1 J1_DQ1 AT3 J1_DQ1 28
BI I0_DQ1 AC6 AH3 I1_DQ1
BI BI J0_DQ0 AR8 AU2 J1_DQ0
BI
27 I0_DQ0 AD7 I0_DQ0 I1_DQ0 AF1 I1_DQ0 27
BI BI J_CK_P BC11
28 OUT J_CK_P
27 I_CK_P AK9 I_CK_P 28 J_CK_N BB10 J_CK_N
OUT I_CK_N AJ10
OUT J_DRAM_RESET AV11
27 OUT I_CK_N 28 OUT J_DRAM_RESET
27 I_DRAM_RESET AH11 I_DRAM_RESET
OUT
M1090982-001 BGA2963
M1090982-001 BGA2963
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DEBUG, SB SIGNALS, VOLTAGE SENSE

D D
U1 IC
ARDEN
15 OF 35
JTAG-DEBUG-MISC
ANATSTIN_P BC15 ANATSTIN_P
ANATSTIN_N BD15 ANATSTIN_N
ANATSTOUT_P BE14 ANATSTOUT_P

ANATSTOUT_N BF14 ANATSTOUT_N
32 DBREQ_L BL3 DBREQ_N THERMDA BK46 THERMDA

IN SOC_TCK BL2 BJ46 THERMDC
32 IN TCK THERMDC
32 SOC_TDI BM3 TDI
IN SOC_TDO BH1 BG5 ANALOGOUT0
32 OUT TDO ANALOGOUT0
32 SOC_TMS BJ1 TMS ANALOGOUT1 BG7 ANALOGOUT1
IN TRST_L BM4
32 IN TRST_N
RTC_RETAIL BE13 DIECRACKMON
DIECRACKMON
R84 X32K_X1 BT52 X32K_X1
32 X32K_X2_R 1 2 X32K_X2 BR53 X32K_X2 BP_0 BK42 BP_0
IN BJ42 BP_1 V_SOC1P8
0 OHM 5% BP_1
402 CH R97 SVC_R_SOC BT44 SVC0 BP_2 BF42 BP_2
1 2 SVD_R_SOC BR43 BE42 BP_3
C 20 MOHM 5% SVT_R_SOC BP44
SVD0
SVT0
BP_3
1 R438 C
402 CH TMON_CAL0 BH6 TMON_CAL0 1 KOHM
RTC_XDK 1SVC1 BP42 BJ47 PCC 1% V_SOC1P8_VDD
DB255 SVC1 PCC
TP 15 1SVD1 BN42 BL6 2 CH
DB256 SVD1 PSEN 402
Y1 TP 1SVT1 BN44 BT13 A0_BYPASS
DB257 SVT1 A0_BYPASS
2 1 SIC TP BN5 SOC_SIC
SID BP5 SOC_SID VR_MEMIO_CTL BJ53 VR_MEMIO_CTL 1 R418 1 R260
SM PWROK BH2 SOC_PWR_OK 10 KOHM
C144 C155 IN 32 38
1% 10 KOHM
1 XTAL 1 MST_SIC0 BT15 MST_SIC0 1%
RTC_XDK 32.768 KHZ RTC_XDK MST_SID0 BR15 BH11 SOC_RST_N 2 EMPTY
MST_SID0 RESET_N IN 32 402 2 CH
402 2.2 PF RTC_XDK 402 2.2 PF BJ10 SOC_THERMTRIP_N 201
THERMTRIP_N OUT 32
NP0 50 V 50 V NP0 MST_SIC1 BM15 BT9 SP_SMC_INT_N
2 2 MST_SIC1 ALERT_N OUT 32
+/-0.25PF +/-0.25PF MST_SID1 BM16 MST_SID1
PROCHOT_N BG1 PROCHOT_N
29 QSS_N BL43 QSS_N
C144, C155 VALUE SELECTED OUT QSS1_N BL44 15 BM54 1P8V_GPIO0 1
QSS1_N 1P8V_GPIO0 DB258
TO CENTER XTAL FREQ 29 QSIO3 BG43 QSIO3 1P8V_GPIO1 BN55 1P8V_GPIO1 1 TP
OUT QSIO2 BH43 TP DB259
R1002 29 OUT QSIO2
38 SVC 1 2 29 QSIO1 BH44 QSIO1 3P3V_CIO_PLUG_DET BM51 3P3V_CIO_PLUG_DET
OUT IN QSIO0 BK44 BL51 3P3V_SLEEP_S3_N
R1001 0 OHM 5% 29 OUT QSIO0 3P3V_SLEEP_S3_N OUT 44 R254
201 CH 29 QSCLK BM43 QSCLK 3P3V_FORCE_PWR BL52 3P3V_FORCE_PWR 44 15 1P8V_GPIO0 1 2 SVD1 15
38 BI SVD 1 2 OUT OUT
0 OHM 5%
B SVT 1
R1000
2
0 OHM
201
5%
CH M1090982-001 BGA2963 201 EMPTY
B
38 IN
0 OHM 5%
201 CH
R431 1 DB4
SB_SOC_CLK 1 2 TP
32 IN 1 DB6
243 OHM 1% TP
1 402 CH IC U1 1 DB8
C554 ARDEN TP
47 PF 1 DB10
5% 14 OF 35 TP
50 V
2 EMPTY VOLTAGE SENSE
402 VDD_GFX_SENSE BT41 SOC_GFXCORE_S 38
BR41 SOC_GFXCORE_S_RTN
OUT
VSS_GFX_SENSE OUT 38
R430
32 SB_SOC_DATA 1 2
BI VDD_CPU_SENSE AY15 SOC_CPUCORE_S
OUT 38
243 OHM 1% VSS_CPU_SENSE AW15 SOC_CPUCORE_S_RTN 38
1
C553 402 CH OUT
47 PF VDD_SOC_SENSE R17 SOC_VSOC_S 45
5%
R16 SOC_VSOC_S_RTN
OUT
50 V VSS_SOC_SENSE OUT 45
2 EMPTY
402 P43 SOC_MEMIO_S
VDD_MEM_SENSE OUT 45
VSS_MEM_SENSE P44 SOC_MEMIO_S_RTN 45
OUT
VDD_MEMP_SENSE P13 SOC_MEMPHY_S 45
N14 SOC_MEMPHY_S_RTN
OUT
VSS_MEMP_SENSE OUT 45
BGA2963 M1090982-001
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DECOUPLING
V_GFXCORE V_GFXCORE 22UF 0603 DECOUPLING (116) V_GFXCORE V_GFXCORE
V_GFXCORE 10UF 0603 DECOUPLING (53)
D D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1514 C462 C912 C969 C1011 C1266 C1273 C1283 C1324 C1335 C1451 C1569 C1475 C1554 C1574 C1465 C1452 C1489 C1580 C1510 1 1 1 1 1 1 1 1 1 1
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF C1573 C1532 C1502 C1562 C1483 C1461 C1472 C1476 C1572 C1575
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
603 603 603 603 603 603 603 603 603 603
V_GFXCORE V_GFXCORE V_GFXCORE
1 1
1
C1560
1
C1457
1
C1555
1
C1505
1
C1445
1
C1456
1
C1495
1
C1564
1
C1494
1
C1565
1
C1582 C255 1
C1581 C261 1 C263 1 C274 1 C278 1 C280 1 C293 1 C295 1
C1544
1
C1556
1
C1541
1
C1520
1
C1533
1
C1543
1
C1517
1
C1516
1
C1524
1
C1576
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
C V_GFXCORE V_GFXCORE V_GFXCORE C
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
C1531
22 UF
C1559
22 UF
C1540
22 UF
C1549
22 UF
C1447
22 UF
C1458
22 UF
C1449
22 UF
C1497
22 UF
C1496
22 UF
C1506
22 UF C254 1 C256 1 C260 1 C262 1 C264 1 C277 1 C279 1 C281 1 C294 1 C296 C1521
10 UF
C1534
10 UF
C1490
10 UF
C1477
10 UF
C1446
10 UF
C1463
10 UF
C1469
10 UF
C1487
10 UF
C1501
10 UF
C1529
10 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 603 603 603 603 603 603 603 603 603 603
603 603 603 603 603 603 603 603 603 603
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1561 C1530 C1507 C1550 C1448 C1459 C1563 C1474 C1485 C1508 C1594 C1598 C1602 C1606 C1610 C1614 C1618 C1622 C1626 C1630 C1518 C328 C1542 C1567 C1523 C1460 C1473 C1484 C1498 C1481
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
B 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
B
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1591 C1595 C1599 C1603 C1607 C1611 C1615 C1619 C1623 C1627 C1552 C1668 C1486 C1500 C1509 1 C1522 C1566 C1571 C1482 C1471 C1464 C1578 C1488 C1579 C1470
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF C253 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 22 UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
2 X5R 603 603 603 603 603 603 603 603 603 603
603
V_GFXCORE V_GFXCORE
1 1 1
1 1 1 1 1 1 1 1 1 1 C1515 C1528 C1539
C1592 C1596 C1450 C1604 C1631 C1612 C1616 C1620 C1624 C1628 10 UF 10 UF 10 UF
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 20% 20% 20%
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 6.3 V 6.3 V 6.3 V
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 2 X5R 2 X5R 2 X5R
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 603 603 603
603 603 603 603 603 603 603 603 603 603
A A
V_GFXCORE
1 1 1 1 1 1 1 1 1 1
C1593 C1597 C1601 C1605 C1609 C1613 C1617 C1621 C1625 C1629
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 603 603 603 603 603 603

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DECOUPLING
V_GFXCORE V_GFXCORE 22UF 0603 DECOUPLING (53) V_CPUCORE V_CPUCORE 22UF 0603 DECOUPLING (61) V_CPUCORE
V_CPUCORE 1UF 0201 DECOUPLING (4)
D D
1 1 1 1 1 1 1 1 1 1
C1694 C1700 C1706 C1712 C1718 C1724 C1748 C670 C672 C678 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF C1525 C1468 C1672 C1480 C1671 C1538 C1454 C1467 C1667 C1590 C151 C166 C167 C168
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 1 UF 1 UF 1 UF 1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603
603 603 603 603 603 603 603 603 603 603 201 201 201 201
V_GFXCORE V_CPUCORE
V_CPUCORE
V_CPUCORE 10UF 0603 DECOUPLING (8)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C309 C333 C352 C443 C671 C673 C684 C685 C686 C687 C1722 C1703 C1716 C308 C1721 C307 C1733 C1740 C1728 C1734 1 1 1 1 1 1 1 1
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF C1513 C1492 C1546 C1586 C1466 C1478 C1585 C1493
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603
V_GFXCORE V_CPUCORE
C C
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1693 C1699 C1705 C1711 C1717 C1723 C1729 C1735 C1741 C1747 C1634 C1638 C1642 C1646 C1650 C1654 C1658 C1662 C1666 C1670
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
V_GFXCORE V_CPUCORE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
V_GFXCORE V_CPUCORE
B B
1 1 1 1 1 1 1 1 1 1
C1674 C1676 C1678 C1680 C1682 C1684 C1686 C1688 C1690 C1692 1 1 1 1 1 1 1 1 1 1
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF C1632 C1636 C1640 C1644 C1648 C1652 C1656 C1660 C1664 C1504
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 603 603 603 603 603 603
603 603 603 603 603 603 603 603 603 603
V_GFXCORE V_CPUCORE
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C330 C351 C389 C1512 C1635 C1639 C1643 C1647 C1651 C1655 C1659 C1663 C1526 C1479
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603 603 603 603 603
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEMPHY V_MEMIO
V_MEMPHY 1UF 201 DECOUPLING (87) SOC: DECOUPLING V_MEMIO 1UF 201 DECOUPLING (54)
1 1 1 1 1 1 1 1 1 1
V_SOC 1 1 1 1 1 1 1 1 1 1
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20% V_SOC 22UF 0603 DECOUPLING (13) 1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
D 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R
D
201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201
1 1 1 1 1 1 1 1 1 1
C688 C690 C691 C692 C693 C694 C702 C696 C697 C698
V_MEMPHY 22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
V_MEMIO
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 603 603 603 603 603 603 603 603
1 1 1 1 1 1 1 1 1 1
V_SOC 1 1 1 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201
1 1 1
V_MEMPHY C699 C700 C701 V_MEMIO
22 UF 22 UF 22 UF
20% 20% 20%
6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R
603 603 603
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C766 C771 C783 C790 C798 C803 C807 C813 C817 C828 V_SOC C338 C628 C356 C362 C385 C394 C399 C406 C632 C415
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
V_SOC 1UF 0201 DECOUPLING (4) 20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
C 201 201 201 201 201 201 201 201 201 201
1 1 1 1
201 201 201 201 201 201 201 201 201 201
C
V_MEMPHY C570 C854 C576 C578 V_MEMIO
1 UF 1 UF 1 UF 1 UF
20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R
201 201 201 201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201
V_MEMPHY V_MEMIO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201
B V_MEMPHY V_MEMIO B
1 1 1 1 1 1 1 1 1 1
C418 C419 C437 C484 C510 C512 C513 C514 C515 C516 1 1 1 1
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF C605 C610 C613 C616
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 1 UF 1 UF 1 UF 1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V
201 201 201 201 201 201 201 201 201 201
2 X5R 2 X5R 2 X5R 2 X5R
201 201 201 201
V_MEMPHY
1 1 1 1 1 1 1 1 1 1
C531 C537 C544 C547 C555 C558 C560 C562 C565 C567
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
201 201 201 201 201 201 201 201 201 201
V_MEMPHY
1 1 1 1 1 1 1 1 1 1
C533 C538 C545 C548 C556 C559 C561 C563 C566 C569
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
A 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R
A
201 201 201 201 201 201 201 201 201 201
V_MEMPHY
1 1 1 1 1 1 1
C535 C541 C546 C551 C557 C768 C780
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
201 201 201 201 201 201 201
PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL A: 8GB

GDDR6_BASE
D V_MEMIO U1006 IC D
GDDR6_SGRAM_180P GDDR6_BASE
2 OF 2
A1 VDD_1 U1006 IC
V1 VDD_2 GDDR6_SGRAM_180P
H2 VDD_3 VSS_1 B1 1 OF 2
L2 VDD_4 VSS_2 D1 10 A0_CA0 H3 CA0_A DQ0_A B4 A0_DQ0 10
E5 F1
IN A0_CA1 G11 A3 A0_DQ1
BI
VDD_5 VSS_3 10 IN CA1_A DQ1_A BI 10
P5 VDD_6 VSS_4 G1 10 A0_CA2 G4 CA2_A DQ2_A B3 A0_DQ2 10
E10 M1
IN A0_CA3 H12 B2 A0_DQ3
BI
P10 VDD_8 VSS_6 N1 10 A0_CA4 H5 CA4_A DQ4_A E3 A0_DQ4 10
H13 R1
IN A0_CA5 H10 E2 A0_DQ5
BI
L13 VDD_10 VSS_8 U1 10 A0_CA6 J12 CA6_A DQ6_A F2 A0_DQ6 10
A14 A2
IN A0_CA7 J11 G2 A0_DQ7
BI
V14 VDD_12 VSS_10 V2 10 A0_CA8 J4 CA8_A DQ8_A B11 A0_DQ8 10
C3
IN A0_CA9 J3 A12 A0_DQ9
BI
VSS_11 10 IN CA9_A DQ9_A BI 10
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 A0_DQ10 10
E1 F3 A1_CA0 L3 B13 A0_DQ11
BI
VDDQ_2 VSS_13 10 IN CA0_B DQ11_A BI 10
H1 VDDQ_3 VSS_14 G3 10 A1_CA1 M11 CA1_B DQ12_A E12 A0_DQ12 10
L1 M3
IN A1_CA2 M4 E13 A0_DQ13
BI
P1 VDDQ_5 VSS_16 N3 10 A1_CA3 L12 CA3_B DQ14_A F13 A0_DQ14 10
T1 R3
IN A1_CA4 L5 G13 A0_DQ15
BI
J2 VDDQ_7 VSS_18 T3 10 A1_CA5 L10 CA5_B
K2 A4
IN A1_CA6 K12 C2 A0_EDC_0
C C4
VDDQ_8
VDDQ_9
VSS_19
VSS_20 E4
10
10
IN
IN A1_CA7 K11
CA6_B
CA7_B
EDC0_A
EDC1_A C13 A0_EDC_1
OUT
OUT
10
10 C
F4 VDDQ_10 VSS_21 H4 10 A1_CA8 K4 CA8_B
N4 L4
IN A1_CA9 K3 D2 A0_DBI_0
VDDQ_11 VSS_22 10 IN CA9_B DBI0_A_N BI 10
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 A0_DBI_1 10
B5 V4 A0_CABI J5
BI
VDDQ_13 VSS_24 10 IN CABI_A_N
U5 VDDQ_14 VSS_25 C5 10 A1_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 10 A0_CKE_N G10 CKE_A_N DQ0_B U4 A1_DQ0 10
C11 T10
IN A1_CKE_N M10 V3 A1_DQ1
BI
VDDQ_17 VSS_28 10 IN CKE_B_N DQ1_B BI 10
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 A1_DQ2 10
N11 E11 A_CK_P J10 U2 A1_DQ3
BI
VDDQ_19 VSS_30 10 IN CK_P DQ3_B BI 10
T11 VDDQ_20 VSS_31 H11 10 A_CK_N K10 CK_N DQ4_B P3 A1_DQ4 10
J13 L11
IN P2 A1_DQ5
BI
VDDQ_21 VSS_32 DQ5_B BI 10
K13 VDDQ_22 VSS_33 P11 10 A0_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 A1_DQ6 10
C14 V11
IN A0_WCK1_N D10 M2 A1_DQ7
BI
VDDQ_23 VSS_34 10 IN WCK1_A_N/NC DQ7_B BI 10
E14 VDDQ_24 VSS_35 C12 10 A1_WCK1_P R11 WCK1_B_P DQ8_B U11 A1_DQ8 10
H14 D12
IN A1_WCK1_N R10 V12 A1_DQ9
BI
VDDQ_25 VSS_36 10 IN WCK1_B_N DQ9_B BI 10
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 A1_DQ10 10
P14 G12 A0_WCK0_P D4 U13 A1_DQ11
BI
VDDQ_27 VSS_38 10 IN WCK0_A_P DQ11_B BI 10
V_MEMIO T14 VDDQ_28 VSS_39 M12 10 IN A0_WCK0_N D5 WCK0_A_N DQ12_B P12 A1_DQ12
BI 10
VSS_40 N12 10 A1_WCK0_P R4 WCK0_B_P/NC DQ13_B P13 A1_DQ13 10
A5 R12
IN A1_WCK0_N R5 N13 A1_DQ14
BI
VPP_1 VSS_41 10 IN WCK0_B_N/NC DQ14_B BI 10
B 1 R298
2.37 KOHM
V5
A10
VPP_2 VSS_42 T12
A13 G6_TMS F5
DQ15_B M13 A1_DQ15
BI 10
B
1%
VPP_3 VSS_43 57 28 27 26 25 24 23 22 21 20 BI TMS
V10 VPP_4 VSS_44 V13 57 G6_TDO N10 TDO EDC0_B T2 A1_EDC_0 10
2 CH B14
BI B_TDO F10 T13 A1_EDC_1
OUT
201 VSS_45 20 BI TDI EDC1_B OUT 10
A_VREFC K1 VREFC VSS_46 D14 57 28 27 26 25 24 23 22 21 20 G6_TCK N5 TCK
F14
BI R2 A1_DBI_0
VSS_47 DBI0_B_N BI 10
1 R299 1 A_ZQ_A J14 ZQ_A VSS_48 G14 10 A_DRAM_RESET 1 2 A_DRAM_RESET_C 1 2 A_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 A1_DBI_1 10
5.49 KOHM C1380 A_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R32 R145 M1032794-001 BGA180
2 CH 10 V 1 R300 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
1 R301 G5 RFU_A/NC VSS_51 R14 1 R12 201 CH C130 201 CH
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201
1% 1%
RFU_B/NC VSS_52 1% 5%
2 CH 2 CH 2 CH 2
50 V
C0G V_MEMIO
CHANNEL A DECOUPLING
402 402 M1032794-001 BGA180 201 201
V_MEMIO: 2X22UF 0603 + 20X1UF 0201 PER CHANNEL
V_DRAM1P8 1 1 1 1 1 1 1 1 1 1
C122 C188 C196 C201 C216 C222 C237 C242 C270 C325
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1 1 1 1 1 201 201 201 201 201 201 201 201 201 201
C1381 C1382 C1383 C1384 C1385
10 UF 1 UF 1 UF 1 UF 1 UF
20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V V_MEMIO V_MEMIO
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201
A 1
C1760
1
C47
1
C719
1
C724
1
C341
1
C357
1
C366
1
C377
1
C382
1
C402
1
C1285
1
C1325 A
22 UF 22 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY 603 603 201 201 201 201 201 201 201 201 201 201
ZZ9
I166
M1098563-001 IC U1009,U1003,U1008,U1007,U1002,U1011 GDDR6, SAMSUNG, 16GB GDDR6_SAMSUNG
ZZ11
I167
M1108660-001 IC U1004,U1012,U1005,U1006 GDDR6, SAMSUNG, 8GB GDDR6_SAMSUNG
M1107532-001
ZZ230
I171
IC U1009,U1003,U1008,U1007,U1002,U1011 GDDR6, HYNIX, 16GB GDDR6_HYNIX
M1108913-001
ZZ231
I170
IC U1004,U1012,U1005,U1006 GDDR6, HYNIX, 8GB GDDR6_HYNIX
ZZ21
I175
M1107537-001 IC U1009,U1003,U1008,U1007,U1002,U1011 GDDR6, MICRON, 16GB GDDR6_MICRON
ZZ22
I176
M1107533-001 IC U1004,U1012,U1005,U1006 GDDR6, MICRON, 8GB GDDR6_MICRON

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL B: 16GB

D D
GDDR6_BASE
U1011 IC GDDR6_BASE
V_MEMIO GDDR6_SGRAM_180P
2 OF 2 U1011 IC
A1 VDD_1 GDDR6_SGRAM_180P
V1 VDD_2 1 OF 2
H2 VDD_3 VSS_1 B1 10 B0_CA0 H3 CA0_A DQ0_A B4 B0_DQ0 10
L2 D1
IN B0_CA1 G11 A3 B0_DQ1
BI
E5 VDD_5 VSS_3 F1 10 B0_CA2 G4 CA2_A DQ2_A B3 B0_DQ2 10
P5 G1
IN B0_CA3 H12 B2 B0_DQ3
BI
E10 VDD_7 VSS_5 M1 10 B0_CA4 H5 CA4_A DQ4_A E3 B0_DQ4 10
P10 N1
IN B0_CA5 H10 E2 B0_DQ5
BI
H13 VDD_9 VSS_7 R1 10 B0_CA6 J12 CA6_A DQ6_A F2 B0_DQ6 10
L13 U1
IN B0_CA7 J11 G2 B0_DQ7
BI
A14 VDD_11 VSS_9 A2 10 B0_CA8 J4 CA8_A DQ8_A B11 B0_DQ8 10
V14 V2
IN B0_CA9 J3 A12 B0_DQ9
BI
VSS_11 C3 DQ10_A B12 B0_DQ10 10
C1 D3 B1_CA0 L3 B13 B0_DQ11
BI
E1 VDDQ_2 VSS_13 F3 10 B1_CA1 M11 CA1_B DQ12_A E12 B0_DQ12 10
H1 G3
IN B1_CA2 M4 E13 B0_DQ13
BI
L1 VDDQ_4 VSS_15 M3 10 B1_CA3 L12 CA3_B DQ14_A F13 B0_DQ14 10
IN BI
C P1
T1
VDDQ_5 VSS_16 N3
R3
10 IN B1_CA4
B1_CA5
L5
L10
CA4_B DQ15_A G13 B0_DQ15
BI 10
C
VDDQ_6 VSS_17 10 IN CA5_B
J2 VDDQ_7 VSS_18 T3 10 B1_CA6 K12 CA6_B EDC0_A C2 B0_EDC_0 10
K2 A4
IN B1_CA7 K11 C13 B0_EDC_1
OUT
VDDQ_8 VSS_19 10 IN CA7_B EDC1_A OUT 10
C4 VDDQ_9 VSS_20 E4 10 B1_CA8 K4 CA8_B
F4 H4
IN B1_CA9 K3 D2 B0_DBI_0
N4 VDDQ_11 VSS_22 L4 DBI1_A_N D13 B0_DBI_1 10
T4 P4 B0_CABI J5
BI
B5 VDDQ_13 VSS_24 V4 10 B1_CABI K5 CABI_B_N
U5 C5
IN
VDDQ_14 VSS_25
B10 VDDQ_15 VSS_26 T5 10 B0_CKE_N G10 CKE_A_N DQ0_B U4 B1_DQ8 10
U10 C10
IN B1_CKE_N M10 V3 B1_DQ9
BI
C11 VDDQ_17 VSS_28 T10 DQ2_B U3 B1_DQ10 10
F11 A11 B_CK_P J10 U2 B1_DQ11
BI
N11 VDDQ_19 VSS_30 E11 10 B_CK_N K10 CK_N DQ4_B P3 B1_DQ12 10
T11 H11
IN P2 B1_DQ13
BI
J13 VDDQ_21 VSS_32 L11 10 B0_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 B1_DQ14 10
K13 P11
IN B0_WCK1_N D10 M2 B1_DQ15
BI
C14 VDDQ_23 VSS_34 V11 10 B1_WCK0_P R11 WCK1_B_P DQ8_B U11 B1_DQ0 10
E14 C12
IN B1_WCK0_N R10 V12 B1_DQ1
BI
H14 VDDQ_25 VSS_36 D12 DQ10_B U12 B1_DQ2 10
L14 F12 B0_WCK0_P D4 U13 B1_DQ3
BI
V_DRAM1P8 VDDQ_26 VSS_37 10 IN WCK0_A_P DQ11_B BI 10
P14 G12 B0_WCK0_N D5 P12 B1_DQ4
B V_MEMIO T14
VDDQ_27
VDDQ_28
VSS_38
VSS_39 M12
10
10
IN
IN B1_WCK1_P R4
WCK0_A_N
WCK0_B_P/NC
DQ12_B
DQ13_B P13 B1_DQ5
BI
BI
10
10 B
VSS_40 N12 10 B1_WCK1_N R5 WCK0_B_N/NC DQ14_B N13 B1_DQ6 10
A5 R12
IN M13 B1_DQ7
BI
VPP_1 VSS_41 DQ15_B BI 10
1 R344 V5 VPP_2 VSS_42 T12 57 28 27 26 25 24 23 22 21 19 G6_TMS F5 TMS
2.37 KOHM A10 A13
BI B_TDO N10 T2 B1_EDC_1
1%
VPP_3 VSS_43 19 BI TDO EDC0_B OUT 10
V10 VPP_4 VSS_44 V13 21 C_TDO F10 TDI EDC1_B T13 B1_EDC_0 10
2 CH B14
BI G6_TCK N5
OUT
201 VSS_45 57 28 27 26 25 24 23 22 21 19 BI TCK
B_VREFC K1 VREFC VSS_46 D14 DBI0_B_N R2 B1_DBI_1 10
F14 B_DRAM_RESET 1 2 B_DRAM_RESET_C 1 2 B_DRAM_RESET_R J1 R13 B1_DBI_0
BI
VSS_47 10 IN RESET_N DBI1_B_N BI 10
1 R345 1 B_ZQ_A J14 ZQ_A VSS_48 G14
5.49 KOHM C1434 B_ZQ_B K14 ZQ_B VSS_49 M14 R721 R723 M1032794-001 BGA180
1% 0.1 UF 10 OHM 1% 1 49.9 OHM 1%
10% VSS_50 N14 1 R720 201 CH C722 201 CH
2 CH 10 V 1 R346 R347
201 2 EMPTY
120 OHM
1
120 OHM
G5 RFU_A/NC VSS_51 R14 4.99 KOHM
1%
120 PF
5%
V_MEMIO
CHANNEL B DECOUPLING
201 M5 RFU_B/NC VSS_52 U14 50 V V_MEMIO: 2X22UF 0603 + 20X1UF 0201 PER CHANNEL
1% 1% 2 CH 2 C0G
2 CH 2 CH 201 201
402 402 M1032794-001 BGA180
1 1 1 1 1 1 1 1 1 1
C440 C452 C457 C464 C469 C474 C482 C492 C499 C511
V_DRAM1P8 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
201 201 201 201 201 201 201 201 201 201
1 1 1 1 1 V_MEMIO V_MEMIO
C1435 C1436 C1437 C1438 C1439
20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
A
2 X5R
402
2 X5R
201
2 X5R
201
2 X5R
201
2 X5R
201
A
1 1 1 1 1 1 1 1 1 1 1 1
C1769 C431 C745 C746 C534 C543 C581 C588 C607 C638 C1334 C1340
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL C: 8GB

GDDR6_BASE
D V_MEMIO U1005 IC
GDDR6_BASE
D
GDDR6_SGRAM_180P
2 OF 2
A1 VDD_1 U1005 IC
L2 VDD_4 VSS_2 D1 11 C0_CA0 H3 CA0_A DQ0_A B4 C0_DQ8 11
E5 F1
IN C0_CA1 G11 A3 C0_DQ9
BI
P5 VDD_6 VSS_4 G1 11 C0_CA2 G4 CA2_A DQ2_A B3 C0_DQ10 11
E10 M1
IN C0_CA3 H12 B2 C0_DQ11
BI
P10 VDD_8 VSS_6 N1 11 C0_CA4 H5 CA4_A DQ4_A E3 C0_DQ12 11
H13 R1
IN C0_CA5 H10 E2 C0_DQ13
BI
L13 VDD_10 VSS_8 U1 11 C0_CA6 J12 CA6_A DQ6_A F2 C0_DQ14 11
A14 A2
IN C0_CA7 J11 G2 C0_DQ15
BI
V14 VDD_12 VSS_10 V2 11 C0_CA8 J4 CA8_A DQ8_A B11 C0_DQ0 11
C3
IN C0_CA9 J3 A12 C0_DQ1
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 C0_DQ2 11
E1 F3 C1_CA0 L3 B13 C0_DQ3
BI
H1 VDDQ_3 VSS_14 G3 11 C1_CA1 M11 CA1_B DQ12_A E12 C0_DQ4 11
L1 M3
IN C1_CA2 M4 E13 C0_DQ5
BI
P1 VDDQ_5 VSS_16 N3 11 C1_CA3 L12 CA3_B DQ14_A F13 C0_DQ6 11
T1 R3
IN C1_CA4 L5 G13 C0_DQ7
BI
J2 VDDQ_7 VSS_18 T3 11 C1_CA5 L10 CA5_B
K2 A4
IN C1_CA6 K12 C2 C0_EDC_1
C C4
VDDQ_8
VDDQ_9
VSS_19
VSS_20 E4
11
11
IN
IN C1_CA7 K11
CA6_B
CA7_B
EDC0_A
EDC1_A C13 C0_EDC_0
OUT
OUT
11
11 C
F4 VDDQ_10 VSS_21 H4 11 C1_CA8 K4 CA8_B
N4 L4
IN C1_CA9 K3 D2 C0_DBI_1
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 C0_DBI_0 11
B5 V4 C0_CABI J5
BI
U5 VDDQ_14 VSS_25 C5 11 C1_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 11 C0_CKE_N G10 CKE_A_N DQ0_B U4 C1_DQ0 11
C11 T10
IN C1_CKE_N M10 V3 C1_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 C1_DQ2 11
N11 E11 C_CK_P J10 U2 C1_DQ3
BI
T11 VDDQ_20 VSS_31 H11 11 C_CK_N K10 CK_N DQ4_B P3 C1_DQ4 11
J13 L11
IN P2 C1_DQ5
BI
K13 VDDQ_22 VSS_33 P11 11 C0_WCK0_P D11 WCK1_A_P/NC DQ6_B N2 C1_DQ6 11
C14 V11
IN C0_WCK0_N D10 M2 C1_DQ7
BI
E14 VDDQ_24 VSS_35 C12 11 C1_WCK1_P R11 WCK1_B_P DQ8_B U11 C1_DQ8 11
H14 D12
IN C1_WCK1_N R10 V12 C1_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 C1_DQ10 11
P14 G12 C0_WCK1_P D4 U13 C1_DQ11
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 11 IN C0_WCK1_N D5 WCK0_A_N DQ12_B P12 C1_DQ12
BI 11
VSS_40 N12 11 C1_WCK0_P R4 WCK0_B_P/NC DQ13_B P13 C1_DQ13 11
A5 R12
IN C1_WCK0_N R5 N13 C1_DQ14
BI
VPP_1 VSS_41 11 IN WCK0_B_N/NC DQ14_B BI 11
B 1 R308
2.37 KOHM
V5
A10
VPP_2 VSS_42 T12
A13 G6_TMS F5
DQ15_B M13 C1_DQ15
BI 11
B
1%
VPP_3 VSS_43 57 28 27 26 25 24 23 22 20 19 BI TMS
V10 VPP_4 VSS_44 V13 20 C_TDO N10 TDO EDC0_B T2 C1_EDC_0 11
2 CH B14
BI D_TDO F10 T13 C1_EDC_1
OUT
C_VREFC K1 VREFC VSS_46 D14 57 28 27 26 25 24 23 22 20 19 G6_TCK N5 TCK
F14
BI R2 C1_DBI_0
1 R309 1 C_ZQ_A J14 ZQ_A VSS_48 G14 11 C_DRAM_RESET 1 2 C_DRAM_RESET_C 1 2 C_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 C1_DBI_1 11
5.49 KOHM C1392 C_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R663 R674 M1032794-001 BGA180
2 CH 10 V 1 R310 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
201 120 OHM
1%
120 OHM
1%
M5 RFU_B/NC VSS_52 U14 4.99 KOHM
1%
120 PF
5%
V_MEMIO
CHANNEL C DECOUPLING
2 CH 2 CH 2 CH 2
50 V V_MEMIO: 2X22UF 0603 + 20X1UF 0201 PER CHANNEL
M1032794-001 BGA180 C0G
402 402 201 201
V_DRAM1P8 1 1 1 1 1 1 1 1 1 1
C125 C189 C197 C204 C218 C232 C238 C243 C301 C326
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1 1 1 1 1 201 201 201 201 201 201 201 201 201 201
C1393 C1394 C1395 C1396 C1397
20% 20% 20% 20% 20% V_MEMIO V_MEMIO
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201
1 1
C1762 C62 1 1 1 1 1 1 1 1 1 1
C727 C732 C342 C358 C368 C378 C383 C405 C1294 C1326
A 22 UF
20%
22 UF
20% 1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
A
6.3 V 6.3 V
2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603
201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL D: 16GB

D U1002
GDDR6_BASE
IC
D
V_MEMIO
2 OF 2
A1 VDD_1 U1002 IC
L2 VDD_4 VSS_2 D1 11 D0_CA0 H3 CA0_A DQ0_A B4 D0_DQ8 11
E5 F1
IN D0_CA1 G11 A3 D0_DQ9
BI
P5 VDD_6 VSS_4 G1 11 D0_CA2 G4 CA2_A DQ2_A B3 D0_DQ10 11
E10 M1
IN D0_CA3 H12 B2 D0_DQ11
BI
P10 VDD_8 VSS_6 N1 11 D0_CA4 H5 CA4_A DQ4_A E3 D0_DQ12 11
H13 R1
IN D0_CA5 H10 E2 D0_DQ13
BI
L13 VDD_10 VSS_8 U1 11 D0_CA6 J12 CA6_A DQ6_A F2 D0_DQ14 11
A14 A2
IN D0_CA7 J11 G2 D0_DQ15
BI
V14 VDD_12 VSS_10 V2 11 D0_CA8 J4 CA8_A DQ8_A B11 D0_DQ0 11
C3
IN D0_CA9 J3 A12 D0_DQ1
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 D0_DQ2 11
E1 F3 D1_CA0 L3 B13 D0_DQ3
BI
H1 VDDQ_3 VSS_14 G3 11 D1_CA1 M11 CA1_B DQ12_A E12 D0_DQ4 11
L1 M3
IN D1_CA2 M4 E13 D0_DQ5
BI
P1 VDDQ_5 VSS_16 N3 11 D1_CA3 L12 CA3_B DQ14_A F13 D0_DQ6 11
T1 R3
IN D1_CA4 L5 G13 D0_DQ7
BI
J2 T3 D1_CA5 L10
C K2
VDDQ_7
VDDQ_8
VSS_18
VSS_19 A4
11
11
IN
IN D1_CA6 K12
CA5_B
CA6_B EDC0_A C2 D0_EDC_1
OUT 11 C
C4 VDDQ_9 VSS_20 E4 11 D1_CA7 K11 CA7_B EDC1_A C13 D0_EDC_0 11
F4 H4
IN D1_CA8 K4
OUT
N4 VDDQ_11 VSS_22 L4 11 D1_CA9 K3 CA9_B DBI0_A_N D2 D0_DBI_1 11
T4 P4
IN D13 D0_DBI_0
BI
VDDQ_12 VSS_23 DBI1_A_N BI 11
B5 VDDQ_13 VSS_24 V4 11 D0_CABI J5 CABI_A_N
U5 C5
IN D1_CABI K5
VDDQ_14 VSS_25 11 IN CABI_B_N
B10 VDDQ_15 VSS_26 T5
U10 VDDQ_16 VSS_27 C10 11 D0_CKE_N G10 CKE_A_N DQ0_B U4 D1_DQ0 11
C11 T10
IN D1_CKE_N M10 V3 D1_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 D1_DQ2 11
N11 E11 D_CK_P J10 U2 D1_DQ3
BI
T11 VDDQ_20 VSS_31 H11 11 D_CK_N K10 CK_N DQ4_B P3 D1_DQ4 11
J13 L11
IN P2 D1_DQ5
BI
K13 VDDQ_22 VSS_33 P11 11 D0_WCK0_P D11 WCK1_A_P/NC DQ6_B N2 D1_DQ6 11
C14 V11
IN D0_WCK0_N D10 M2 D1_DQ7
BI
E14 VDDQ_24 VSS_35 C12 11 D1_WCK1_P R11 WCK1_B_P DQ8_B U11 D1_DQ8 11
H14 D12
IN D1_WCK1_N R10 V12 D1_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 D1_DQ10 11
P14 G12 D0_WCK1_P D4 U13 D1_DQ11
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 11 IN D0_WCK1_N D5 WCK0_A_N DQ12_B P12 D1_DQ12
BI 11
VSS_40 N12 11 D1_WCK0_P R4 WCK0_B_P/NC DQ13_B P13 D1_DQ13 11
IN BI
B 1 R312
A5
V5
VPP_1 VSS_41 R12
T12
11 IN D1_WCK0_N R5 WCK0_B_N/NC DQ14_B N13
M13
D1_DQ14
D1_DQ15
BI 11
B
2.37 KOHM A10 A13 G6_TMS F5
1%
VPP_3 VSS_43 57 28 27 26 25 24 23 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 21 D_TDO N10 TDO EDC0_B T2 D1_EDC_0 11
2 CH B14
BI E_TDO F10 T13 D1_EDC_1
OUT
D_VREFC K1 VREFC VSS_46 D14 57 28 27 26 25 24 23 21 20 19 G6_TCK N5 TCK
F14
BI R2 D1_DBI_0
1 R313 1 D_ZQ_A J14 ZQ_A VSS_48 G14 11 D_DRAM_RESET 1 2 D_DRAM_RESET_C 1 2 D_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 D1_DBI_1 11
5.49 KOHM C1398 D_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R676 R678 M1032794-001 BGA180
2 CH 10 V 1 R314 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL D DECOUPLING
2 CH 2 CH
M1032794-001 BGA180 2 CH 2 C0G V_MEMIO: 2X22UF 0603 + 20X1UF 0201 PER CHANNEL
402 402 201 201
V_DRAM1P8 1 1 1 1 1 1 1 1 1 1
C442 C453 C517 C458 C476 C465 C470 C485 C494 C500
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
201 201 201 201 201 201 201 201 201 201
1 1 1 1 1
C1399 C1400 C1401 C1402 C1403
20% 20% 20% 20% 20% V_MEMIO V_MEMIO
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201
A 1
C1763
1
C432
1
C733
1
C734
1
C536
1
C549
1
C582
1
C589
1
C639
1
C618
1
C1336
1
C1341
A
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL E: 16GB

GDDR6_BASE
2 OF 2
A1 VDD_1 U1007 IC
L2 VDD_4 VSS_2 D1 12 E0_CA0 H3 CA0_A DQ0_A B4 E0_DQ0 12
E5 F1
IN E0_CA1 G11 A3 E0_DQ1
BI
P5 VDD_6 VSS_4 G1 12 E0_CA2 G4 CA2_A DQ2_A B3 E0_DQ2 12
E10 M1
IN E0_CA3 H12 B2 E0_DQ3
BI
P10 VDD_8 VSS_6 N1 12 E0_CA4 H5 CA4_A DQ4_A E3 E0_DQ4 12
H13 R1
IN E0_CA5 H10 E2 E0_DQ5
BI
L13 VDD_10 VSS_8 U1 12 E0_CA6 J12 CA6_A DQ6_A F2 E0_DQ6 12
A14 A2
IN E0_CA7 J11 G2 E0_DQ7
BI
V14 VDD_12 VSS_10 V2 12 E0_CA8 J4 CA8_A DQ8_A B11 E0_DQ8 12
C3
IN E0_CA9 J3 A12 E0_DQ9
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 E0_DQ10 12
E1 F3 E1_CA0 L3 B13 E0_DQ11
BI
H1 VDDQ_3 VSS_14 G3 12 E1_CA1 M11 CA1_B DQ12_A E12 E0_DQ12 12
L1 M3
IN E1_CA2 M4 E13 E0_DQ13
BI
P1 VDDQ_5 VSS_16 N3 12 E1_CA3 L12 CA3_B DQ14_A F13 E0_DQ14 12
T1 R3
IN E1_CA4 L5 G13 E0_DQ15
BI
J2 VDDQ_7 VSS_18 T3 12 E1_CA5 L10 CA5_B
IN
C K2
C4
VDDQ_8 VSS_19 A4
E4
12 IN E1_CA6
E1_CA7
K12
K11
CA6_B EDC0_A C2
C13
E0_EDC_0
E0_EDC_1
OUT 12
C
F4 VDDQ_10 VSS_21 H4 12 E1_CA8 K4 CA8_B
N4 L4
IN E1_CA9 K3 D2 E0_DBI_0
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 E0_DBI_1 12
B5 V4 E0_CABI J5
BI
U5 VDDQ_14 VSS_25 C5 12 E1_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 12 E0_CKE_N G10 CKE_A_N DQ0_B U4 E1_DQ0 12
C11 T10
IN E1_CKE_N M10 V3 E1_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 E1_DQ2 12
N11 E11 E_CK_P J10 U2 E1_DQ3
BI
T11 VDDQ_20 VSS_31 H11 12 E_CK_N K10 CK_N DQ4_B P3 E1_DQ4 12
J13 L11
IN P2 E1_DQ5
BI
K13 VDDQ_22 VSS_33 P11 12 E0_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 E1_DQ6 12
C14 V11
IN E0_WCK1_N D10 M2 E1_DQ7
BI
E14 VDDQ_24 VSS_35 C12 12 E1_WCK1_P R11 WCK1_B_P DQ8_B U11 E1_DQ8 12
H14 D12
IN E1_WCK1_N R10 V12 E1_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 E1_DQ10 12
P14 G12 E0_WCK0_P D4 U13 E1_DQ11
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 12 IN E0_WCK0_N D5 WCK0_A_N DQ12_B P12 E1_DQ12
BI 12
VSS_40 N12 12 E1_WCK0_P R4 WCK0_B_P/NC DQ13_B P13 E1_DQ13 12
A5 R12
IN E1_WCK0_N R5 N13 E1_DQ14
BI
B 1 R317 V5
VPP_1
VPP_2
VSS_41
VSS_42 T12
12 IN WCK0_B_N/NC DQ14_B
DQ15_B M13 E1_DQ15
BI
BI
12
12 B
1%
VPP_3 VSS_43 57 28 27 26 25 24 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 22 E_TDO N10 TDO EDC0_B T2 E1_EDC_0 12
2 CH B14
BI F_TDO F10 T13 E1_EDC_1
OUT
E_VREFC K1 VREFC VSS_46 D14 57 28 27 26 25 24 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 E1_DBI_0
1 R319 1 E_ZQ_A J14 ZQ_A VSS_48 G14 12 E_DRAM_RESET 1 2 E_DRAM_RESET_C 1 2 E_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 E1_DBI_1 12
5.49 KOHM C1404 E_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R680 R683 M1032794-001 BGA180
2 CH 10 V 1 R320 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL E DECOUPLING
2 CH 2 CH
402 402 201 201
V_DRAM1P8 1 1 1 1 1 1 1 1 1 1
C181 C198 C205 C219 C234 C239 C244 C315 C346 C331
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1 1 1 1 1 201 201 201 201 201 201 201 201 201 201
C1405 C1406 C1407 C1408 C1409
20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201
A 1
C1764
1
C63
1
C735
1
C736
1
C191
1
C363
1
C370
1
C379
1
C386
1
C411
1
C1321
1
C1327 A
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL F: 16GB

D GDDR6_BASE
D
V_MEMIO U1008 IC
2 OF 2
A1 VDD_1 U1008 IC
L2 VDD_4 VSS_2 D1 12 F1_CA0 H3 CA0_A DQ0_A B4 F1_DQ0 12
E5 F1
IN F1_CA1 G11 A3 F1_DQ1
BI
P5 VDD_6 VSS_4 G1 12 F1_CA2 G4 CA2_A DQ2_A B3 F1_DQ2 12
E10 M1
IN F1_CA3 H12 B2 F1_DQ3
BI
P10 VDD_8 VSS_6 N1 12 F1_CA4 H5 CA4_A DQ4_A E3 F1_DQ4 12
H13 R1
IN F1_CA5 H10 E2 F1_DQ5
BI
L13 VDD_10 VSS_8 U1 12 F1_CA6 J12 CA6_A DQ6_A F2 F1_DQ6 12
A14 A2
IN F1_CA7 J11 G2 F1_DQ7
BI
V14 VDD_12 VSS_10 V2 12 F1_CA8 J4 CA8_A DQ8_A B11 F1_DQ8 12
C3
IN F1_CA9 J3 A12 F1_DQ9
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 F1_DQ10 12
E1 F3 F0_CA0 L3 B13 F1_DQ11
BI
H1 VDDQ_3 VSS_14 G3 12 F0_CA1 M11 CA1_B DQ12_A E12 F1_DQ12 12
L1 M3
IN F0_CA2 M4 E13 F1_DQ13
BI
P1 VDDQ_5 VSS_16 N3 12 F0_CA3 L12 CA3_B DQ14_A F13 F1_DQ14 12
IN BI
C T1
J2
VDDQ_6 VSS_17 R3
T3
12 IN F0_CA4
F0_CA5
L5
L10
CA4_B DQ15_A G13 F1_DQ15
BI 12
C
K2 VDDQ_8 VSS_19 A4 12 F0_CA6 K12 CA6_B EDC0_A C2 F1_EDC_0 12
C4 E4
IN F0_CA7 K11 C13 F1_EDC_1
OUT
F4 VDDQ_10 VSS_21 H4 12 F0_CA8 K4 CA8_B
N4 L4
IN F0_CA9 K3 D2 F1_DBI_0
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 F1_DBI_1 12
B5 V4 F1_CABI J5
BI
U5 VDDQ_14 VSS_25 C5 12 F0_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 12 F1_CKE_N G10 CKE_A_N DQ0_B U4 F0_DQ0 12
C11 T10
IN F0_CKE_N M10 V3 F0_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 F0_DQ2 12
N11 E11 F_CK_P J10 U2 F0_DQ3
BI
T11 VDDQ_20 VSS_31 H11 12 F_CK_N K10 CK_N DQ4_B P3 F0_DQ4 12
J13 L11
IN P2 F0_DQ5
BI
K13 VDDQ_22 VSS_33 P11 12 F1_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 F0_DQ6 12
C14 V11
IN F1_WCK1_N D10 M2 F0_DQ7
BI
E14 VDDQ_24 VSS_35 C12 12 F0_WCK1_P R11 WCK1_B_P DQ8_B U11 F0_DQ8 12
H14 D12
IN F0_WCK1_N R10 V12 F0_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 F0_DQ10 12
P14 G12 F1_WCK0_P D4 U13 F0_DQ11
BI
V_MEMIO T14 M12 F1_WCK0_N D5 P12 F0_DQ12
B VDDQ_28 VSS_39
VSS_40 N12
12
12
IN
IN F0_WCK0_P R4
WCK0_A_N
WCK0_B_P/NC
DQ12_B
DQ13_B P13 F0_DQ13
BI
BI
12
12 B
A5 VPP_1 VSS_41 R12 12 F0_WCK0_N R5 WCK0_B_N/NC DQ14_B N13 F0_DQ14 12
1 R322 V5 T12
IN M13 F0_DQ15
BI
1%
VPP_3 VSS_43 57 28 27 26 25 23 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 23 F_TDO N10 TDO EDC0_B T2 F0_EDC_0 12
2 CH B14
BI G_TDO F10 T13 F0_EDC_1
OUT
F_VREFC K1 VREFC VSS_46 D14 57 28 27 26 25 23 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 F0_DBI_0
1 R323 1 F_ZQ_A J14 ZQ_A VSS_48 G14 12 F_DRAM_RESET 1 2 F_DRAM_RESET_C 1 2 F_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 F0_DBI_1 12
5.49 KOHM C1410 F_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R686 R690 M1032794-001 BGA180
2 CH 10 V 1 R326 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL F DECOUPLING
2 CH 2 CH
402 402 201 201
V_DRAM1P8
1 1 1 1 1 1 1 1 1 1
C444 C454 C459 C466 C477 C488 C495 C501 C539 C521
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
1 1 1 1 1 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
C1411 C1412 C1413 C1414 C1415 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
10 UF 1 UF 1 UF 1 UF 1 UF 201 201 201 201 201 201 201 201 201 201
20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R V_MEMIO V_MEMIO
402 201 201 201 201
A A
1 1 1 1 1 1 1 1 1 1 1 1
C1765 C435 C737 C738 C471 C552 C585 C593 C619 C640 C1337 C1342
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL G: 16GB

GDDR6_BASE
D U1003 IC
D
V_MEMIO
2 OF 2
A1 VDD_1 U1003 IC
L2 VDD_4 VSS_2 D1 13 G1_CA0 H3 CA0_A DQ0_A B4 G1_DQ0 13
E5 F1
IN G1_CA1 G11 A3 G1_DQ1
BI
P5 VDD_6 VSS_4 G1 13 G1_CA2 G4 CA2_A DQ2_A B3 G1_DQ2 13
E10 M1
IN G1_CA3 H12 B2 G1_DQ3
BI
P10 VDD_8 VSS_6 N1 13 G1_CA4 H5 CA4_A DQ4_A E3 G1_DQ4 13
H13 R1
IN G1_CA5 H10 E2 G1_DQ5
BI
L13 VDD_10 VSS_8 U1 13 G1_CA6 J12 CA6_A DQ6_A F2 G1_DQ6 13
A14 A2
IN G1_CA7 J11 G2 G1_DQ7
BI
V14 VDD_12 VSS_10 V2 13 G1_CA8 J4 CA8_A DQ8_A B11 G1_DQ8 13
C3
IN G1_CA9 J3 A12 G1_DQ9
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 G1_DQ10 13
E1 F3 G0_CA0 L3 B13 G1_DQ11
BI
H1 VDDQ_3 VSS_14 G3 13 G0_CA1 M11 CA1_B DQ12_A E12 G1_DQ12 13
L1 M3
IN G0_CA2 M4 E13 G1_DQ13
BI
P1 VDDQ_5 VSS_16 N3 13 G0_CA3 L12 CA3_B DQ14_A F13 G1_DQ14 13
T1 R3
IN G0_CA4 L5 G13 G1_DQ15
BI
J2 T3 G0_CA5 L10
C K2
VDDQ_7
VDDQ_8
VSS_18
VSS_19 A4
13
13
IN
IN G0_CA6 K12
CA5_B
CA6_B EDC0_A C2 G1_EDC_0
OUT 13 C
C4 VDDQ_9 VSS_20 E4 13 G0_CA7 K11 CA7_B EDC1_A C13 G1_EDC_1 13
F4 H4
IN G0_CA8 K4
OUT
N4 VDDQ_11 VSS_22 L4 13 G0_CA9 K3 CA9_B DBI0_A_N D2 G1_DBI_0 13
T4 P4
IN D13 G1_DBI_1
BI
B5 VDDQ_13 VSS_24 V4 13 G1_CABI J5 CABI_A_N
U5 C5
IN G0_CABI K5
U10 VDDQ_16 VSS_27 C10 13 G1_CKE_N G10 CKE_A_N DQ0_B U4 G0_DQ8 13
C11 T10
IN G0_CKE_N M10 V3 G0_DQ9
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 G0_DQ10 13
N11 E11 G_CK_P J10 U2 G0_DQ11
BI
T11 VDDQ_20 VSS_31 H11 13 G_CK_N K10 CK_N DQ4_B P3 G0_DQ12 13
J13 L11
IN P2 G0_DQ13
BI
K13 VDDQ_22 VSS_33 P11 13 G1_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 G0_DQ14 13
C14 V11
IN G1_WCK1_N D10 M2 G0_DQ15
BI
E14 VDDQ_24 VSS_35 C12 13 G0_WCK0_P R11 WCK1_B_P DQ8_B U11 G0_DQ0 13
H14 D12
IN G0_WCK0_N R10 V12 G0_DQ1
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 G0_DQ2 13
P14 G12 G1_WCK0_P D4 U13 G0_DQ3
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 13 IN G1_WCK0_N D5 WCK0_A_N DQ12_B P12 G0_DQ4
BI 13
VSS_40 N12 13 G0_WCK1_P R4 WCK0_B_P/NC DQ13_B P13 G0_DQ5 13
IN BI
B 1 R329
A5
V5
VPP_1 VSS_41 R12
T12
13 IN G0_WCK1_N R5 WCK0_B_N/NC DQ14_B N13
M13
G0_DQ6
G0_DQ7
BI 13
B
1%
VPP_3 VSS_43 57 28 27 26 24 23 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 24 G_TDO N10 TDO EDC0_B T2 G0_EDC_1 13
2 CH B14
BI H_TDO F10 T13 G0_EDC_0
OUT
G_VREFC K1 VREFC VSS_46 D14 57 28 27 26 24 23 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 G0_DBI_1
1 R330 1 G_ZQ_A J14 ZQ_A VSS_48 G14 13 G_DRAM_RESET 1 2 G_DRAM_RESET_C 1 2 G_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 G0_DBI_0 13
5.49 KOHM C1416 G_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R696 R711 M1032794-001 BGA180
2 CH 10 V 1 R331 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201
1% 1%
RFU_B/NC VSS_52 1% 5%
50 V
2 CH 2 CH
M1032794-001 BGA180 2 CH 2 C0G
V_MEMIO
CHANNEL G DECOUPLING
402 402 201 201 V_MEMIO: 2X22UF 0603 + 20X1UF 0201 PER CHANNEL
V_DRAM1P8
1 1 1 1 1 1 1 1 1 1
C186 C194 C199 C208 C235 C240 C247 C323 C347 C332
1 1 1 1 1 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
C1417 C1418 C1419 C1420 C1421 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
10 UF 1 UF 1 UF 1 UF 1 UF 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
20% 20% 20% 20% 20% 201 201 201 201 201 201 201 201 201 201
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201 V_MEMIO V_MEMIO
A A
1 1 1 1 1 1 1 1 1 1 1 1
C1766 C119 C739 C740 C220 C364 C371 C380 C393 C416 C1322 C1328
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL H: 8GB

GDDR6_BASE
2 OF 2
A1 VDD_1 U1012 IC
L2 VDD_4 VSS_2 D1 13 H1_CA0 H3 CA0_A DQ0_A B4 H1_DQ0 13
E5 F1
IN H1_CA1 G11 A3 H1_DQ1
BI
P5 VDD_6 VSS_4 G1 13 H1_CA2 G4 CA2_A DQ2_A B3 H1_DQ2 13
E10 M1
IN H1_CA3 H12 B2 H1_DQ3
BI
P10 VDD_8 VSS_6 N1 13 H1_CA4 H5 CA4_A DQ4_A E3 H1_DQ4 13
H13 R1
IN H1_CA5 H10 E2 H1_DQ5
BI
L13 VDD_10 VSS_8 U1 13 H1_CA6 J12 CA6_A DQ6_A F2 H1_DQ6 13
A14 A2
IN H1_CA7 J11 G2 H1_DQ7
BI
V14 VDD_12 VSS_10 V2 13 H1_CA8 J4 CA8_A DQ8_A B11 H1_DQ8 13
C3
IN H1_CA9 J3 A12 H1_DQ9
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 H1_DQ10 13
E1 F3 H0_CA0 L3 B13 H1_DQ11
BI
H1 VDDQ_3 VSS_14 G3 13 H0_CA1 M11 CA1_B DQ12_A E12 H1_DQ12 13
L1 M3
IN H0_CA2 M4 E13 H1_DQ13
BI
P1 VDDQ_5 VSS_16 N3 13 H0_CA3 L12 CA3_B DQ14_A F13 H1_DQ14 13
T1 R3
IN H0_CA4 L5 G13 H1_DQ15
BI
J2 VDDQ_7 VSS_18 T3 13 H0_CA5 L10 CA5_B
IN
C K2
C4
VDDQ_8 VSS_19 A4
E4
13 IN H0_CA6
H0_CA7
K12
K11
CA6_B EDC0_A C2
C13
H1_EDC_0
H1_EDC_1
OUT 13
C
F4 VDDQ_10 VSS_21 H4 13 H0_CA8 K4 CA8_B
N4 L4
IN H0_CA9 K3 D2 H1_DBI_0
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 H1_DBI_1 13
B5 V4 H1_CABI J5
BI
U5 VDDQ_14 VSS_25 C5 13 H0_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 13 H1_CKE_N G10 CKE_A_N DQ0_B U4 H0_DQ8 13
C11 T10
IN H0_CKE_N M10 V3 H0_DQ9
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 H0_DQ10 13
N11 E11 H_CK_P J10 U2 H0_DQ11
BI
T11 VDDQ_20 VSS_31 H11 13 H_CK_N K10 CK_N DQ4_B P3 H0_DQ12 13
J13 L11
IN P2 H0_DQ13
BI
K13 VDDQ_22 VSS_33 P11 13 H1_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 H0_DQ14 13
C14 V11
IN H1_WCK1_N D10 M2 H0_DQ15
BI
E14 VDDQ_24 VSS_35 C12 13 H0_WCK0_P R11 WCK1_B_P DQ8_B U11 H0_DQ0 13
H14 D12
IN H0_WCK0_N R10 V12 H0_DQ1
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 H0_DQ2 13
P14 G12 H1_WCK0_P D4 U13 H0_DQ3
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 13 IN H1_WCK0_N D5 WCK0_A_N DQ12_B P12 H0_DQ4
BI 13
VSS_40 N12 13 H0_WCK1_P R4 WCK0_B_P/NC DQ13_B P13 H0_DQ5 13
A5 R12
IN H0_WCK1_N R5 N13 H0_DQ6
BI
B 1 R302 V5
VPP_1
VPP_2
VSS_41
VSS_42 T12
DQ15_B M13 H0_DQ7
BI
BI
13
13 B
1%
VPP_3 VSS_43 57 28 27 25 24 23 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 25 H_TDO N10 TDO EDC0_B T2 H0_EDC_1 13
2 CH B14
BI I_TDO F10 T13 H0_EDC_0
OUT
H_VREFC K1 VREFC VSS_46 D14 57 28 27 25 24 23 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 H0_DBI_1
1 R303 1 H_ZQ_A J14 ZQ_A VSS_48 G14 13 H_DRAM_RESET 1 2 H_DRAM_RESET_C 1 2 H_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 H0_DBI_0 13
5.49 KOHM C1386 H_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R150 R661 M1032794-001 BGA180
2 CH 10 V 1 R305 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL H DECOUPLING
2 CH 2 CH
402 402 201 201
V_DRAM1P8
1 1 1 1 1 1 1 1 1 1
C445 C528 C455 C461 C480 C467 C472 C489 C496 C502
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
1 1 1 1 1 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
C1387 C1388 C1389 C1390 C1391 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
10 UF 1 UF 1 UF 1 UF 1 UF 201 201 201 201 201 201 201 201 201 201
20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R V_MEMIO V_MEMIO
402 201 201 201 201
A 1
C1761
1
C438
1
C725
1
C726
1
C540
1
C564
1
C586
1
C594
1
C660
1
C623
1
C1338
1
C1343 A
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL I: 16GB

D GDDR6_BASE
D
V_MEMIO U1009 IC
GDDR6_BASE
GDDR6_SGRAM_180P
2 OF 2
A1 VDD_1 U1009 IC
L2 VDD_4 VSS_2 D1 14 I1_CA0 H3 CA0_A DQ0_A B4 I1_DQ8 14
E5 F1
IN I1_CA1 G11 A3 I1_DQ9
BI
P5 VDD_6 VSS_4 G1 14 I1_CA2 G4 CA2_A DQ2_A B3 I1_DQ10 14
E10 M1
IN I1_CA3 H12 B2 I1_DQ11
BI
P10 VDD_8 VSS_6 N1 14 I1_CA4 H5 CA4_A DQ4_A E3 I1_DQ12 14
H13 R1
IN I1_CA5 H10 E2 I1_DQ13
BI
L13 VDD_10 VSS_8 U1 14 I1_CA6 J12 CA6_A DQ6_A F2 I1_DQ14 14
A14 A2
IN I1_CA7 J11 G2 I1_DQ15
BI
V14 VDD_12 VSS_10 V2 14 I1_CA8 J4 CA8_A DQ8_A B11 I1_DQ0 14
C3
IN I1_CA9 J3 A12 I1_DQ1
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 I1_DQ2 14
E1 F3 I0_CA0 L3 B13 I1_DQ3
BI
H1 VDDQ_3 VSS_14 G3 14 I0_CA1 M11 CA1_B DQ12_A E12 I1_DQ4 14
L1 M3
IN I0_CA2 M4 E13 I1_DQ5
BI
P1 VDDQ_5 VSS_16 N3 14 I0_CA3 L12 CA3_B DQ14_A F13 I1_DQ6 14
T1 R3
IN I0_CA4 L5 G13 I1_DQ7
BI
C J2
K2
VDDQ_7 VSS_18 T3
A4
14 IN I0_CA5
I0_CA6
L10
K12
CA5_B
C2 I1_EDC_1 C
C4 VDDQ_9 VSS_20 E4 14 I0_CA7 K11 CA7_B EDC1_A C13 I1_EDC_0 14
F4 H4
IN I0_CA8 K4
OUT
N4 VDDQ_11 VSS_22 L4 14 I0_CA9 K3 CA9_B DBI0_A_N D2 I1_DBI_1 14
T4 P4
IN D13 I1_DBI_0
BI
B5 VDDQ_13 VSS_24 V4 14 I1_CABI J5 CABI_A_N
U5 C5
IN I0_CABI K5
U10 VDDQ_16 VSS_27 C10 14 I1_CKE_N G10 CKE_A_N DQ0_B U4 I0_DQ0 14
C11 T10
IN I0_CKE_N M10 V3 I0_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 I0_DQ2 14
N11 E11 I_CK_P J10 U2 I0_DQ3
BI
T11 VDDQ_20 VSS_31 H11 14 I_CK_N K10 CK_N DQ4_B P3 I0_DQ4 14
J13 L11
IN P2 I0_DQ5
BI
K13 VDDQ_22 VSS_33 P11 14 I1_WCK0_P D11 WCK1_A_P/NC DQ6_B N2 I0_DQ6 14
C14 V11
IN I1_WCK0_N D10 M2 I0_DQ7
BI
E14 VDDQ_24 VSS_35 C12 14 I0_WCK1_P R11 WCK1_B_P DQ8_B U11 I0_DQ8 14
H14 D12
IN I0_WCK1_N R10 V12 I0_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 I0_DQ10 14
P14 G12 I1_WCK1_P D4 U13 I0_DQ11
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 14 IN I1_WCK1_N D5 WCK0_A_N DQ12_B P12 I0_DQ12
BI 14
N12 I0_WCK0_P R4 P13 I0_DQ13
B A5 VPP_1
VSS_40
VSS_41 R12
14
14
IN
IN I0_WCK0_N R5
WCK0_B_P/NC
WCK0_B_N/NC
DQ13_B
DQ14_B N13 I0_DQ14
BI
BI
14
14 B
1 R333 V5 VPP_2 VSS_42 T12 DQ15_B M13 I0_DQ15 14
BI
1%
VPP_3 VSS_43 57 28 26 25 24 23 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 26 I_TDO N10 TDO EDC0_B T2 I0_EDC_0 14
2 CH B14
BI J_TDO F10 T13 I0_EDC_1
OUT
I_VREFC K1 VREFC VSS_46 D14 57 28 26 25 24 23 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 I0_DBI_0
1 R334 1 I_ZQ_A J14 ZQ_A VSS_48 G14 14 I_DRAM_RESET 1 2 I_DRAM_RESET_C 1 2 I_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 I0_DBI_1 14
5.49 KOHM C1422 I_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
10% VSS_50 N14 R713 R715 M1032794-001 BGA180
2 CH 10 V 1 R336 10 OHM 1% 1 49.9 OHM 1%
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL I DECOUPLING
2 CH 2 CH
402 402 201 201
V_DRAM1P8
1 1 1 1 1 1 1 1 1 1
C324 C335 C348 C365 C381 C376 C401 C420 C1323 C1329
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1 1 1 1 1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
C1423 C1424 C1425 C1426 C1427 201 201 201 201 201 201 201 201 201 201
20% 20% 20% 20% 20%
2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R
V_MEMIO V_MEMIO
402 201 201 201 201
A 1 1 1 1 1 1 1 1 1 1 1 1
A
C1767 C120 C741 C742 C187 C195 C200 C212 C236 C248 C221 C241
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603 201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: GDDR6 CHANNEL J: 8GB

GDDR6_BASE
2 OF 2
A1 VDD_1 U1004 IC
L2 VDD_4 VSS_2 D1 14 J1_CA0 H3 CA0_A DQ0_A B4 J1_DQ0 14
E5 F1
IN J1_CA1 G11 A3 J1_DQ1
BI
P5 VDD_6 VSS_4 G1 14 J1_CA2 G4 CA2_A DQ2_A B3 J1_DQ2 14
E10 M1
IN J1_CA3 H12 B2 J1_DQ3
BI
P10 VDD_8 VSS_6 N1 14 J1_CA4 H5 CA4_A DQ4_A E3 J1_DQ4 14
H13 R1
IN J1_CA5 H10 E2 J1_DQ5
BI
L13 VDD_10 VSS_8 U1 14 J1_CA6 J12 CA6_A DQ6_A F2 J1_DQ6 14
A14 A2
IN J1_CA7 J11 G2 J1_DQ7
BI
V14 VDD_12 VSS_10 V2 14 J1_CA8 J4 CA8_A DQ8_A B11 J1_DQ8 14
C3
IN J1_CA9 J3 A12 J1_DQ9
BI
C1 VDDQ_1 VSS_12 D3 DQ10_A B12 J1_DQ10 14
E1 F3 J0_CA0 L3 B13 J1_DQ11
BI
H1 VDDQ_3 VSS_14 G3 14 J0_CA1 M11 CA1_B DQ12_A E12 J1_DQ12 14
L1 M3
IN J0_CA2 M4 E13 J1_DQ13
BI
P1 VDDQ_5 VSS_16 N3 14 J0_CA3 L12 CA3_B DQ14_A F13 J1_DQ14 14
T1 R3
IN J0_CA4 L5 G13 J1_DQ15
BI
J2 VDDQ_7 VSS_18 T3 14 J0_CA5 L10 CA5_B
IN
C K2
C4
VDDQ_8 VSS_19 A4
E4
14 IN J0_CA6
J0_CA7
K12
K11
CA6_B EDC0_A C2
C13
J1_EDC_0
J1_EDC_1
OUT 14
C
F4 VDDQ_10 VSS_21 H4 14 J0_CA8 K4 CA8_B
N4 L4
IN J0_CA9 K3 D2 J1_DBI_0
T4 VDDQ_12 VSS_23 P4 DBI1_A_N D13 J1_DBI_1 14
B5 V4 J1_CABI J5
BI
U5 VDDQ_14 VSS_25 C5 14 J0_CABI K5 CABI_B_N
B10 T5
IN
VDDQ_15 VSS_26
U10 VDDQ_16 VSS_27 C10 14 J1_CKE_N G10 CKE_A_N DQ0_B U4 J0_DQ0 14
C11 T10
IN J0_CKE_N M10 V3 J0_DQ1
BI
F11 VDDQ_18 VSS_29 A11 DQ2_B U3 J0_DQ2 14
N11 E11 J_CK_P J10 U2 J0_DQ3
BI
T11 VDDQ_20 VSS_31 H11 14 J_CK_N K10 CK_N DQ4_B P3 J0_DQ4 14
J13 L11
IN P2 J0_DQ5
BI
K13 VDDQ_22 VSS_33 P11 14 J1_WCK1_P D11 WCK1_A_P/NC DQ6_B N2 J0_DQ6 14
C14 V11
IN J1_WCK1_N D10 M2 J0_DQ7
BI
E14 VDDQ_24 VSS_35 C12 14 J0_WCK1_P R11 WCK1_B_P DQ8_B U11 J0_DQ8 14
H14 D12
IN J0_WCK1_N R10 V12 J0_DQ9
BI
V_DRAM1P8 L14 VDDQ_26 VSS_37 F12 DQ10_B U12 J0_DQ10 14
P14 G12 J1_WCK0_P D4 U13 J0_DQ11
BI
V_MEMIO T14 VDDQ_28 VSS_39 M12 14 IN J1_WCK0_N D5 WCK0_A_N DQ12_B P12 J0_DQ12
BI 14
VSS_40 N12 14 J0_WCK0_P R4 WCK0_B_P/NC DQ13_B P13 J0_DQ13 14
A5 R12
IN J0_WCK0_N R5 N13 J0_DQ14
BI
B 1 R338 V5
VPP_1
VPP_2
VSS_41
VSS_42 T12
DQ15_B M13 J0_DQ15
BI
BI
14
14 B
1%
VPP_3 VSS_43 57 27 26 25 24 23 22 21 20 19 BI TMS
V10 VPP_4 VSS_44 V13 27 J_TDO N10 TDO EDC0_B T2 J0_EDC_0 14
2 CH B14
BI G6_TDI F10 T13 J0_EDC_1
OUT
J_VREFC K1 VREFC VSS_46 D14 57 27 26 25 24 23 22 21 20 19 G6_TCK N5 TCK
F14
BI R2 J0_DBI_0
1 R341 1 J_ZQ_A J14 ZQ_A VSS_48 G14 14 J_DRAM_RESET 1 2 J_DRAM_RESET_C 1 2 J_DRAM_RESET_R J1 RESET_N DBI1_B_N R13 J0_DBI_1 14
5.49 KOHM C1428 J_ZQ_B K14 M14
IN BI
0.1 UF ZQ_B VSS_49
1%
N14 R717 R719
2 CH
10%
10 V 1 R342
VSS_50 10 OHM 1% 1 49.9 OHM 1% M1032794-001 BGA180
201 2 EMPTY
120 OHM 120 OHM M5 U14 4.99 KOHM 120 PF
201 RFU_B/NC VSS_52
1% 1% 1% 5%
50 V V_MEMIO
CHANNEL J DECOUPLING
2 CH 2 CH
402 402 201 201
V_DRAM1P8
1 1 1 1 1 1 1 1 1 1
C451 C456 C463 C468 C481 C473 C491 C498 C505 C532
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1 1 1 1 1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
C1429 C1430 C1431 C1432 C1433 201 201 201 201 201 201 201 201 201 201
20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 201 201 201 201
1 1
A C1768
22 UF
C439
22 UF
1
C743
1
C744
1
C542
1
C568
1
C587
1
C606
1
C675
1
C626
1
C1339
1
C1344 A
20% 20% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
6.3 V 6.3 V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
603 603
201 201 201 201 201 201 201 201 201 201

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY: SPI FLASH

MAX40200 IDEAL DIODE PROVIDES BACKDRIVE PROTECTION FROM DEDIPROG
V_SOC1P8
D D
SPI_FLASH
U715 IC
MAX40200
VDD 1
4 NC OUT 5 1 R718 1 SPI_FLASH

0 OHM C713
5% 1 UF
3 EN GND 2
2 EMPTY 20%
6.3 V
402 2 X5R
SOC PIN TO SPI_FLASH MAPPING M1109119-001 201
SOC PIN SPI_FLASH
SOT23-5
QSS_N CS_N
QSIO3 HOLD_N IO3 = HOLD_N
QSIO2 WP_N IO2 = WP_N
QSIO1 DO IO1 = DO
QSIO0 DI
C QSCLK CLK C
29 V_SOC1P8_SPI_FLASH
1 SPI_FLASH 1 SPI_FLASH
C102 C103
1 UF 10 UF
SPI_FLASH_BASE 20% 20%
6.3 V 6.3 V
U1014 IC 2 X5R 2 X5R
201 402
SPI_FLASH SPI_FLASH SPI_FLASH
SPI_FLASH
VCC 8
1 R90 1 R86 1 R72
10 KOHM 10 KOHM 10 KOHM
1% 1% 1% 29 15 QSIO0 5 DI/IO0 D0/IO1 2 QSIO1 15 29
IN OUT
2 CH 2 CH 2 CH
402 402 402 29 15 QSCLK 6 CLK
IN
QSIO2 3
B 15
15
IN
IN QSIO3 7
IO2
IO3 GND 4 B
29 15 QSS_N 1 CS_N MPAD 9
IN
1 R88 1 R94 1 R103 M1070747-001
10 KOHM 10 KOHM 10 KOHM
1% 1% 1%
DFN9
2 EMPTY 2 EMPTY 2 EMPTY
402 402 402
J5
2X3HDR
29 V_SOC1P8_SPI_FLASH 1 2
29 15 QSS_N 3 4 QSCLK 15 29
IN QSIO1 5 6 QSIO0
IN
29 15 IN OUT 15 29
SM
HDR
DEBUG_HEADER
A MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY

A
ZZ209
I42
M1070747-001 IC U1014 FLASH MEMORY,FLASH,256MBIT,SM,WSON8,SERIAL,W/DUAL/QUAD SPI SPI_FLASH_WINBOND
ZZ210
I43
M1104466-001 IC U1014 FLASH MEMORY,FLASH,256MBIT,SM,8-WSON,SERIAL,MULTI I/O,DTR,1.8V SPI_FLASH_MACRONIX

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Q621M CONTROL SLAVE ADDRESS V_3P3STBY_HDMI U40 IC
ADDR0/ADDR1
FLOAT/FLOAT
7-BIT ADDRESS
0X5E
8-BIT ADDRESS
BC/BD
HDMI: VIDEO OUT NB7NQ621M
3 OF 3
POWER
C192 1 C703 1 C705 1 C707 1 C708 1 C709 3 VCC
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 9 6
16 AVAILABLE OPTIONS (7-BIT): 0X50 - 0X5E 201 201 201 201 201 201 VCC GND
V_3P3STBY_HDMI 10% 10% 10% 10% 10% 10% 16 15
16 V 16 V 16 V 16 V 16 V 16 V VCC GND
D SEE DATASHEET FOR MORE DETAILS X5R
2
X5R
2
X5R
2
X5R
2
X5R
2
X5R 22
28
VCC GND 25
35
D
VCC GND
STRAP CONFIG: HIGH FLOAT FLOAT FLOAT LOW 34 39
VCC MPAD
U40 IC 1 R183 1 R691 1 R693 1 R697 1 R699
0 OHM 0 OHM 0 OHM 0 OHM 0 OHM M1093444-002
NB7NQ621M 5% 5% 5% 5% 5% 1 1 1 C267 1 C475 1 C479 QFN39
C704 C706 0.01 UF 10 UF 22 UF
1 OF 3 2 CH 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 22 PF 1000 PF
10%
10%
201
20%
402
20%
603
R28 CONTROL 402 402 402 402 402 2%
50 V
50 V
EMPTY 2
EMPTY
16 V 2
X5R
6.3 V 2
EMPTY
6.3 V
57 52 44 38 32 SMBUS_CLK 1 2 HDMI_TX_RDRVR_SCL_CTL 13 OS/SCL I2C_EN 18 HDMI_TX_RDRVR_I2C_EN 2 2
IN HDMI_TX_RDRVR_SDA_CTL 12 31 HDMI_TX_RDRVR_ADDR0
NP0 201
0 OHM 5% FG/SDA EQ0/ADDRO 201
402 CH EQ1/ADDR1 17 HDMI_TX_RDRVR_ADDR1
R29 HDMI_TX_RDRVR_EN 36 EN MODE 37 HDMI_TX_RDRVR_MODE
57 52 44 38 32 SMBUS_DATA 1 2 LANE_SWAP 14 HDMI_TX_RDRVR_LANE_SWAP
BI 1 R31
1
C39
0 OHM 5% 10 KOHM 0.1 UF 1 R184 1 R692 1 R694 1 R698 1 R700
402 CH 1% 10%
16 V
M1093444-002 0 OHM 0 OHM 0 OHM 0 OHM 0 OHM
R30 2 CH EMPTY QFN39 5% 5% 5% 5% 5%
32 HDMI_TX_RDRVR_EN_R 1 2 402 2 201 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 CH
IN 402 402 402 402 402
0 OHM 5%
1 402 CH
FT15 FTP
U40 IC
C NB7NQ621M
2 OF 3 C
1
C52
2
HDMI
3 TMDS_TX_DP2 TMDS_TX_DP2_C 1 A_RXP A_TXP 30
IN 2 29
A_RXN A_TXN
0.1 UF 10% 4 27
C49 B_RXP B_TXP
3 TMDS_TX_DN2 16 V X5R 201 1 2 TMDS_TX_DN2_C 5 B_RXN B_TXN 26
IN 7 24
C_RXP C_TXP
0.1 UF 10% 8 23
C_RXN C_TXN
C57 16 V X5R 201 10 D_RXP D_TXP 21
3 TMDS_TX_DP1 1 2 TMDS_TX_DP1_C
IN 11 D_RXN D_TXN 20
0.1 UF 10%
1
C55 AUXP 33 NC
3 TMDS_TX_DN1 16 V X5R 201 1 2 TMDS_TX_DN1_C EG688 EG690 EG696 EG702
IN AUXN 32 NC
0.1 UF 10%
J2 CONN
C38 NC 38 HPD_SRC HPD_SNK 19 DIO DIO DIO DIO HDMI_19P_10MH
3 TMDS_TX_DP0 1 2 16 V X5R 201 TMDS_TX_DP0_C
IN SM SM SM SM TMDS_TX_DP2_CONN 1 TMDS_DATA2_DP
2
0.1 UF 10% M1093444-002 M1015860-001 M1015860-001 M1015860-001 M1015860-001 2 TMDS_DATA2_SHD
C36 QFN39 TMDS_TX_DN2_CONN 3 TMDS_DATA2_DN
TMDS_TX_DN0 16 V X5R 201 1 2 TMDS_TX_DN0_C
1
3 IN TMDS_TX_DP1_CONN 4 TMDS_DATA1_DP
0.1 UF 10%
EG41 EG689 EG695 EG701 5 TMDS_DATA1_SHD
C45 TMDS_TX_DN1_CONN 6 TMDS_DATA1_DN
3 TMDS_TX_CLKP 1 2 16 V X5R 201 TMDS_TX_CLKP_C
IN DIO DIO DIO DIO TMDS_TX_DP0_CONN 7 TMDS_DATA0_DP
B 0.1 UF 10% SM SM SM SM 8 TMDS_DATA0_SHD
B
2
C42 M1015860-001 M1015860-001 M1015860-001 M1015860-001 TMDS_TX_DN0_CONN 9 TMDS_DATA0_DN
3 TMDS_TX_CLKN 16 V X5R 201 1 2 TMDS_TX_CLKN_C HDMI_TX_RDRVR_HPD
IN TMDS_TX_CLKP_CONN 10 TMDS_CLK_DP MT1 20
0.1 UF 10% 11 TMDS_CLK_SHD MT2 21
16 V X5R 201 TMDS_TX_CLKN_CONN 12 TMDS_CLK_DN MT3 22
32 HDMI_CEC 13 CEC MT4 23
BI HDMIDPOUT_MODE_DET 14 24
32 OUT UTILITY MT5
HDMI_TX_SCL_CONN 15 SCL MT6 25
1
1 R178 V_3P3STBY_SOC V_5P0 EG24 HDMI_TX_SDA_CONN 16 SDA MT7 26
0 OHM X882235-001 17 DDC/CEC_GND MT8 27
5% V_5P0_HDMI_OUT 18 28
+5V_POWER MT9
2 CH DIO HDMI_TX_HPD_CONN 19 29
402 HOT_PLUG_DET MT10
402
2
1 1 M1087810-001 SM
C25 C478
4.7 UF 0.1 UF R19
V_3P3STBY_SOC 20% 10% 1 2
10 V 16 V
2 X5R 2 X5R 0 OHM 5%
402 201 402 CH
HDMI_TX_SCL_BUF R18
HDMI_TX_SDA_BUF 1 2
3 DP0_HPD 1 R50 1 R54
OUT 2 KOHM 2 KOHM 0 OHM 5%
1% 1% U21 IC 402 CH
R52
32 SB_DDC_CLK 1 2 2 CH 2 CH HDMIDP1_5F6
IN 402 402 C4 VDD_5V CEC E1 1 C14
0 OHM 5% C3 2.2 UF
402 CH VDD_IC 20%
R51 6.3 V
32 SB_DDC_DATA 1 2 HDMI_TX_SCL_R E5 R_SCL_IC SCL D2 2 X5R
BI HDMI_TX_SDA_R D5 C1 201
0 OHM 5% R_SDA_IC SDA
A 3 BI SOC_DDC_CLK
402 CH
C24 0.1 UF SOC_AUXP D4 AUX_P 5V_OUT A3 A
201 10% E4
X5R 16 V SCL_IC
HDMI 5V LOAD SWITCH: 5V, 250MA MAX TDC
R382
32 OUT DP0_HPD_SB 1 2 3 BI SOC_DDC_DATA C15
201
0.1 UF
10%
SOC_AUXN D3
E2
AUX_N DP PWR LOAD SWITCH: 3.3V, 500MA MAX TDC
0 OHM 5% X5R 16 V SDA_IC
402 CH HPD A1
B5 HPD_IC
32 HDMIDPOUT_MODE_SEL A2 SELECT_IC GND B1
IN HDMI_V_5P0_EN A5 C2
32 IN ENABLE_IC GND
1 R48 1 R148
FT6 FTP
1 10 KOHM 10 KOHM M1004155-003
1% 1% WLCSP18
2 CH 2 CH
402 402 PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HDMI: LOAD SWITCHES

D D
V_3P3STBY_SOC V_3P3STBY_HDMI
R612
1 2
0 OHM 5%
1 402 EMPTY 1 1 R20
C1218 C1219 10 KOHM
1 UF 1 UF 1%
20% 20%
6.3 V 6.3 V 2 CH
2 X5R 2 X5R 402
201 U82 IC 201
C 5
STMPS2151
1 C
IN OUT
FAULT_N 3 V_3P3STBY_HDMI_FLT_N 1
DB402
R600
50 44 38 32 VREG_1P1_ACTIVE_EN 1 2 V_3P3STBY_HDMI_EN 4 EN GND 2
IN
0 OHM 5%
402 CH X912985-001
SOT23-5
HDMI_LOAD_SWITCH_BASE
U82 IS MITIGATION FOR HDMI TMDS BACK-DRIVE CURRENT THROUGH Q621M RE-DRIVER

ZZ2
I39
X912985-001 IC U82 IC,SM,SOT23-5,STMPS2151STR,PWR SW,1CH,0.5A HDMI_LOAD_SWITCH_ST
ZZ8
I40
X862402-001 IC U82 IC,SM,SOT23-5,TPS2065DBVR,HI SIDE SW,1.5A HDMI_LOAD_SWITCH_TI
ZZ16
I41
X934019-001 IC U82 IC,SM,SOT23-5,AP2151D,PWR SW,1CH,0.5A,DIODES QUAL HDMI_LOAD_SWITCH_DIODES
B B
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: BOARD TO BOARD V_SOC1P8
V_3P3STBY_SOC V_SOC1P8
D D
DEBUG_HDT DEBUG_HDT DEBUG_HDT DEBUG_HDT DEBUG_HDT
1 R264 1 R269 1 R265 1 R271 1 R65 1 R116 1 R118 1 R121 1 R125
1.27 KOHM 1.27 KOHM 2 KOHM 2 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM
1% 1% 1% 1% 1% 1% 1% 1% 1%
2 EMPTY 2 EMPTY 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH
402 402 402 402 402 402 402 402 402
57 52 44 38 32 30 SMBUS_CLK 32 15 SB_SOC_CLK
BI SMBUS_DATA
BI SB_SOC_DATA
57 52 44 38 32 30 BI 32 15 BI
32 15 SOC_TDI
32 15 SOC_TMS
32 15 SOC_TCK
32 15 TRST_L
32 15 DBREQ_L
V_3P3STBY_SOC
J1
SM
M1094507-001 1 R168 J1
1X80RCPT_40MH 10 KOHM
3 OF 3
C 2 OF 3 1 OF 3 2
1%
CH MH1 81 C
402 MH2 82
50 44 38 31 VREG_1P1_ACTIVE_EN 41 40 TRST_L 15 32
OUT 42 39 CFX_PWR_FAULT_N
OUT MH3 83
IN 36 84
V_SOC1P8 1 R134 HDMI_CEC 43 38 CFX_INS_N MH4
30 BI IN 35 36 85
V_3P3STBY_SOC 100 KOHM 44 37 DBREQ_L MH5
OUT 15 CFX_INS_N: 86
1%
SB_DDC_DATA 45 36 NC 32 MH6
30 BI 100K PULLUP TO V_3P3STBY_SOC (OFFPAGE) 87
2 CH SB_DDC_CLK 46 35 ENET_REFCLK_N MH7
402 30 BI OUT 52 88
47 34 MH8
MH9 89
1 R27 1 R56 1 R108 1 R278 53 25MHZ_SB_CLK 48 33 SOC_TDO 15
10 KOHM 4.7 KOHM 100 KOHM 10 KOHM OUT 49 32 SOC_TDI
IN MH10 90
OUT 15 32 91
1% 1% 1% 1%
SMBUS_CLK 50 31 MH11
57 52 44 38 32 30 OUT 92
2 CH 2 CH 2 CH 2 CH SMBUS_DATA 51 30 PEX_ENET_SOC_TN_C MH12
402 402 402 402 57 52 44 38 32 30 BI OUT 2 93
52 29 PEX_ENET_SOC_TP_C MH13
OUT 2 94
VREG_PWRGPAB_CPUGFX_PWRGD 53 28 MH14
50 44 38 IN 95
57 51 SP_SMC_INT_N 54 27 SOC_TMS MH15
15 IN OUT 15 32 96
SOC_THERMTRIP_N 55 26 SOC_TCK MH16
15 IN OUT 15 32 97
56 25 MH17
MH18 98
32 15 SB_SOC_CLK 57 24 ENET_PEX_SS_100M_CLKN 52
OUT SB_SOC_DATA 58 23 ENET_PEX_SS_100M_CLKP
IN MH19 99
32 15 BI IN 52 100
59 22 MH20
MH21 101
15 SOC_RST_N 60 21 SOC_PWR_OK 15 38
OUT 61 20
OUT MH22 102
B 15 OUT X32K_X2_R 62 19 PEX_L0_SOC_SB_TN_C
IN 2 1 R277
MH23 103
104 B
63 18 PEX_L0_SOC_SB_TP_C MH24
IN 2 100 KOHM 105
V12P0_PWRGD 64 17 1%
MH25
51 OUT 106
VREG_3P3STBY_EN 65 16 PEX_L0_SB_SOC_TN_C MH26
49 OUT OUT 2 2 CH 107
66 15 PEX_L0_SB_SOC_TP_C 402 MH27
OUT 2 108
1 R276 1 R77 HDMI_V_5P0_EN 67 14 MH28
10 KOHM 100 KOHM V_BAT 30 OUT DP0_HPD_SB 68 13 PEX_L1_SOC_SB_TN_C MH29 109
30 IN IN 2 110
1% 1%
69 12 PEX_L1_SOC_SB_TP_C MH30
IN 2 111
2 CH 2 CH 70 11 MH31
402 402 MH32 112
71 10 PEX_L1_SB_SOC_TN_C 2
HDMIDPOUT_MODE_DET 72 9 PEX_L1_SB_SOC_TP_C
OUT MH33 113
30 IN OUT 2 114
HDMI_TX_RDRVR_EN_R 73 8 MH34
30 OUT 115
HDMIDPOUT_MODE_SEL 74 7 SB_PEX_SS_100M_CLKP MH35
30 OUT IN 52 116
75 6 SB_PEX_SS_100M_CLKN MH36
IN 52 117
VREG_PWRGPA_EN 76 5 MH37
50 36 OUT 118
VREG_PWRGPB_EN 77 4 PEX_SOC_ENET_TP_C V_5P0 MH38
51 OUT IN 2 119
VREG_PWRGPC_EN 78 3 PEX_SOC_ENET_TN_C MH39
51 OUT IN 2 120
79 2 MH40
1 R262 1 R267 1 R126
34 PCIE_RST_N 80 1
10 KOHM
1%
10 KOHM
1%
10 KOHM
1%
OUT
1 R261
2 CH 2 CH 2 CH 100 KOHM 1 RF 1 RF 1 RF 1 RF 1 RF
402 402 402 1% C37 C176 C644 C648 C650
15 PF 15 PF 15 PF 3 PF 3 PF
2 CH 5% 5% 5% +/-0.1PF +/-0.1PF
402 25 V 25 V 25 V 25 V 25 V
2 COG 2 COG 2 COG 2 COG 2 COG
201 201 201 201 201
A
RF FILTER CAPS
A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: POWER
D D
CRITICAL NOTE:
THE RF BOM STUFFING OPTION
SHOULD BE USED BY DEFAULT
NON-RF BOM CONFIGURATIONS WILL REQUIRE
INDUCTOR L10 TO BE PHYSICALLY SHORTED
J11
C 2X5RCPT_PWR_2MH V_12P0_SOC C
11 MH RF
L10
6 1 V_12P0_SOC_IN 1 2
7 2 15 NH IND
8 3 1 RF 1 RF 1 RF 1 RF 1 RF 1 RF 1 RF 1 RF 1 RF 1 RF 1 1 1 C252 1 C251
C1362 C1363 C1364 C121 C129 48 A SM C1365 C1366 C1367 C135 C137 C269 C249
9 4 1 MOHM 270 UF 0.1 UF 0.1 UF
15 PF 15 PF 15 PF 3 PF 3 PF 3 PF 3 PF 15 PF 15 PF 15 PF 10 UF 10% 10%
10 5 5% 5% 5% +/-0.1PF +/-0.1PF +/-0.1PF +/-0.1PF 5% 5% 5% 20% 20% 25 V 25 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 16 V 25 V EMPTY EMPTY
2 COG 2 COG 2 COG 2 COG 2 COG 2 COG 2 COG 2 COG 2 COG 2 COG 2 POLY 2 X5R 2
201
2
201
12 MH 201 201 201 201 201 201 201 201 201 201 SM 603
M1081256-001
SM
J11.11 CONNECTED TO V_12P0_IN TO AVOID CUTTING 12V PLANE
B B
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: M.2
D D
BOARD_LEVEL_SHIELD
SHLD3 SHIELD
SHLD_28P
14 SHLD SHLD 15
SSD POWER 13 SHLD SHLD 16
NOM.VOLTAGE: 3.3V 12 SHLD SHLD 17
V_3P3_GATED PEAK CURRENT: 2.5A 11 SHLD SHLD 18
J32 10 SHLD SHLD 19
PCIE_M2_M_RCPT_67P_2MH 9 SHLD SHLD 20
8 SHLD SHLD 21
2 1
7 SHLD SHLD 22
4 3
DEBUG 6 SHLD SHLD 23
DEBUG 6 5
1 1 1 1 1 1 1 D8 5 SHLD SHLD 24
C446 C1759 C450 C448 C1075 C1078 C449 R328 8 7
4 25
C 22 UF
20%
22 UF
20%
22 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 UF
20%
1 2 M2_LED_R 1 2 M2_LED 10
12
9
11
3
SHLD
SHLD
SHLD
SHLD 26 C
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 511 OHM 1% 2 27
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 402 CH 14 13 SHLD SHLD
GREEN 1 28
603 603 603 201 201 201 201
16 15 SHLD SHLD
SM
LED 18 17
20 19 M1097297-003
22 21 SM
24 23
26 25
28 27
30 29 PEX_L1_M2_SOC_TN 2
32 31 PEX_L1_M2_SOC_TP
OUT
OUT 2
34 33
36 35 PEX_L1_SOC_M2_TN_C 2
38 37 PEX_L1_SOC_M2_TP_C
IN
R283 1 R293 1 IN 2
10 KOHM 10 KOHM 40 39
1% 1% 42 41 PEX_L0_M2_SOC_TN 2
44 43 PEX_L0_M2_SOC_TP
OUT
CH 2 CH 2 OUT 2
402 402 46 45
48 47 PEX_L0_SOC_M2_TN_C 2
M2_PCIE_RESET_N 50 49 PEX_L0_SOC_M2_TP_C
IN
IN 2
52 M2_CLKREQ_N 52 51
OUT 54 53 M2_PEX_SS_100M_CLKN
B IN 52
3
U63
56
58
55
57
M2_PEX_SS_100M_CLKP
IN 52 B
FET
RST_G_C 1
SOT23-3
3
2
U66 68 67
R318 FET
32 PCIE_RST_N 1 2 1 70 69
IN SOT23-3 72 71
100 OHM 1% 1 74 73
2
402 CH C433 75
0.022 UF
10% 76 MH1
25 V 77
2 X5R MH2
201
R307 M1104823-001
RST_G 1 2 RST_G_R SM
100 OHM 1% STANDOFF
402 CH MTG5
1
SOME SSDS HAVE AN INTERNAL PULL-UP ON THEIR PCIE RESET INPUT.
ISOLATION OF SIGNAL PCIE_RST_N MAY BE NEEDED TO ISOLATE
SOUTHBRIDGE OUTPUT FROM SSD PULLUP
M1104828-001
TH
SSD MOUNTING HARDWARE
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN: SPDIF, CFEXPRESS

CFX_PERST_N DRIVEN BY GPIO FROM MP2926
NCP803 RESET SUPERVISOR FOOTPRINT LEFT IN DESIGN AS BACKUP
V_3P3_CFX
D D
V_3P3_CFX EMPTY
U132 1 R104
10 KOHM
NCP803 1%
3 VCC 2 CH
R154 402
RESET_N 2 CFX_PERST_MONITOR_N 1 2
1
C131 0 OHM 5%
0.1 UF 1 402 EMPTY PEX_L1_CFX_SOC_TP
10% GND 35 2 OUT
10 V V_3P3_CFX 35 2 PEX_L1_CFX_SOC_TN 35 CFX_PERST_N 35 2 PEX_L1_SOC_CFX_TN_C
2 EMPTY
OUT PEX_L1_SOC_CFX_TP_C PEX_L1_SOC_CFX_TP_C
201
M1095945-001 35 2 IN CFEXPRESS 35 2
SOT23-3 R209 35 2 PEX_L1_SOC_CFX_TN_C 52 35 CFX_CLKREQ_N
1 2
IN 2.5A EDC
1
1.55A TDC
1
100 KOHM 1% EG7 EG12
402 EMPTY EG2 EG6
R175 J3 CONN EMPTY EMPTY
CFX_PERST_GPIO_N 1 2 EMPTY EMPTY SM SM
2
44 IN CF_EXPRESS SM SM M1015860-001 M1015860-001
1 33
2
0 OHM 5% GND MH12
402 CH 2 PER1_N MH13 34 M1015860-001 M1015860-001
3 PER1_P MH14 35
R106 4 GND MH15 36
1 2 5 37 PEX_L1_CFX_SOC_TN
C V_3P3_CFX 0 OHM 5% 6
PET1_N
PET1_P
MH16
MH17 38
35 2
35 2 PEX_L1_CFX_SOC_TP C
402 CH CFX_RSV1 7 RESERVED MH18 39
8 40
1
RESERVED MH19
35 CFX_PERST_N 9 PERST_N MH20 41 EG8 EG13
10 +3.3V MH21 42
52 35 CFX_CLKREQ_N 11 CLKREQ_N MH22 43
1 1 1 1
OUT CFX_INS_N 12 44 EMPTY EMPTY
32 OUT INS_N MH23
C1444 C1758 C752 C750 36 CFX_PEX_SS_100M_CLKN 13 45 SM SM
2
22 UF 22 UF 10 UF 1 UF 52 35 IN REFCLK- MH24
CFX_PEX_SS_100M_CLKP 14 46 M1015860-001 M1015860-001
1
20% 20% 20% 20% 1 52 35 REFCLK+ MH25
6.3 V 6.3 V 6.3 V 6.3 V DB18 IN 15 47
2 X5R 2 X5R 2 X5R 2 X5R EG86 GND MH26
603 603 402 201 35 2 PEX_L0_CFX_SOC_TN 16 PER0_N MH27 48
OUT PEX_L0_CFX_SOC_TP 17 49
35 2 OUT PER0_P MH28
EMPTY 18 GND MH29 50 52 35 CFX_PEX_SS_100M_CLKN
SM PEX_L0_SOC_CFX_TN_C 19 51 CFX_PEX_SS_100M_CLKP
2
35 2 IN PET0_N MH30 52 35
35 2 PEX_L0_SOC_CFX_TP_C 20 PET0_P MH31 52
IN 21 53
1
M1015860-001 GND MH32
V_3P3_CFX 22 MH1 MH33 54 EG9 EG14
NOTE: 23 MH2 MH34 55
RF FILTER CAPS
THE FOLLOWING SIGNALS HAVE BEEN POLARITY 24 MH3 MH35 56
SWAPPED AT THE CFX CONNECTOR 25 MH4 MH36 57 EMPTY EMPTY
PINS 2,3: PEX_L1_CFX_SOC 26 58 SM SM
2
MH5 MH37
PINS 5,6: PEX_L1_SOC_CFX 27 MH6 MH38 59 M1015860-001 M1015860-001
B 1 RF
C651
1 RF
C652
1 RF
C653
1 RF
C654
1 RF
C655
28
29
MH7 MH39 60
61 B
MH8 MH40
15 PF 15 PF 15 PF 3 PF 3 PF 30 62
5% 5% 5% +/-0.1PF +/-0.1PF MH9 MH41
25 V 25 V 25 V 25 V 25 V 31 MH10 MH42 63 35 2 PEX_L0_SOC_CFX_TN_C
2 COG 2 COG 2 COG 2 COG 2 COG 32 64 PEX_L0_SOC_CFX_TP_C
201 201 201 201 201
MH11 MH43 35 2
1
M1097401-003
SM EG10 EG15
V_3P3_GATED EMPTY EMPTY

SM SM
2
M1015860-001 M1015860-001
V_3P3_GATED
1 1
C1268 C1269 PEX_L0_CFX_SOC_TN
1 UF 10 UF 35 2
1 R164
V_3P3_GATED 20% 20% 35 2 PEX_L0_CFX_SOC_TP
6.3 V 6.3 V
1 KOHM 2 X5R 2 X5R
1
1% 201 402
2 CH EG11 EG16
SPDIF_DETECT
402 1 R644 J7 CONN
3 OUT 100 KOHM
1%
SPDIF_4P_10MH EMPTY EMPTY
3 2 VCC MH 5
2 CH 6 SM SM
2
MH
Q166
402
R643 MH 7 M1015860-001 M1015860-001
FET 1 SPDIF_DETECT_N_R 1 2 SPDIF_DETECT_N 4 DETECT MH 8
SOT23-3 1 KOHM 1% MH 9
2 10
402 CH MH
A
1
A 1
C646
EG1
X882235-001
1
C647 3 IN SPDIF_OUT 3 VIN MH 11
12
0.1 UF 22 PF 1 MH
10% DIO 2% EG5 13
1 MH
10 V 402 50 V 1 14
2 X5R 2 NP0
X882235-001 C8 GND MH
EMPTY 22 PF
201 201
2
R165 402 2%
50 V M1087812-001
1 2 2 NP0 TH
2
0 OHM 5% 201
402 EMPTY
Q166 PROVIDES LOGIC INVERSION

SPDIF DETECT IS ACTIVE LOW PROJECT NAME PAGE CSA FAB VER
SOC REQUIRES ACTIVE HIGH MICROSOFT PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_3P3_GATED, V_3P3_CFX

COMPARATOR 1 OF 2 V_3P3STBY_SOC V_3P3_GATED
V_3P3_GATED LOAD SWITCH
D NOM.VOLTAGE: 3.3V
R292 D
PEAK CURRENT: 3.0A 1 2
0 OHM 5%
V_3P3_GATED POWERS M.2, CFEXPRESS, SPDIF, 805 EMPTY
1 1 1 R637
SOC VDD3, CLOCK GENERATOR 3.3V C434 C1371 10 KOHM
1 UF 22 UF
20% Q3 20%
1%
6.3 V NTTFS4C50N 6.3 V 2 CH
2 X5R 2 X5R 402
201
X889324-001 603
V_12P0_SOC DFN5
FET
FET_3P3GATED_BASE
3
V_12P0_SOC 1 5 2
C519 1 R213 1
0.1 UF
10% 34.8 KOHM
25 V 1% 1
1 R215 2 X5R C1369
201
2 CH 0.1 UF
75 KOHM 402 10%
4
1% 25 V
2
8
2 CH X5R
201
402 V_1P65_VREF 2
- V+
1 V_3P3_GATED_EN
1 R216
1 3 + V-
C 11.5 KOHM
1%
C34
1 UF
U34 C
LM393
4
2 CH 20%
402 6.3 V MSOP8
2 X5R MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY
201
X859331-001
ZZ20
I268
X889324-001 FET Q3 TRA-N-CNL,SM,WDFN8,30 V,44 AMP FET_3P3GATED_ONSEMI
ZZ23
I269
X875313-001 FET Q3 FET,N-CH,10MOHM,30V,37A,SM,WDFN8,TPN8R903,QUAL FET_3P3GATED_TOSHIBA
ZZ24
I270
M1128430-001 FET Q3 TRA-N-CNL,SM,WDFN8,8.8MOHM,30V,40A,BSZ088N03LSGATMA1,QUAL FET_3P3GATED_INFINEON
50 36 32 VREG_PWRGPA_EN
IN
COMPARATOR 2 OF 2
V_3P3_CFX LOAD SWITCH
NOM.VOLTAGE: 3.3V
EDC: 2.5A
TDC: 1.5A V_3P3_CFX_EN DRIVEN VIA GPIO FROM MP2926
COMPARATOR CIRCUIT LEFT IN AS BACKUP
B B
50 36 32 IN VREG_PWRGPA_EN V_3P3STBY_SOC
RT9742AGJ5F
1 R91 CURRENT LIMIT
49.9 KOHM MIN TYP MAX
1% 3A 3.3A 3.6A
2 CH 1 1
402 V_3P3STBY_SOC C642 C203 10 OHM OUTPUT DISCHARGE
VREG_PWRGPA_EN_DIV 10 UF 10 UF
V_3P3STBY_SOC 20% 20%
U6 IC V_3P3_CFX
6.3 V 6.3 V
1 R96 X859331-001 2 EMPTY 2 X5R
100 KOHM MSOP8 402 402
RT9742
1 R188 5 VIN VOUT 1
1 R85 1% LM393 34.8 KOHM
66.5 KOHM 2 CH U34 1%
3 CFX_PWR_FAULT_N 1
402 FLG_N OUT 32
C643
1%
5 2 CH
2 CH + 402 R172 10 UF
R85 AND R89 PROVIDES 7 V_3P3_CFX_EN_COMP 1 2 V_3P3_CFX_EN 4 EN GND 2 20%
402 6.3 V
100K PULLUP RESISTANCE CFX_INS_N_DIV 6 0 OHM 5% 2 X5R
- 1
FOR CFX_INS_N C202
402 EMPTY M1033328-001 402
1 R89 10000 PF SOT23-5
34.8 KOHM 1
C175 10%
1% 10000 PF 50 V LOAD_SWITCH_CFX_BASE
10% 2 X7R
2 CH
402
402 50 V
2 X7R
402
R174
44 V_3P3_CFX_EN_GPIO 1 2
IN
0 OHM 5%
35 32 CFX_INS_N 402 CH
IN
A GPA_EN CFX_INS_N GPA_EN_DIV CFX_INS_N_DIV ENABLE
1 R207
10 KOHM
A
1%
3.3V 0V 2.2V 1.13V 3.3V
2 CH MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY
3.3V 3.3V 2.2V 3.3V 0V 402
0V 0V 0V 1.13V 0V ZZ25
I266
M1033328-001 IC U6 IC-PWR,HIGH SIDE PWR SWITCH,2.7-6V,3A,RICHTEK LOAD_SWITCH_CFX_RICHTEK
0V 3.3V 0V 3.3V 0V ZZ26
I267
M1122901-001 IC U6 IC,SM,SOT25,LOAD SWITCH,SINGLE CHANNEL,AP22814,DIODES LOAD_SWITCH_CFX_DIODES

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: INPUT FILTERS

D D
C GFX/CPU INPUT FILTER MEMIO/MEMPHY/SOC INPUT CAPS C

V_12P0_SOC ST3
1 2
SHORT
V_12P0_SOC
L7
1 2 V_12P0_GFXCPU 39 40 41 42 43
OUT
220 NH EMPTY
32 A SM 1
C313 1
C312 1
C1313 1
C1312
1.1 MOHM 270 UF 270 UF 270 UF 270 UF
20% 20% 20% 20%
16 V 16 V 16 V 16 V 1 C35 1 C436
POLY POLY POLY POLY 180 UF 180 UF
2 SM 2 SM 2 SM 2 SM 20% 20%
16 V 16 V
EMPTY EMPTY
2 SM 2 SM
ST8
V_12P0_GFXCPU_SENSED 1 2
B 38 OUT
44 OUT V_12P0_MEMIOPHYSOC_SENSED 1
ST9
2 B
SHORT
SHORT
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_CPUCORE, V_GFXCORE CONTROLLER DB71

1
TP
1
FTP FT1005 R1003
1 2 SOC_GFXCORE_S_RTN
D V_3P3STBY_SOC 0 OHM 5%
IN 15
D
R564 402 CH
100 OHM
1%
1 R563 CH
2.2 OHM 402
1%
R231 2 CH 1
57 52 44 32 30 SMBUS_CLK 2 1 SMBUS_CLK_GFXCPU 603 C9
IN VREG_GFXCPU_VDD33 0.1 UF
0 OHM 5% 10%
R233
CH 402
2
16 V V_GFXCORE
1 EMPTY
57 52 44 32 30 SMBUS_DATA 2 1 SMBUS_DATA_GFXCPU C1009 402
BI 1 UF
0 OHM 5% 20%
CH 402 6.3 V
43 42 41 40 39 VREG_GFXCPU_SYNC 2 R225
OUT X5R
100 OHM
R252 201
1%
37 V_12P0_GFXCPU_SENSED 1 2 VINSEN_12P0_GFXCPU
IN VREG_GFXCPU_VDD18 CH
150 KOHM 1% 402 R1006
402 CH 1 R253 1 2 SOC_GFXCORE_S 15
10 KOHM 1
C395
IN
C391 0 OHM 5%
1% 0.01 UF U57 IC 1 DB1005 402 CH
10% 1 UF
2 CH TP
402 2
16 V MP2855 20%
6.3 V 1
X5R 18 SCL_P X5R
FTP FT1004
201
35
C 17 SDA_P
VDD33
VDD18 13
201
C
V_SOC1P8 19 STB
1 DB1007
12 VINSEN TP
1 FT1007
FTP R230
VORTN1 6 VREG_GFXCORE_S_RTN
1 2 SOC_CPUCORE_S_RTN 15
1 R243 1 R246 VOSEN1 5 VREG_GFXCORE_S IN
0 OHM 5%
1 MOHM 1 MOHM R565 CH
V_3P3STBY_SOC DB70 1
402
TP R228 1% 1% 100 OHM
15 SVT 1 2 2 EMPTY 2 EMPTY 1%
OUT 402 402
0 OHM 5% CH
DB69 402 CH 32 15 SOC_PWR_OK 23 PWROK/PVID3 402
TP 1 R219 IN 36 VREG_GFXCORE_CS1
SVD 1 2 CS1 IN 39 1
1 R120 15 BI SVT_R 21 37 VREG_GFXCORE_CS2
SVT CS2 IN 39 C133
10 KOHM 0 OHM 5% 38 VREG_GFXCORE_CS3 0.1 UF
DB68 1 CH CS3 IN 40 10%
1% TP R220 402
SVD_R 25 39 VREG_GFXCORE_CS4 V_CPUCORE
SVC 1 2 SVD/PVID1 CS4 IN 40 16 V
2 EMPTY 15 IN 40 VREG_GFXCORE_CS5 2 EMPTY
402 CS5 IN 41
402
0 OHM 5% SVC_R 24 1 VREG_GFXCORE_CS6
402 CH SVC/PVID2 CS6 IN 41
CS7 2 VREG_GFXCORE_CS7 42 1 R232
VREG_GFXCPU_MUX_ALT 16 3 VREG_CPUCORE_CS2
IN 100 OHM
MUX_ALT CS8 IN 43
1%
R249 CS9 4 VREG_CPUCORE_CS1 43
IN
B 57
44 32
51 50 OUT VREG_PWRGPAB_CPUGFX_PWRGD 1 2 VREG_GFXCPU_PG1 15 PG1
2 CH
402
1
R5
2 SOC_CPUCORE_S B
R248 0 OHM 5% IN 15
1 2 402 CH VREG_GFXCPU_PG2 14 PG2 DB1006 0 OHM 5%
1
R581 0 OHM 5% TP 402 CH
44
31 VREG_1P1_ACTIVE_EN 402 EMPTY VREG_GFXCPU_EN 20 EN 1 FT1006
32 IN FTP
50 0 OHM 5% V_SOC1P8
402 CH 1 R580
100 KOHM
1%
22 VDDIO VORTN2 8 VREG_CPUCORE_S_RTN
2 EMPTY 7 VREG_CPUCORE_S
402 VOSEN2
1
C1010 34 VREG_GFXCORE_PWM1_R
1 UF PWM1
20% PWM2 33 VREG_GFXCORE_PWM2_R
6.3 V 32 VREG_GFXCORE_PWM3_R
2 X5R PWM3
201 PWM4 31 VREG_GFXCORE_PWM4_R
30 VREG_GFXCORE_PWM5_R R217
PWM5 1 2 VREG_GFXCORE_PWM1
29 VREG_GFXCORE_PWM6_R OUT 39
41 PWM6
VREG_GFXCORE_TEMP 9 28 VREG_GFXCORE_PWM7_R 0 OHM 402 5% CH R176
39 IN TSENS1 PWM7 1 2 VREG_GFXCORE_PWM2
40 27 VREG_CPUCORE_PWM2_R OUT 39
42 PWM8
1 R3 1 1 38 VREG_GFX_IMON 10 26 VREG_CPUCORE_PWM1_R 0 OHM 402 5% CH R153
C2 FT1003 FTP IMON1 PWM9 1 2 VREG_GFXCORE_PWM3
24.9 KOHM OUT 40
0.1 UF 1
1%
10% DB1004 1 38 VREG_CPU_IMON 11 41 R160 0 OHM 402 5% CH
FT1002 FTP IMON2 MPAD 1 2 VREG_GFXCORE_PWM4
2 CH 16 V OUT 40
402 2 X5R 1
1 R122 DB1003 0 OHM 402 5% CH R212
201 M1080755-006 1 2 VREG_GFXCORE_PWM5 41
0 OHM 1 R245
C390 QFN41 OUT
5% 75 KOHM 0 OHM 402 5% CH R119
1000 PF DEBUG_HEADER 1 2 VREG_GFXCORE_PWM6
2 CH 1%
10% OUT 41
402 2 EMPTY 50 V J176 R7 0 OHM 402 5% CH
402 EMPTY 2X2HDR 1 2 VREG_GFXCORE_PWM7
OUT 42
A
402
38 VREG_CPU_IMON
VREG_GFX_IMON
1
3
2
4
0 OHM 402 5% CH
1
R218
2 VREG_CPUCORE_PWM2
A
38 OUT 43
R244
VREG_CPUCORE_TEMP 1 2 0 OHM 402 5% CH R110
43 IN VREG_CPUCORE_PWM1
0 OHM 5%
SM 1 2
OUT 43
402 EMPTY 1 R4 1 HDR 0 OHM 402 5% CH
24.9 KOHM C3
1% 0.1 UF
10% MP2855 RAIL ASSIGNMENTS
2 EMPTY 25 V MP2855 I2C ADDRESS
402 2 EMPTY RAIL 1: V_GFXCORE (POWER GROUP B)
402 7-BIT BASE R/W I2C ADDR 8-BIT HEX
RAIL 2: V_CPUCORE (POWER GROUP B)
WRITE 010 0000 0 0X20 0X40
READ 010 0000 1 0X20 0X41
PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_GFXCORE OUTPUT PHASE 1 & 2

V_3P3STBY_SOC
D D
V_GFXCORE
R480 C207
1 2 VREG_GFXCORE_VDD1 1 2
VID: 0.7V-1.1V BOOT: .8V
2.2 OHM 1%
1 402 CH 1 UF 10% TDC: 214A EDC: 288A FSW: 500KHZ
C206 6.3 V
1 UF X5R
10% 402
6.3 V
2 X5R
402
VR_GFXCPU_BASE
U41 IC
MP86965
VDD 25
BST 2 VREG_GFXCORE_BST1
43 42 41 40 39 37 V_12P0_GFXCPU
IN
27 VDRV SW 3 1
1 1 1 1
C145 C147 C211
1
C213
1
C210
1
C600
1
C214 C523 1 C530 SW 4 C209
1 UF V_GFXCORE
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 5 10%
10% 10% 10% 10% 10% 10% 10% 10% 10% VIN SW
20 6 6.3 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V VIN SW 2 X5R
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 21 7
402 402 402 805 805 805 805 805 805
VIN SW 402 L1009
29 VIN SW 30 VREG_GFXCORE_SW1 1 2
150 NH IND CAPACITOR_SP_BASE
AGND 26 50 A SM C1330
1 R138 1
C 38 IN VREG_GFXCORE_PWM1 22 PWM PGND 8
9
0.66 MOHM 220 OHM
330 UF
20% C
PGND INDUCTOR_CORE_BASE 1% 2 V
43 42 41 40 39 38 VREG_GFXCPU_SYNC 23 SYNC PGND 10 2 CH POLY
IN 11 402 2 SM
PGND
PGND 12
PGND 13
R23 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
38 VREG_GFXCORE_CS1 1 2 VREG_GFXCORE_CSFAULT1_R 24 CS PGND 17
OUT VREG_GFXCORE_TEMP 1 2 VREG_GFXCORE_TEMP1 19 18
42 41 40 39 38 OUT VTEMP PGND
28 FAULT_N PGND 31
R1026
0 OHM 5%
402 CH
M1109161-001
LGA31
V_3P3STBY_SOC
R543 C310
VREG_GFXCORE_VDD2 1 2
B 1
C304
2.2 OHM
402
1%
CH 1 UF 10%
6.3 V B
1 UF VR_GFXCPU_BASE X5R
10% 402
6.3 V U52 IC
2 X5R
402
MP86965
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU
IN
27 VDRV SW 3
1 1 1 1
C143 C146 C314
1
C322
1
C882
1
C321
1
C876 C493 1 C527 SW 4 C311 V_GFXCORE
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 5 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% VIN SW 10%
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 20 VIN SW 6 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 21 7 X5R
402 402 402 805 805 805 805 805 805
VIN SW 402
L1010
AGND 26 50 A SM 1
C1331
VREG_GFXCORE_PWM2 22 8 0.66 MOHM 330 UF
38 IN PWM PGND 20%
PGND 9 INDUCTOR_CORE_BASE 2 V
43 42 41 40 39 38 VREG_GFXCPU_SYNC 23 SYNC PGND 10 POLY
IN 11 2 SM
PGND
PGND 12
PGND 13
R24 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
28 31
A R1027
FAULT_N PGND
A
0 OHM 5% M1109161-001
402 CH
LGA31
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY
ZZ14
I134
M1067777-001 IC U41,U52,U46,U48,U1000,U1001,U4,U55,U1013 IC-PWR, DC/DC CONV, MP86955 VR_GFXCPU_MP86955 ZZ28
I137
X913175-001 IC C1330,C1331,C1332,C1333,C1257,C1256 PANASONIC 330UF SP QUAL CAPACITOR_SP_PANASONIC
ZZ15
I135
M1109161-001 IC U41,U52,U46,U48,U1000,U1001,U4,U55,U1013 IC-PWR, DC/DC CONV, MP86965 VR_GFXCPU_MP86965 ZZ29
I138
X913175-001 IC C1263,C1260 PANASONIC 330UF SP QUAL CAPACITOR_SP_PANASONIC
M1070340-001 IC C1330,C1331,C1332,C1333,C1257,C1256 MURATA 330UF SP QUAL CAPACITOR_SP_MURATA
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY ZZ31
I140
M1070340-001 IC C1263,C1260 MURATA 330UF SP QUAL CAPACITOR_SP_MURATA

ZZ1
I131
M1116117-001 IC L1009,L1010,L1004,L1005,L1007,L1008,L6,L1006,L1011 INDUCTOR_CORE_EATON ZZ32
I142
ZZ3
I130
M1117589-001 IC L1009,L1010,L1004,L1005,L1007,L1008,L6,L1006,L1011 INDUCTOR_CORE_SUNLORD
ZZ27
I136
M1126117-001 IC L1009,L1010,L1004,L1005,L1007,L1008,L6,L1006,L1011 INDUCTOR_CORE_ITG
PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D V_3P3STBY_SOC
D
R504 C230
2.2 OHM 1%
CH 1 UF 10%
402 6.3 V
C226
10% 402
6.3 V U46 IC
X5R MP86965
402
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU
IN 27 3
VDRV SW
SW 4 C231 V_GFXCORE
1 1 1 1 1 1 1 1 1 1 UF
C162 C164 C233 C662 C659 C245 C246 C575 C580 1 VIN SW 5
10%
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 20 6
10% 10% 10% 10% 10% 10% 10% 10% 10% VIN SW 6.3 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 21 VIN SW 7 X5R L1004
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 29 30 VREG_GFXCORE_SW3 402 1 2
402 402 402 805 805 805 805 805 805
VIN SW
AGND 26 50 A SM 1
C1332
38 IN PWM PGND
C VREG_GFXCPU_SYNC 23
PGND 9
10
INDUCTOR_CORE_BASE
20%
2 V C
43 42 41 40 39 38 IN SYNC PGND POLY
11 2 SM
PGND
PGND 12
PGND 13
R59 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
28 FAULT_N PGND 31
R1007
0 OHM 5%
402 CH M1109161-001
LGA31
V_3P3STBY_SOC
B B
R521 C265
2.2 OHM 1%
CH 1 UF 10%
402 6.3 V
C259
10% 402
6.3 V U48 IC
X5R MP86965
402
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU
IN
27 VDRV SW 3
1 1 1 1 V_GFXCORE
C163 C165 C271
1
C283
1
C775
1
C282
1
C765 C577 1 C579 1 VIN
SW
SW
4
5
C266
1 UF
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10%
10% 10% 10% 10% 10% 10% 10% 10% 10% 20 VIN SW 6 6.3 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 21 7 X5R
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R VIN SW 402
L1005
402 402 402 805 805 805 805 805 805 29 VIN SW 30 VREG_GFXCORE_SW4 1 2
AGND 26 50 A SM 1
C1333
38 IN PWM PGND 20%
IN 11 2 SM
PGND
PGND 12
PGND 13
R55 14
PGND
0 OHM 5% 15
A 402 CH
PGND
PGND 16 A
28 FAULT_N PGND 31
R1008
0 OHM 5%
402 CH
M1109161-001
LGA31

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

V_3P3STBY_SOC
D D
R1018 C1244
2.2 OHM 1%
CH 1 UF 10%
402 6.3 V
C1239
10% 402
6.3 V U1000 IC
X5R MP86965
402
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU BST 2 VREG_GFXCORE_BST5

IN
27 VDRV SW 3
1 1 1 1
C153 C156 C1232
1
C1233
1
C1235
1
C1237
1
C1240 C571 1 C573 SW 4 C1246 V_GFXCORE
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 5 1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% VIN SW 10%
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 20 VIN SW 6 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 21 7 X5R
402 402 402 805 805 805 805 805 805
VIN SW 402
L1007
CAPACITOR_SP_BASE
150 NH IND C1257
AGND 26 50 A SM 1
330 UF
38 VREG_GFXCORE_PWM5 22 PWM PGND 8 0.66 MOHM 20%
IN 9 2 V
PGND INDUCTOR_CORE_BASE
VREG_GFXCPU_SYNC 23 10 POLY
C 43 42 41 40 39 38 IN SYNC PGND
PGND 11
2 SM
C
PGND 12
PGND 13
R47 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
28 FAULT_N PGND 31
R1012
0 OHM 5% M1109161-001
402 CH LGA31
V_3P3STBY_SOC
C1242 R1019 C1245

1 UF VREG_GFXCORE_VDD6 1 2
B 10%
6.3 V 2.2 OHM 1% B
X5R CH 1 UF 10%
402 6.3 V
402
VR_GFXCPU_BASE X5R
402
U1001 IC
MP86965
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU
IN
27 VDRV SW 3
1 1 1 1
C154 C157 C1243
1
C1234
1
C1236
1
C1238
1
C1241 C572 1 C574 1 VIN
SW
SW
4
5
C1247
1 UF V_GFXCORE
10% 10% 10% 10% 10% 10% 10% 10% 10% 20 VIN SW 6 6.3 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 21 7 X5R
L1008
AGND 26 50 A SM 1
C1256
38 IN PWM PGND 20%
IN 11 2 SM
PGND
PGND 12
PGND 13
R44 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
A
42 41 40 39 38 OUT 28
VTEMP
FAULT_N
PGND
PGND 31 A
R1013
0 OHM 5%
402 CH M1109161-001
LGA31

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_GFXCORE OUTPUT PHASE 7

V_3P3STBY_SOC
D D
1
C86 R82 C99
1 UF 1 2 VREG_GFXCORE_VDD7 1 2
10%
6.3 V 2.2 OHM 1%
2 X5R CH 1 UF 10%
402 6.3 V
402
VR_GFXCPU_BASE X5R
402
U4 IC
MP86965
VDD 25
43 41 40 39 37 V_12P0_GFXCPU
IN
27 VDRV SW 3
1
1
1
C72
1
C73
1
C76
1
C80
1
C81
1
C82
1
C83 C592 1 C595 1 VIN
SW
SW
4
5
C100
1 UF V_GFXCORE
10% 10% 10% 10% 10% 10% 10% 10% 10% 20 VIN SW 6 6.3 V
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 21 7 2 X5R
L6
150 NH IND
26
C 38 IN VREG_GFXCORE_PWM7 22 PWM
AGND
PGND 8
50 A SM
0.66 MOHM C
PGND 9 INDUCTOR_CORE_BASE
43 41 40 39 38 VREG_GFXCPU_SYNC 23 SYNC PGND 10
IN 11
PGND
PGND 12
PGND 13
R66 PGND 14
0 OHM 5% 15
CH
PGND
402 16
PGND
41 40 39 38 OUT VTEMP PGND
28 FAULT_N PGND 31
R9
0 OHM 5%
402 CH M1109161-001
LGA31
B B
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_CPUCORE OUTPUT

D V_3P3STBY_SOC D
R556
VREG_CPUCORE_VDD1
2.2 OHM 1%
1 402 CH 1 V_CPUCORE
C349 C353
1 UF 1 UF VID: 0.7V-1.23V BOOT: .8V
10% VR_GFXCPU_BASE 10%
6.3 V 6.3 V TDC: 36A EDC: 97A FSW: 700KHZ
2 X5R U55 IC 2 X5R
402 402
MP86965
VDD 25
43 42 41 40 39 37 V_12P0_GFXCPU
IN BST 2 VREG_CPUCORE_BST1
C367
1 1 1 1 1 1 1 1 1 27 VDRV SW 3 1 UF
C183 C185 C369 C373 C992 C989 C372 C583 C590 SW 4 10%
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 6.3 V
10% 10% 10% 10% 10% 10% 10% 10% 10% 1 VIN SW 5 X5R V_CPUCORE
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 20 6 402
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R VIN SW
402 402 402 805 805 805 805 805 805 21 VIN SW 7 L1006
29 VIN SW 30 VREG_CPUCORE_SW1 1 2
AGND 26 50 A SM 1 R186 1
C1263
VREG_CPUCORE_PWM1 22 8 0.66 MOHM 1 KOHM 330 UF
38 IN PWM PGND 1% 20%
9
C 43 42 41 40 39 38 IN VREG_GFXCPU_SYNC 23 SYNC
PGND
PGND 10
INDUCTOR_CORE_BASE
2 CH
402
2 V
POLY C
11 2 SM
PGND
PGND 12
PGND 13
R255 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
38 VREG_CPUCORE_CS1 1 2 VREG_CPUCORE_CSFAULT1_R 24 CS PGND 17
OUT VREG_CPUCORE_TEMP 1 2 VREG_CPUCORE_TEMP1 19 18
43 38 OUT VTEMP PGND
28 FAULT_N PGND 31
R1009
0 OHM 5%
402 CH M1109161-001
LGA31
V_3P3STBY_SOC
R1087
VREG_CPUCORE_VDD2
2.2 OHM 1%
1 402 CH 1
C1350 C1353
1 UF 1 UF
10% 10%
B 2
6.3 V
X5R 2
6.3 V
X5R B
402 402
VR_GFXCPU_BASE
U1013 IC
MP86965
43 42 41 40 39 37 V_12P0_GFXCPU VDD 25
IN
BST 2 VREG_CPUCORE_BST2
1 1 1 1
C182 C184 C1352
1
C1347
1
C1348
1
C1349
1
C1351 C584 1 C591 C1354
1 UF 1 UF 1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 27 3
10% 10% 10% 10% 10% 10% 10% 10% 10% VDRV SW 1 UF V_CPUCORE
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V SW 4 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 1 5 6.3 V
402 402 402 805 805 805 805 805 805
VIN SW X5R
20 VIN SW 6 402
21 VIN SW 7 L1011
29 VIN SW 30 VREG_CPUCORE_SW2 1 2
AGND 26 50 A SM 1
C1260
VREG_CPUCORE_PWM2 22 8 0.66 MOHM 330 UF
38 IN PWM PGND 20%
IN 11 2 SM
PGND
PGND 12
PGND 13
R247 14
PGND
0 OHM 5% 15
CH
PGND
402 16
PGND
38 VREG_CPUCORE_CS2 1 2 VREG_CPUCORE_CSFAULT2_R 24 CS PGND 17
OUT VREG_CPUCORE_TEMP 1 2 VREG_CPUCORE_TEMP2 19 18
43 38 OUT VTEMP PGND
A R1083
28 FAULT_N PGND 31 A
0 OHM 5%
402 CH M1109161-001
LGA31

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_MEMIO, V_MEMPHY, V_SOC CONTROLLER

D V_3P3STBY_SOC V_MEMPHY/V_MEMIO PSTATES D
PVID1 PVID2
V_MEMPHY V_MEMIO 3P3V_SLEEP_S3_N 3P3V_FORCE_PWR
1 R171 0.85 1.35 0 0
2.2 OHM
1% 0.85 1.25 0 1
R143 0.75 1.25 1 0
SMBUS_CLK 2 1 SMBUS_CLK_MEMIOPHYSOC 2 CH
57 52 38 32 30 IN 603 0.70 1.25 1 1
0 OHM 5% VREG_MEMIOPHYSOC_VDD33
CH 402
R133
57 52 38 32 30 SMBUS_DATA 2 1 SMBUS_DATA_MEMIOPHYSOC 1 MP2926 RAIL ASSIGNMENTS
BI C178
0 OHM 5% 1 UF
CH 402 20% RAIL 1: V_MEMPHY (POWER GROUP B)
6.3 V
2 X5R RAIL 2: V_MEMIO (POWER GROUP A)
R132 201
37 V_12P0_MEMIOPHYSOC_SENSED 1 2 VINSEN_12P0_MEMIOPHYSOC RAIL 3: V_SOC (POWER GROUP B)
IN
150 KOHM 1%
402 CH 1 R140 1
10 KOHM C169 44 VREG_MEMIOPHYSOC_VDD18
0.01 UF
1%
10% MP2926 I2C ADDRESS
2 CH 16 V 1
402 2 X5R 7-BIT BASE R/W I2C ADDR 8-BIT HEX
201
C18
1 UF WRITE 010 0001 0 0X23 0X46
U480 IC 20%
6.3 V
C MP2926 2 X5R READ 010 0001 1 0X23 0X47
19
1 of 2
35
201 C
SCL_P VDD33
18 SDA_P VDD18 17
13 VINSEN
R71 STB 20 VREG_MEMIOPHYSOC_SYNC 46 47 48
VREG_1P1_ACTIVE_EN 1 2 VREG_MEMIOPHYSOC_EN 22
OUT
50 38 32 31 IN EN
0 OHM 5% VREG_MEMIOPHYSOC_PG 25 PGOOD
402 CH 1 R130 V_3P3_GATED
100 KOHM 37 VREG_MEMPHY_CS1
1%
CS1 IN 46
CS2 38 VREG_MEMPHY_CS2 46
2 EMPTY 39 VREG_MEMIO_CS2
IN
402 CS3 IN 47
1 R144 1 R660 1 R667 CS4 40 VREG_MEMIO_CS1 47
10 KOHM 10 KOHM 10 KOHM 1 VREG_SOC_CS2
IN
CS5 IN 48
R131 1% 1% 1%
2 VREG_SOC_CS1
VREG_PWRGPAB_CPUGFX_PWRGD 1 2 CS6 IN 48
57 51 50 38 32 OUT 2 EMPTY 2 EMPTY 2 EMPTY
0 OHM 5% 402 402 402
DB141 1 VREG_MEMIOPHYSOC_PVID0 32 PVID0
PG PULLED UP EXTERNALLY 402 CH
VREG_MEMIOPHYSOC_PVID1 31 PVID1
15 3P3V_SLEEP_S3_N 1 2 VREG_MEMIOPHYSOC_PVID2 30 PVID2
IN
1 R170 1 R669 1 R671 R179
R210 34 VREG_MEMPHY_PWM1_R 1 2 VREG_MEMPHY_PWM1
10 KOHM 10 KOHM 10 KOHM PWM1 OUT 46
0 OHM 5% 33 VREG_MEMPHY_PWM2_R
1% 1% 1% PWM2 0 OHM 402 5% CH R180
B 15 IN 3P3V_FORCE_PWR 402 CH 1 2 2 CH
402
2 CH
402
2 CH
402
PWM3 29
28
VREG_MEMIO_PWM2_R
VREG_MEMIO_PWM1_R
1 2 VREG_MEMPHY_PWM2
OUT 46
B
PWM4 0 OHM 402 5% CH R181
R659 27 VREG_SOC_PWM2_R 1 2 VREG_MEMIO_PWM2
PWM5 OUT 47
0 OHM 5% 26 VREG_SOC_PWM1_R
PWM6 0 OHM 402 5% CH R182
402 CH 1 2 VREG_MEMIO_PWM1
OUT 47
DB661 1 VREG_MEMIOPHYSOC_GPIO1 36 GPIO1 R682 0 OHM 402 5% CH
35 CFX_PERST_GPIO_N 21 GPIO2 1 2 VREG_SOC_PWM2 48
OUT V_3P3_CFX_EN_GPIO 23
OUT
36 OUT GPIO3 0 OHM 402 5% CH R684
53 52 SOC_REFCLK_N 24 GPIO4 1 2 VREG_SOC_PWM1 48
OUT OUT
0 OHM 402 5% CH
GPIO STRAPPING IS ON SINK PAGES
46 VREG_MEMPHY_TEMP 9 TSENS1 44
IMON1 14 VREG_MEMPHY_IMON 1
IN VREG_MEMIO_TEMP 10 44 15 VREG_MEMIO_IMON 1
DB685
47 IN TSENS2 IMON2 DB677 1
48 VREG_SOC_TEMP 11 TSENS3 IMON3 16 1 R681 1 FTP FT686
IN 1 R672 1
1
FTP FT679 75 KOHM C683
C674 1% 1000 PF
75 KOHM 10%
1000 PF
12 41 1%
10% 2 EMPTY 50 V
ADDR MPAD 402 2 EMPTY
1 R70 1 1 R513 1 1 R658 1 2 EMPTY 50 V
C127 C656 C666 402 2 EMPTY 402
24.9 KOHM 24.9 KOHM 24.9 KOHM
1% 0.1 UF 1% 0.1 UF 1% 0.1 UF M1094197-004 402
2 CH
10%
16 V 2 CH
10%
16 V 2 CH
10%
16 V
QFN41
402 2 X5R 402 2 X5R 402 2 X5R
201 201 201
J177 44 VREG_SOC_IMON 1
DB678
2X3HDR 1
44 VREG_SOC_IMON 1 2 1 R673 1 FTP FT680
VREG_MEMIO_IMON 3 4 75 KOHM C676
R668 44 1000 PF
A 44 VREG_MEMIOPHYSOC_VDD18 1 2 VREG_MEMIOPHYSOC_ADDR 44 VREG_MEMPHY_IMON 5 6
2
1%
EMPTY
10%
50 V
A
3.32 KOHM 1% 402 2 EMPTY
402 EMPTY 1 R670 SM 402
10 KOHM
1%
HDR
DEBUG_HEADER
2 CH
402

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_MEMIO, V_MEMPHY, V_SOC SENSE

ST4 V_MEMPHY
ST_W5
SHORT
VREG_MEMPHY_ALT_S 1 2
D D
1 R53
100 OHM
1%
2 CH
402 R69
1 2 SOC_MEMPHY_S 15
IN
0 OHM 5%
402 CH
1 DB1013
1 TP
FTP FT12
1
C285
0.1 UF
10%
16 V 1
MP2926 RAIL ASSIGNMENTS 2 EMPTY DB23
TP
402
RAIL 1: V_MEMPHY (POWER GROUP B) 1
FTP FT10
RAIL 2: V_MEMIO (POWER GROUP A) R63
1 2 SOC_MEMPHY_S_RTN 15
RAIL 3: V_SOC (POWER GROUP B) IN
0 OHM 5%
402 CH
1 R49
100 OHM ST2
1% ST_W5
2 CH SHORT
C 402 VREG_MEMPHY_ALT_S_RTN 1 2 ST5 V_MEMIO C
ST_W5
SHORT
VREG_MEMIO_ALT_S 1 2
1 R189
0 OHM
U480 IC 5%
MP2926 2 CH
R196
2 of 2 402 1 2 SOC_MEMIO_S 15
VOSEN1 3 VREG_MEMPHY_S IN
4 VREG_MEMPHY_S_RTN 1 DB25 0 OHM 5%
VORTN1 402 EMPTY
1 TP
FTP FT17
1
VOSEN2 5 VREG_MEMIO_S C299
6 VREG_MEMIO_S_RTN 0.1 UF
VORTN2 10%
16 V
2 EMPTY
402 1 DB24
TP
VOSEN3 7 VREG_SOC_S 1
FTP FT16 R191
VORTN3 8 VREG_SOC_S_RTN
1 2 SOC_MEMIO_S_RTN 15
IN
B M1094197-004 1
0 OHM
R190 0 OHM 5%
402 EMPTY B
QFN41 5%
ST10
ST_W5
2 CH
402 SHORT
VREG_MEMIO_ALT_S_RTN 1 2
ST1 V_SOC
ST_W5
SHORT
VREG_SOC_ALT_S 1 2
1 R506
100 OHM
1%
2 CH
R512
402 1 2 SOC_VSOC_S
IN 15
1 0 OHM 5%
TP DB508 402 CH
1
FTP FT510
1
C504
0.1 UF
10%
16 V
2 EMPTY
402
1
TP DB507
1
FTP FT509 R511
1 2 SOC_VSOC_S_RTN 15
IN
1 R505 0 OHM 5%
A 100 OHM
1%
402 CH
ST0 A
ST_W5
2 CH
402 SHORT
VREG_SOC_ALT_S_RTN 1 2

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_MEMPHY OUTPUT

D V_MEMPHY
D
V_3P3STBY_SOC PVID: 0.85V, 0.8V, 0.75V, 0.7V
TDC: 28A EDC: 36A FSW: 700KHZ
1
C41
1 UF
V_12P0_SOC VR_MEMSOC_BASE 20%
6.3 V
U31 IC 2 X5R
201
MP86910C
VCC 21
1 1 1 1 1 1 1
C1315 C507 C1320 C506 C60 C59 C54 BST 2 VREG_MEMPHY_BST2
10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 UF C46
10% 10% 10% 10% 20% 20% 10% 1 1 UF
25 V 25 V 25 V 25 V 25 V 25 V 16 V 1 VIN_1 SW_1 3 V_MEMPHY
2 2 2 2 2 2 2 20%
X5R X5R X5R X5R X5R X5R X5R 16 VIN_2 SW_2 4 10 V
805 805 805 805 603 603 402
23 VIN_3 SW_3 5 X5R L2
24 VREG_MEMPHY_SW2 2 201 1 2
SW_4
CAPACITOR_SP_BASE
150 NH IND C1259
44 VREG_MEMPHY_PWM2 17 PWM AGND 20 50 A SM 1 R304 1 1 1 1 1 1
IN 6 0.66 MOHM 1 KOHM C43 C44 C51 C664 C665 330 UF
PGND 22 UF 22 UF 22 UF 22 UF 22 UF 20%
VREG_MEMIOPHYSOC_SYNC 1 2 VREG_MEMPHY_SYNC2 18 7 INDUCTOR_CORE_BASE 1%
20% 20% 20% 20% 20% 2 V
48 47 46 44 IN SYNC PGND
C R62
PGND 8
9
2 CH
402 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R 2
6.3 V
X5R
POLY
2 SM
C
PGND 603 603 603 603 603
0 OHM 5% 10
PGND
402 CH R237 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
44 VREG_MEMPHY_CS2 1 2 VREG_MEMPHY_CS2_R 19 CS PGND 14
OUT 15
PGND
46 44 VREG_MEMPHY_TEMP 1 2 VREG_MEMPHY_TEMP2 22 VTEMP/FLT PGND 25
OUT
R1079
0 OHM 5%
M1079610-001
402 CH
LGA25
V_3P3STBY_SOC
1
C424
1 UF
B V_12P0_SOC
20%
6.3 V B
2 X5R
VR_MEMSOC_BASE 201
U62 IC
MP86910C
VCC 21
1 1 1 1 1 1 1
C430 C1074 C1071 C429 C97 C1316 C427
10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 UF
BST 2 VREG_MEMPHY_BST1
10% 10% 10% 10% 20% 20% 10%
25 V 25 V 25 V 25 V 25 V 25 V 16 V 1
C425
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 1 3 1 UF
805 805 805 805 603 603 402
VIN_1 SW_1 20% V_MEMPHY
16 VIN_2 SW_2 4 10 V
23 VIN_3 SW_3 5 X5R L16
2 201 1 2
SW_4 24 VREG_MEMPHY_SW1
CAPACITOR_SP_BASE
150 NH IND C1258
44 VREG_MEMPHY_PWM1 17 PWM AGND 20 50 A SM 1 1 1 1 1 1
IN 6 0.66 MOHM
C20 C16 C17 C50 C56 330 UF
PGND 22 UF 22 UF 22 UF 22 UF 22 UF 20%
48 47 46 44 VREG_MEMIOPHYSOC_SYNC 1 2 VREG_MEMPHY_SYNC1 18 SYNC PGND 7 INDUCTOR_CORE_BASE 20% 20% 20% 20% 20% 2 V
IN 8 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V POLY
PGND 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 SM
R266 9
PGND 603 603 603 603 603
0 OHM 5% 10
PGND
402 CH R234 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
44 VREG_MEMPHY_CS1 1 2 VREG_MEMPHY_CS1_R 19 CS PGND 14
OUT 15
PGND
46 44 VREG_MEMPHY_TEMP 1 2 VREG_MEMPHY_TEMP1 22 VTEMP/FLT PGND 25
OUT
R1080
M1079610-001
A 0 OHM
402
5%
CH
LGA25 A

ZZ41
I174
X913175-001 IC C1259,C1258,C1261,C1262,C110,C109 PANASONIC 330UF SP QUAL CAPACITOR_SP_PANASONIC
ZZ42
I175
M1070340-001 IC C1259,C1258,C1261,C1262,C110,C109 MURATA 330UF SP QUAL CAPACITOR_SP_MURATA
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY
M1116117-001 IC L2,L16,L3,L15,L0,L1002 INDUCTOR_CORE_EATON M1079610-001 IC U31,U62,U32,U60,U0,U59 IC-PWR, DC/DC CONV, MP86910C VR_MEMSOC_MP86910C
ZZ6 ZZ18
I170 I172
M1117589-001 IC L2,L16,L3,L15,L0,L1002 INDUCTOR_CORE_SUNLORD M1126229-001 IC U31,U62,U32,U60,U0,U59 IC-PWR, DC/DC CONV, MP86912C VR_MEMSOC_MP86912C
ZZ10 ZZ19
I171 I173
M1126117-001 IC L2,L16,L3,L15,L0,L1002 INDUCTOR_CORE_ITG

ZZ43
I176

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_MEMIO OUTPUT

V_MEMIO
D PVID: 1.35V, 1.25V

D
TDC: --A EDC: --A FSW: 700KHZ
V_3P3STBY_SOC
1
C69
1 UF
20%
V_12P0_SOC VR_MEMSOC_BASE
2
6.3 V
X5R
U32 IC 201
MP86910C
VCC 21
1 1 1 1 1 1 1 VREG_MEMIO_BST1
C508 C509 C1253 C1249 C61 C66 C75 BST 2 C77
10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 1 UF
10% 10% 10% 10% 20% 20% 10%
1 3
1 1 UF V_MEMIO
25 V 25 V 25 V 25 V 25 V 25 V 16 V VIN_1 SW_1 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 16 4
805 805 805 805 603 603 402
VIN_2 SW_2 10 V
23 VIN_3 SW_3 5 X5R L3
24 VREG_MEMIO_SW1 2 201 1 2
SW_4
CAPACITOR_SP_BASE
150 NH IND C1261
44 VREG_MEMIO_PWM1 17 PWM AGND 20 50 A SM 1 R79 1
IN 6 0.66 MOHM 1 KOHM
330 UF
PGND 20%
C 48 47 46 44 IN VREG_MEMIOPHYSOC_SYNC 1 2 VREG_MEMIO_SYNC1 18 SYNC PGND 7
8
INDUCTOR_CORE_BASE
1%
2 CH
2 V
POLY C
PGND 402 2 SM
R73 9
PGND
0 OHM 5% 10
PGND
402 CH R240 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
44 VREG_MEMIO_CS1 1 2 VREG_MEMIO_CS1_R 19 CS PGND 14
OUT 15
PGND
47 44 VREG_MEMIO_TEMP 1 2 VREG_MEMIO_TEMP1 22 VTEMP/FLT PGND 25
OUT
R1025
0 OHM 5%
M1079610-001
402 CH
LGA25
B V_3P3STBY_SOC B
1
C423
1 UF
20%
2
6.3 V
X5R
U60 IC 201
MP86910C
VCC 21
1 1 1 1 1 1 1
C1248 C1250 C428 C426 C1069 C1072 C421 BST 2 VREG_MEMIO_BST2
10% 10% 10% 10% 20% 20% 10% 1 1 UF
V_MEMIO
25 V 25 V 25 V 25 V 25 V 25 V 16 V 1 VIN_1 SW_1 3 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 16 4 10 V
805 805 805 805 603 603 402
VIN_2 SW_2 X5R
23 VIN_3 SW_3 5 201 L15
24 VREG_MEMIO_SW2 2 1 2
SW_4
44 VREG_MEMIO_PWM2 17 PWM AGND 20 50 A SM C1262
IN 6 0.66 MOHM
1
330 UF
PGND 20%
48 47 46 44 VREG_MEMIOPHYSOC_SYNC 1 2 VREG_MEMIO_SYNC2 18 SYNC PGND 7 INDUCTOR_CORE_BASE
IN 8
2 V
PGND POLY
R270 9 2 SM
PGND
0 OHM 5% 10
PGND
402 CH R241 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
VREG_MEMIO_CS2 1 2 VREG_MEMIO_CS2_R 19 14
A
44 OUT CS PGND
PGND 15 A
47 44 VREG_MEMIO_TEMP 1 2 VREG_MEMIO_TEMP2 22 VTEMP/FLT PGND 25
OUT
R1024
0 OHM 5%
M1079610-001
402 CH
LGA25

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_SOC OUTPUT

D D
V_3P3STBY_SOC
V_SOC
VID RANGE: 0.7V-1.1V BOOT VOLTAGE: 1.00V
1
C118 TDC: 31A EDC: 58A FSW: 700KHZ
1 UF
20%
6.3 V
2 X5R
201
U0 IC
MP86910C
VCC 21
1 1 1 1 1 1 1
C12 C116 C115 C10 C7 C6 C23 BST 2 VREG_SOC_BST1
10% 10% 10% 10% 20% 20% 10% 1 1 UF
25 V 25 V 25 V 25 V 25 V 25 V 16 V 1 VIN_1 SW_1 3 20% V_SOC
805 805 805 805 603 603 402
VIN_2 SW_2 X5R
23 VIN_3 SW_3 5 201 L0
24 VREG_SOC_SW1 2 1 2
C SW_4
150 NH IND
CAPACITOR_SP_BASE
C110 C
44 VREG_SOC_PWM1 17 PWM AGND 20 50 A SM 1 1 1 1 1 1
IN 6 0.66 MOHM
C669 C603 C621 C631 C663 330 UF
PGND 22 UF 22 UF 22 UF 22 UF 22 UF 20%
48 47 46 44 VREG_MEMIOPHYSOC_SYNC 1 2 VREG_SOC_SYNC1 18 SYNC PGND 7 INDUCTOR_CORE_BASE 20% 20% 20% 20% 20% 2 V
IN 8 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V POLY
PGND 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 SM
R0 9
PGND 603 603 603 603 603
0 OHM 5% 10
PGND
R256 402 CH 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
44 VREG_SOC_CS1 1 2 VREG_SOC_CS1_R 19 CS PGND 14
OUT 15
PGND
48 44 VREG_SOC_TEMP 1 2 VREG_SOC_TEMP1 22 VTEMP/FLT PGND 25
OUT
R10
0 OHM 5%
M1079610-001
402 CH
LGA25
V_3P3STBY_SOC
B 1
C1296 B
1 UF
20%
6.3 V
2 X5R
201
U59 IC
MP86910C
VCC 21
1 1 1 1 1 1 1
C1292 C1293 C1289 C1291 C1286 C1287 C1295 BST 2 VREG_SOC_BST2
10% 10% 10% 10% 20% 20% 10% 1 1 UF
25 V 25 V 25 V 25 V 25 V 25 V 16 V 1 VIN_1 SW_1 3 20% V_SOC
805 805 805 805 603 603 402
VIN_2 SW_2 X5R
23 VIN_3 SW_3 5 201 L1002
24 VREG_SOC_SW2 2 1 2
SW_4
CAPACITOR_SP_BASE
150 NH IND C109
44 VREG_SOC_PWM2 17 PWM AGND 20 50 A SM 1 R197 1 1 1 1 1 1
IN 6 0.66 MOHM 1 KOHM C668 C602 C615 C627 C661 330 UF
PGND 1% 22 UF 22 UF 22 UF 22 UF 22 UF 20%
48 47 46 44 VREG_MEMIOPHYSOC_SYNC 1 2 VREG_SOC_SYNC2 18 SYNC PGND 7 INDUCTOR_CORE_BASE 20% 20% 20% 20% 20% 2 V
IN 8 2 CH 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V POLY
PGND 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 SM
R139 9
PGND 603 603 603 603 603
0 OHM 5% 10
PGND
R257 402 CH 11
PGND
0 OHM 5% 12
CH
PGND
402 13
PGND
44 VREG_SOC_CS2 1 2 VREG_SOC_CS2_R 19 CS PGND 14
OUT 15
A 48 44 OUT VREG_SOC_TEMP 1 2 VREG_SOC_TEMP2 22 VTEMP/FLT
PGND
PGND 25 A
R137
0 OHM 5%
M1079610-001
402 CH
LGA25
PROJECT NAME PAGE CSA FAB VER

PAGE
Toledo SoC 48/59 48/59 E Retail
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_3P3STBY_SOC
D V_3P3STBY_SOC D
NOM. VOLTAGE: 3.32
V_12P0_SOC 49 VREG_3P3STBY_SOC_VCC
DB66 1
TP 1 C1
1 UF
20%
1 1 1 1 1 1 1 1 1 10 V
C334 C327 C914 C329 C913 C633 C634 C635 C636 2 X5R
0.1 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 10 UF 201
10% 10% 10% 10% 10% 10% 10% 10% 10%
25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V VREG_3P3STBY_SOC_BST
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R U3 IC
201 805 805 805 805 805 805 805 805
TPS568230 1
VCC 17 C916 V_3P3STBY_SOC
0.1 UF
10%
BST 1 25 V INDUCTOR_3P3STBY_BASE
49 VREG_3P3STBY_SOC_VCC 2 1
2 VIN X5R L5 DB57
402 1
3 VIN SW 6 VREG_3P3STBY_SOC_SW 2 1 FTP FT62
4 VIN SW 19 IND 1.5 UH
5 VIN SW 20 SM 12 A 2 1 1 1 1 1 1 1
1 R76 1 R57 ST26 C303 C284 C275 C268 C290 C289 C300
7.5 MOHM 1 UF 22 UF 22 UF 22 UF 22 UF 22 UF 22 UF
C 20 KOHM
1%
330 KOHM
1%
10
NC 16
NC FB 14 VREG_3P3STBY_SOC_FB SHORT 20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V
20%
6.3 V C
NC 1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
2 EMPTY 2 CH 13
402 402 AGND R192 201 603 603 603 603 603 603
1 VREG_3P3STBY_SOC_PG_R 9 PGOOD PGND 7 1 2 VREG_3P3STBY_SOC_S
DB9
VREG_3P3STBY_SOC_MODE 15 MODE PGND 8 182 KOHM 1% 1
R201 FTP FT68
VREG_3P3STBY_SOC_EN_R 12 EN PGND 18 R193 1 402 CH 1
1 R74 40.2 KOHM 1 2 DB61
15 KOHM VREG_3P3STBY_SOC_SS 11 SS MPAD 21 C350
1% 1 2 0 OHM 5%
1%
CH 2 402 EMPTY
2 CH 1 M1081794-001
C0 402 330 PF 5% VENABLE
402 0.022 UF QFN21 50 V
10% X7R
50 V 402
2 EMPTY
V_12P0_SOC 402
1 R294
100 KOHM
1%
1 2 EMPTY
FT72 FTP
402 MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY
1
R351 DB67 M1082612-001 IND L5 IND,PMC,1.5UH,20%,7.5MOHM,11A,SM,ISAT=12A,ITG INDUCTOR_3P3STBY_ITG
B
ZZ36
I95
VREG_3P3STBY_EN 1 2 M1123611-001 IND L5 IND,PWW,1.5UH,20%,7.5MOHM,11A,SM,12A ISAT,SUNLORD INDUCTOR_3P3STBY_SUNLORD

32 IN
0 OHM 5%
ZZ37
I94
ZZ38
I96
M1125599-001 IND L5 IND,PWW,1.5UH,20%,7.5MOHM,11A,SM,2PIN,12A ISAT,CHILISIN INDUCTOR_3P3STBY_CHILISIN B
402 CH
1 R295
47.5 KOHM
1%
2 EMPTY
402
A A

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U914 IS A LINEAR REGULATOR STUFFING OPTION
VREGS: V_SOC1P8, V_DRAM1P8 IN CASE VDD18/SOC1P8 IS SENSITIVE TO RIPPLE VOLTAGE

THIS IS NOT EXPECTED TO BE NEEDED AS AMD HAS SINCE
PROVIDED A RIPPLE VOLTAGE REQUIREMENT OF <30MV PK-PK
R688
D 57 51 50 44 38 32 OUT VREG_PWRGPAB_CPUGFX_PWRGD 1 2 VREG_1P8LDO_PG D
0 OHM 5%
402 EMPTY
V_SOC1P8: 1.80V
R263
TDC: 1.8 EDC: 2.8 FSW: 1.5MHZ 50 36 32 VREG_PWRGPA_EN 1 2 VREG_1P8LDO_EN
IN
0 OHM 5%
402 EMPTY ST12
1 2
SHORT
U714 EMPTY V_SOC1P8
V_3P3STBY_SOC TPS7A84A
U681 IC 14 EN PG 4
RT5788B L682
2 VIN LX 3 VREG_SOC1P8_SW 1 2 VREG_SOC1P8_OUT 15 IN OUT 1
1 UH IND
16 IN OUT 19
1 1 FB 7 8.7 A SM 17 IN OUT 20 1 1 R729 1 1
C679 C680 1 1 1 1 1 C728 31.6 KOHM C721 C716
22 UF 22 UF 26 MOHM C695 C711 C730 C723 C682 10000 PF 22 UF 22 UF
22 UF 22 UF 22 UF 22 UF 22 UF 1%
20% 20% VREG_SOC1P8_PG 1 PGOOD VOUT 5 13 NR/SS SNS 2 NC 10% 20% 20%
6.3 V 6.3 V 20% 20% 20% 20% 20% 50 V 2 EMPTY 6.3 V 6.3 V
2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 2 EMPTY 402 2 EMPTY 2 EMPTY
6 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 12 3
603 603 AGND 603 603 603 603 603
BIAS FB 402 603 603
8 EN PGND 4
1 1 R259 NC 5 50mV R732
C720
C M1111231-001 10000 PF
69.8 KOHM
1%
NC 6 100mV 1 2 VREG_SOC1P8_SNS
IN 4 50
C
SOT23-8 10% NC 7 200mV 31.6 KOHM 1%
50 V 2 EMPTY
2 EMPTY 402 NC 9 400mV GND 8 402 EMPTY
51
44 R725 402 NC 10 800mV GND 18
VREG_1P8LDO_FB_MID
32 OUT VREG_PWRGPAB_CPUGFX_PWRGD 1 2 NC 11 1P6V MPAD 21 OUT
38
50 0 OHM 5% 1 R730
57 402 CH VREG_1P8LDO_NR M1110730-001 0 OHM
R722
QFN21 5%
50 2 EMPTY
32 VREG_PWRGPA_EN 1 2 VREG_SOC1P8_EN V_3P3STBY_SOC
36 IN R258 R728 402
0 OHM 5% VREG_SOC1P8_FB 1 2 1 2 VREG_SOC1P8_SNS VREG_1P8LDO_FB
CH IN 4 50 IN
402
0 OHM 5% 69.8 KOHM 1%
R724 402 CH 402 CH 1
38 1 R726 C729
31 VREG_1P1_ACTIVE_EN 1 2 1
32 IN 34.8 KOHM
1%
VR_FIXED VR_FIXED 10000 PF
10%
C731 1 R731
44 0 OHM 5% 10 UF 24.9 KOHM
50 V 20%
402 EMPTY 2 CH 2 EMPTY 1%
402 6.3 V
402 2 EMPTY 2 EMPTY
402 402
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY FOR FIXED OPERATION @1.8V STUFF R732, R730 AS SHOWN
10NF NR/SS SETS RISE ~1MS
X850496-001 CH R728 (RES-FXD,SM,45.3 KOHM,1%,1/16W,0402, PREFERRED) VR_MM FOR M&M STUFF R732= 6.65KOHM, EMPTY R730
B
ZZ720
SNS CONNECTS AN INTERNAL DIVIDER FOR USE WITH ANYOUT VOLTAGE SETTING
I390
X800967-001 EMPTY R258 (RES_FXD,SM,0 OHM,5%,1/16W,0402,JUMPER,PREFERRED) VR_MM VREG_SOC1P8_FB_MID

ZZ721
I389
OUT FOR EXTERNAL DIVIDER, SNS IS LEFT DISCONNECTED B

V_DRAM1P8: 1.80V IN
TDC: ??A EDC 3A FSW 1 5MHZ
L1661: MWSA0518 USED FOR LOWER HEIGHT

V_3P3STBY_SOC V_DRAM1P8
U7 IC INDUCTOR_DRAM1P8_BASE
RT5788B L1661
2 VIN LX 3 VREG_DRAM1P8_SW 1 2 1
DB137
0.47 UH IND 1
1 1 1 FB 7 12 A SM 1 1 1 1 FTP FT138
C13 C19 C21 9 MOHM C22 C26 C27 C29
22 UF 22 UF 1 UF 22 UF 22 UF 22 UF 22 UF
20% 20% 20% VREG_DRAM1P8_PG 1 PGOOD VOUT 5 20% 20% 20% 20%
6.3 V 6.3 V 6.3 V 1 R823 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 69.8 KOHM 2 X5R 2 X5R 2 X5R 2 X5R
603 603 201 AGND 6 1% 603 603 603 603
8 EN PGND 4 2 EMPTY
402
M1111231-001 VR_FIXED
R1659 SOT23-8 1
57 51 50 44 38 32 VREG_PWRGPAB_CPUGFX_PWRGD 1 2 C31 R481 ST482
OUT 100 PF
5%
1 2 VREG_DRAM1P8_SNS 1 2
0 OHM 5%
CH 25 V
402 2 EMPTY 69.8 KOHM 1% SHORT
R811 201 VR_FIXED 402 CH
A 50 36 32 IN VREG_PWRGPA_EN 1 2 VREG_DRAM1P8_EN 1 R586
0 OHM
A
0 OHM 5%
5%
402 CH VREG_DRAM1P8_FB_MID
2 CH OUT
402
ZZ39
I427
M1120971-001 IND L1661 IND,PMC,0.47UH,9MOHM,10.5A,SM,SUNLORD INDUCTOR_DRAM1P8_SUNLORD
VREG_DRAM1P8_FB
IN
ZZ40
I428
M1126490-001 IND L1661 IND,PMC,0.47UH,8.57MOHM,10.5A,SM,CHILISIN INDUCTOR_DRAM1P8_CHILISIN
1 R825
34.8 KOHM
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY 1%
ZZ7
I394
X850496-001 CH R481 (RES-FXD,SM,45.3 KOHM,1%,1/16W,0402, PREFERRED) VR_MM 2 CH
ZZ12
I393
X800967-001 EMPTY R586 (RES_FXD,SM,0 OHM,5%,1/16W,0402,JUMPER,PREFERRED) VR_MM 402

PAGE
1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS: V_SOCPHY, V_FUSE

D D
V_SOCPHY: 0.75V
TDC: 1.4A EDC: 3.7A FSW: 2.2MHZ
V_3P3STBY_SOC
1 1 1
C483 C497 C490
1 UF 10 UF 10 UF
20% 20% 20%
6.3 V 6.3 V 6.3 V INDUCTOR_SOCPHY_BASE V_SOCPHY
2 X5R 2 X5R 2 X5R
201 402 402
L1
U129 IC 0.47 UH IND
7.8 A SM 1
FTP FT14
0.01 OHM
TPS62826 1
DB7
6 VIN SW 5 VREG_SOCPHY_SW 1 2
57 R136
44
32 VREG_PWRGPAB_CPUGFX_PWRGD 1 2 VREG_SOCPHY_PG 2 PG FB 3
38 OUT 1 1 1 1
50 R135 0 OHM 5% C503 C123 C124 C126
32 VREG_PWRGPB_EN 1 2 402 CH VREG_SOCPHY_EN 1 EN GND 4
IN 22 UF
20%
22 UF
20%
22 UF
20%
22 UF
20%
0 OHM 5%
6.3 V 6.3 V 6.3 V 6.3 V
C 402 CH M1087390-001 2 X5R 2 X5R 2 EMPTY 2 EMPTY
DFN6 603 603 603 603 C
2
C40
PWRGPAB_CPUGFX_PWRGD TIED TO 3P3_MAIN WITH 10K 1 2 1 SHORT
FTP FT13
VREG_PWRGPB_EN PULLED DOWN TO GND WITH 10K 1 ST13
120 PF 5% DB5
50 V
1
NPO
402
VR_FIXED
MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY R68
ZZ34
I435
M1102580-001 IND L1 IND,0.47UH,30%,0.010OHM,5.2A,SM,SUNLORD QUAL INDUCTOR_SOCPHY_SUNLORD VREG_SOCPHY_FB 1 2 VREG_SOCPHY_S
ZZ35
I436
M1125677-001 IND L1 IND,0.47UH,20%,.0095OHM,6.5A,SM,CYNTEC QUAL INDUCTOR_SOCPHY_CYNTEC 24.9 KOHM 1%
402 CH
1 R64
100 KOHM
1%
2 CH
402
IN
OUT
B B
V_FUSE: 0.83V
TDC: 100MA
V_3P3_GATED V_3P3STBY_SOC
V_FUSE OUTPUT ADJUSTED TO .72V FOR A0

REVERT R596 TO 45.3KOHM FOR B0 V_FUSE
1 R324 C447 U68 IC
1 UF
100 KOHM
1%
20%
10 V
AP7331_ADJ
1 IN OUT 5 1
2 CH X5R DB74
201
402
ADJ 4 1 R596 1 C1084 1 1 R597
34 KOHM 0.022 UF C441 49.9 OHM
1% 10% 4.7 UF 1%
VREG_PWRGPC_EN_R 3 EN GND 2 25 V 20%
2 CH EMPTY 10 V 2 CH
2 402 2 2 X5R 402
402
D9 1 R599 M1012324-001 VREG_VFUSE_ADJ 402
20 KOHM
1%
SOT23-5
SOD123 1 R595
2 2 EMPTY 42.2 KOHM
1 MBR130L
32 VREG_PWRGPC_EN D7 402 1%
IN 2 CH
402
A
SOD123
1 MBR130L
A
32 V12P0_PWRGD
IN

PAGE
1.03
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8 7 6 5 4 3 2 1
CLOCK: PCIE 100MHZ SS

9FGL0651 SMBUS ADDRESS
1101 010 R/W HEX
V_3P3_GATED
D WRITE 1101 010
READ 1101 010
0 0XD4
1 0XD5 V_SOC1P8 D
R33
V_1P8_SS_CLK_SEL 1 2 1 1
C105 C95
0 OHM 5% V_3P3_GATED V_3P3_SS_CLK 1 UF 0.1 UF
402 EMPTY 20% 10%
6.3 V 16 V
X5R 2 2 X5R
FB0 R87 FB3 201 201
1 2 1 2 1 2
1000 OHM BEAD 0 OHM 5% 1000 OHM BEAD
200 MA 402 402 CH 200 MA 402
V_3P3_SS_CLK
V_1P8_SS_CLK
1 OHM
U17 IC
1 OHM POWER SUBJECT TO REVIEW
52
6V41466
1 1 1 1 1 1 12 VDDIO VDD3.3 16
R624 1 C64 C65 C67 C70 C74 C79
10 KOHM 10 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 17 VDDIO VDD3.3 31
1% 1 R15 20% 10% 10% 10% 10% 10% 27 VDDIO 1 1 1 1 1 1 1
10 KOHM 6.3 V 16 V 16 V 16 V 16 V 16 V 32 26 C84 C85 C87 C550 C88 C89 C90
CH 2 1% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R VDDIO VDDA3.3 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 10 UF
SPREAD SPECTRUM TURNED ON 402 402 201 201 201 201 201 39 VDDIO 10% 10% 10% 10% 10% 10% 20%
2 CH 11 16 V 16 V 16 V 16 V 16 V 16 V 6.3 V
402 VDDDIG3.3 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
PLACE 0.1UF CAPS CLOSE TO EACH POWER PINS 201 201 201 201 201 201 402
SS_LEVEL_SS_CLK 1 VSS_EN_TRI VDDREF3.3 5
C R14 1
10 KOHM ADR_SEL_SS_CLK 6 VSADR/REF3.3 VDDXTAL3.3 4
PLACE 0.1UF CAPS CLOSE TO EACH POWER PIN
C
1%
EMPTY 2 1 R16
402 10 KOHM 52 34 M2_CLKREQ_N 13 VOE0_N DIF0 14 M2_PEX_SS_100M_CLKP 34
1%
IN 15 M2_PEX_SS_100M_CLKN
OUT
DIF0_N OUT 34
2 EMPTY
402 52 35 CFX_CLKREQ_N 21 VOE1_N DIF1 18 CFX_PEX_SS_100M_CLKP 35
IN 19 CFX_PEX_SS_100M_CLKN
OUT
DIF1_N OUT 35
R21
53 52 44 SOC_REFCLK_N 1 2 52 SPARE_CLKREQ_N 24 VOE2_N DIF2 22 SPARE_PEX_SS_100M_CLKP 1
IN DB1
0 OHM 402 EMPTY DIF2_N 23 SPARE_PEX_SS_100M_CLKN 1
DB2 85 OHM DIFF OUTPUTS
R22
52 32 ENET_REFCLK_N 1 2 52 SB_CLKREQ_N 30 VOE3_N DIF3 28 SB_PEX_SS_100M_CLKP 32
IN 29 SB_PEX_SS_100M_CLKN
OUT
0 OHM 402 EMPTY DIF3_N OUT 32
R25
1 2 52 ENET_CLKREQ_N 35 VOE4_N DIF4 33 ENET_PEX_SS_100M_CLKP 32
34 ENET_PEX_SS_100M_CLKN
OUT
0 OHM 402 DIF4_N OUT 32
R83
1 2 52 SOC_CLKREQ_N 38 VOE5_N DIF5 36 SOC_PEX_SS_100M_CLKP 2
37 SOC_PEX_SS_100M_CLKN
OUT
DEFAULT CONFIG DOES NOT REQ SMBUS 0 OHM 402 DIF5_N OUT 2
DEBUG 52 SS_CKPWRGD_PD_N 40 CKPWRGD_PD_N
R152
B 53 52 SMBUS_CLK_BUFFERED 1 2 52 SS_SCLK 9 SCLK_3.3 NC 7
20 B
0 OHM 402 CH 52 SS_SDATA
NC
R155 10 SDATA_3.3 NC 25
53 52 SMBUS_DATA_BUFFERED 1 2
0 OHM 402 CH 53 25MHZ_REF 2 X1_25 GNDDIG 8
IN 1 SS_XTAL_X2 3 41
DEBUG DB0 X2 EPAD V_3P3_SS_CLK
STUFF R109 AND R113 TO PREVENT SCLK/SDATA FROM FLOATING
M1092049-001
QFN41
RETAIL RETAIL
1 R109 1 R113 1 R35 1 R37 1 R39 1 R42 1 R166
10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 1 KOHM
1% 1% 1% 1 R36 1% 1 R38 1% 1 R41 1% 1 R43 1%
2 CH 2 CH 2 CH 2 CH 10 KOHM 2 EMPTY 2 CH 2 CH
10 KOHM 1% 10 KOHM 10 KOHM
402 402 402 1% 402 402 1% 402 1% 402
2 EMPTY
V_3P3STBY_SOC V_3P3_SS_CLK 52 SS_SCLK 2 CH 402 2 EMPTY 2 CH
402 402 402
52 SS_SDATA
M2_CLKREQ_N
1 R13
1 1 52 34 10 KOHM
C58 C128 1%
1 UF 1 UF CFX_CLKREQ_N
20% 20% 52 35 2 CH
10 V 10 V 402
2 X5R U12 IC 2 X5R SPARE_CLKREQ_N
52
201 201
DEBUG TCA9803 DEBUG
1 VCCA VCCB 8 52 SB_CLKREQ_N
A 57 44 38 32 30 BI SMBUS_DATA
SMBUS_CLK
3
2
SDAA SDAB 6
7
SMBUS_DATA_BUFFERED
SMBUS_CLK_BUFFERED
BI 52 53 52 ENET_CLKREQ_N A
57 44 38 32 30 IN SCLA SCLB OUT 52 53
R2 52 SOC_CLKREQ_N
52 V_3P3_SS_CLK 1 2 SS_SMBUS_EN 5 EN GND 4
0 OHM 5% 52 32 ENET_REFCLK_N
402 CH 1 R11 M1090212-001
10 KOHM SS_CKPWRGD_PD_N
DEBUG
1%
VSSOP 52
DEBUG
2 EMPTY SOC_REFCLK_N
EN: 450K INTERNAL PU TO VCCA 402 53 52 44
V_3P3_SS_CLK HAS 10K PD TO GND
R166 = 1K TO ACCOUNT FOR ~60KOHM COMBINED INPUT IMPEDANCE OF CLOCK GENS
I2C BUFFER PREVENTS LEAKAGE PATH FROM SMBUS PULLUPS TO V_3P3_GATED THROUGH CLOCK GENERATORS
PAGE
1.03
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CLOCK: PCIE 100MHZ NS

9FGL04 SMBUS ADDRESS
1101 000 R/W HEX
D WRITE 1101 000
READ 1101 000
0 0XD0
1 0XD1
D
V_3P3_GATED
53 V_3P3_NS_CLK
1 1
R45 1 C106 C104
1 UF 0.1 UF
10 KOHM
1 R46
20% 10% FB4
1% 6.3 V 16 V 1 2
10 KOHM 2 X5R 2 X5R
EMPTY 2 1%
402 201 201 1000 OHM BEAD
2 EMPTY 200 MA 402
402 U2 IC 1 OHM
SS_LEVEL_NS_CLK 6V41462 53 V_3P3_NS_CLK
VDD3.3 11
R81 1 20
C 10 KOHM
1%
ADR_SEL_NS_CLK VDD3.3
1
C91
1
C92
1
C93
1
C94
1
C96 C
0.1 UF 0.1 UF 0.1 UF 0.1 UF 10 UF
SPREAD SPECTRUM CH 2 1 R124 16 10% 10% 10% 10% 20%
402 VDDA3.3
TURNED OFF 10 KOHM 16 V 16 V 16 V 16 V 6.3 V
1% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
201 201 201 201 402
2 CH 7
402 VDDDIG3.3
23 PLACE 0.1UF CAPS CLOSE TO EACH POWER PIN
25MHZ REFERENCE FOR VSS_EN_TRI
SPREAD CLOCK GENERATOR R17
52 25MHZ_REF 1 2 4 VSADR/REF3.3 VDDXTAL3.3 3
OUT
49.9 OHM 1%
402 CH R61
1 2 53 SOC_NS_CLKREQ_N 12 VOE0_N DIF0 13 SOC_PEX_NS_100M_CLKP 2
14 SOC_PEX_NS_100M_CLKN
OUT
0 OHM 402 DIF0_N OUT 2
52 44 IN SOC_REFCLK_N 1
R58
2 53 SPARE_NS_CLKREQ_N 19 VOE1_N DIF1 17 SPARE_PEX_NS_100M_CLKP 1
DB26
85 OHM DIFF OUTPUTS
0 OHM 402 DIF1_N 18 SPARE_PEX_NS_100M_CLKN 1
DB27
EMPTY
DEFAULT CONFIG DOES NOT REQ SMBUS NS_CKPWRGD_PD_N 22
53 CKPWRGD_PD_N
R156 DEBUG GNDA 15
52 SMBUS_CLK_BUFFERED 1 2 53 NS_SCLK 8 SCLK_3.3 GND1 10
IN 21
0 OHM 402 CH GND2
B 53 NS_SDATA 9 SDATA_3.3 GNDREF 5
24 B
R157 GNDXTAL
52 SMBUS_DATA_BUFFERED 1 2 1 XIN/CLKIN_25 GNDDIG 6
BI 2 25
0 OHM 402 CH X2 MPAD
DEBUG
M1092048-001
QFN25
R107
25MHZ_SB_CLK 1 2 53 V_3P3_NS_CLK
32 IN
0 OHM 402
EMPTY RETAIL
1 R67 1 R80 RETAIL 1 R115
R98 10 KOHM 1 R75 10 KOHM 10 KOHM
NS_XTAL_X1 1 2 NS_XTAL_X1_R 1% 10 KOHM 1% 1 R114 1%
1% 10 KOHM
0 OHM 402 2 EMPTY 2 CH 1% 2 CH
R26 R105 402 2 CH 402 402
1 2 NS_XTAL_X2 1 2 NS_XTAL_X2_R 402 2 CH
402
0 OHM 5% 0 OHM 402 53 SOC_NS_CLKREQ_N
402 EMPTY
Y0
25 MHZ 53 SPARE_NS_CLKREQ_N
XTAL
1 3
53 NS_CKPWRGD_PD_N
C68 1 2 4 1
C78
A 6.8 PF
+/-0.5PF M1085687-001
6.8 PF
+/-0.5PF 53 NS_SCLK A
50 V 50 V
NPO 2 SM 2 NPO
402 402
XTAL_25MHZ_BASE 53 NS_SDATA

ZZ_6
I194
M1115898-001 IC Y0 XTAL,25MHZ,15PPM,8PF,3.2X2.5MM XTAL_25MHZ_KDS
ZZ_7
I193
M1085687-001 IC Y0 XTAL,25MHZ,15PPM,8PF,3.2X2.5MM XTAL_25MHZ_TXC
M1115904-001 IC Y0 XTAL,25MHZ,15PPM,8PF,3.2X2.5MM XTAL_25MHZ_NDK
ZZ_8
I192

PAGE
1.03
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MARGIN: V_SOCPHY,V_SOC1P8, V_DRAM1P8

D D
C C
REMOVED FOR RETAIL FAB
B B
A A

PAGE
1.03
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8 7 6 5 4 3 2 1
MONITOR: V_SOC1P8, V_SOCPHY, V_12P0_SOC, V_DRAM1P8

D D
C C
B B
A A

PAGE
1.03
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8 7 6 5 4 3 2 1
MONITOR: M.2, CFEXPRESS

D D
C C
B B
A A

PAGE
1.03
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DEBUG: VR HEADERS, TEST POINTS, CONNECTORS

V_12P0_SOC V_3P3STBY_SOC V_3P3_GATED
D V_12P0_SOC
3.3V TYP FV
25MA MAX RATED
D
DEBUG_TP DEBUG_TP DEBUG_TP
TP17 TP10 TP1 DEBUG
1 1 1 DEBUG D5
SM SM SM R187
1 2 V_12P0_LED_R 1 2
12.7 KOHM 1%
V_SOC1P8 V_5P0 V_SOCPHY V_FUSE 402 CH GREEN
DEBUG_TP SM
TP5 LED
TP16 1
TP2 TP15
1 1 1
SM V_12P0_SOC
SM SM SM
DEBUG
V_SOC DEBUG D6
V_BAT
DEBUG_TP
DEBUG_TP DEBUG_TP DEBUG_TP R250
TP8 TP0 TP6 1 2 CPUGFX_PWRGD_LED_R 1 2 CPUGFX_PWRGD_LED_R_D
TP3 1 1 1 12.7 KOHM 1%
1 402 CH GREEN
SM 3 DEBUG
SM SM SM SM LED
C V_CPUCORE
U58
FET C
V_GFXCORE 51 50 44 38 32 IN VREG_PWRGPAB_CPUGFX_PWRGD 1
DEBUG_TP
DEBUG_TP 2 SOT23-3
TP9 TP19
1
1
SM SM
V_MEMIO V_MEMPHY V_DRAM1P8
TP4 TP14 TP230
1 1 1 V_3P3STBY_SOC
SM SM SM
AARDVARK/MPS I2C HEADER R169
0 OHM 5% V_5P0
J14 402 EMPTY
2X2HDR
52 44 38 32 30 SMBUS_CLK 1 2 R173
IN SMBUS_DATA 3 4 I2C_2X2_HDR_VDD 1 2
52 44 38 32 30 BI
B 0 OHM 5% B
SM 402 EMPTY
EMPTY
J4
2X3HDR
28 27 26 25 24 23 22 21 20 19 G6_TMS 1 2 G6_TCK 19 20 21 22 23 24 25 26 27 28
OUT G6_TDI 3 4 G6_TDO
OUT
28 OUT IN 19
NC 5 6
SM
HDR
DEBUG_HEADER
A A

PAGE
1.03
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8 7 6 5 4 3 2 1
LABELS AND MOUNTING

TOPSIDE BOARD LEVEL SHIELD BOTTOMSIDE BOARD LEVEL SHIELD
SHLD1 SHLD
SHLD2 D
D 1
SHLD_79P
41
SHLD
SHLD SHLD SHLD_84P
2 SHLD SHLD 42 1 SHLD SHLD 43
HEAT SINK MOUNTING HOLES 17 SHLD SHLD 57 16 SHLD SHLD 58
MEMIO/PHY/SOC HEATSINK MOUNTING PEMNUTS 20 SHLD SHLD 60 19 SHLD SHLD 61
STD STD VR_HEATSINK 22 SHLD SHLD 62 21 SHLD SHLD 63
MTG2 23 63 22 64
C MTG_HOLE
MTG3
MTG_HOLE
MTG6
SPACER_1P 24
SHLD
SHLD
SHLD
SHLD 64 23
SHLD
SHLD
SHLD
SHLD 65 C
NC9 9 NC9 9 1
EMPTY 27 SHLD SHLD 67 26 SHLD SHLD 68
GND=1,2,3,4,5,6,7,8 EMPTY X908259-001 28 SHLD SHLD 68 27 SHLD SHLD 69
GND=1,2,3,4,5,6,7,8 TH 29 SHLD SHLD 69 28 SHLD SHLD 70
VR_HEATSINK 30 SHLD SHLD 70 29 SHLD SHLD 71
STD MTG7 31 SHLD SHLD 71 30 SHLD SHLD 72
MTG4
STD 32 SHLD SHLD 72 31 SHLD SHLD 73
MTG1 SPACER_1P 33 73 32 74
MTG_HOLE MTG_HOLE 1 SHLD SHLD SHLD SHLD
NC9 9 NC9 9 35 SHLD SHLD 75 34 SHLD SHLD 76
X908259-001 36 SHLD SHLD 76 35 SHLD SHLD 77
EMPTY EMPTY TH 37 SHLD SHLD 77 36 SHLD SHLD 78
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 38 SHLD SHLD 78 37 SHLD SHLD 79
40 SHLD 39 SHLD SHLD 81
40 SHLD SHLD 82
M1089500-003 41 SHLD SHLD 83
SM 42 SHLD SHLD 84
B BOARD_LEVEL_SHIELD M1089501-003 B
SM
BOARD_LEVEL_SHIELD
TOPSIDE INTELLIGENT LABEL TARGET BOTTOMSIDE LABEL TARGET (BARCODE ONLY)

LB1 LB2
GND PADS FOR HEATSINK ALIGNMENT PINS LABEL LABEL
1
1 1 M1023566-331 M1023564-301
DB1001 DB1002 25P55X6P5_TARGET 6P5X6P5_TARGET

ZZ4
I43
M1090324-006 FR4 PCB1 PCB,TOLEDO SOC,10LAYERS,GI,FR4,FAB E PCB_GI USES DEBUG NETLIST
ZZ179
I42
M1125041-002 FR4 PCB1 PCB,TOLEDO SOC,10LAYERS,OSP,FR4,DEBUG RF, FAB E PCB_OSP_DEBUG_RF USES DEBUG NETLIST
ZZ13
I41
M1128163-001 FR4 PCB1 PCB,TOLEDO SOC,10LAYERS,OSP,FR4,RETAIL RF,FAB E PCB_OSP_RETAIL_RF USES RETAIL NETLIST
ZZ44
I40
M1128164-001 FR4 PCB1 PCB,TOLEDO SOC,10LAYERS,OSP,FR4,RETAIL NON-RF,FAB E PCB_OSP_RETAIL_NO_RF USES RETAIL NETLIST. INDUCTOR REMOVED BY LAYOUT
A
A
MICROSOFT PROJECT NAME PAGE CSA VER

PAGE
CONFIDENTIAL Toledo SoC 58/59 58/59 1.03
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM DEFINITIONS
BOM DEFINITION D
D BOARD_LEVEL_SHIELD POPULATES TOP AND BOTTOM BOARD LEVEL SHIELDS. POPULATES M.2 BOARD LEVEL SHIELD
COMMON ALL COMPONENTS WITH NO BOM PROPERTY
DEBUG COMPONENTS REQUIRED FOR BRING UP & DEBUG
DEBUG_HDT HDT-RELATED DEBUG COMPONENTS
DEBUG_TP DEBUG TEST HOOKS. POPULATE IF BUILDING BARE PCBAS
DEBUG_HEADER DEBUG HEADERS WITH HEIGHT CLEARANCE ISSUES WITH CHASSIS. POPULATE ONLY ON PCBAS NOT INTENEDED FOR USE IN A CONSOLE ASSEMBLY
DEBUG_SHUNT COMPONENTS WHICH ARE ON DEBUG BOARDS, BUT ARE REMOVED/SHORTED ON RETAIL
GDDR6_BASE DUMMY PLACE HOLDER FOR GDDR6/DRAM. NEVER USE THIS IN THE RECIPE FILE.
GDDR6_HYNIX STUFFS HYNIX GDDR6
GDDR6_SAMSUNG STUFFS SAMSUNG GDDR6
PCB_GI FAB TYPE: GOLD
PCB_HG FAB TYPE: HARD GOLD, RAISED PADS. FOR SOCKETED BOARDS
C PCB_OSP FAB TYPE: ORGANIC SOLDERABILITY PRESERVATIVE GREEN SOLDERMASK C
RETAIL COMPONENTS STUFFED FOR A RETAIL CONSOLE. DO NOT USE WITH DEBUG
RF STUFFS 2.4/5GHZ FILTERS FOR DESENSE MITIGATION
RTC_RETAIL RTC CIRCUIT IMPLEMENTATION FOR RETAIL BOARDS
RTC_XDK RTC CIRCUIT IMPLEMENTATION FOR XDK BOARDS
SOC_BASE DUMMY PLACE HOLDER FOR SOC. NEVER USE THIS IN THE RECIPE FILE.
SOC_EMPTY DOES NOT STUFF ARDEN
SOC_INCLUDE STUFFS ARDEN
SPI_FLASH_BASE DUMMY PLACE HOLDER FOR SPI FLASH. NEVER USE THIS IN THE RECIPE FILE.
SPI_FLASH_MACRONIX STUFFS MACRONIX SPI FLASH
SPI_FLASH_WINBOND STUFFS WINBOND SPI FLASH
B B
VR_FIXED SET ALL VRS TO FIXED VOLTAGES (NON-MARGINED). EXCLUDES V_MEMIO
VR_HEATSINK STUFFS PEMNUTS FOR MOUNTING VRM HEATSINK (BARE PCBAS ONLY)
INDUCTOR_CORE_BASE DUMMY PLACE HOLDER FOR HIGH POWER SOC INDUCTORS. NEVER USE THIS IN THE RECIPE FILE
INDUCTOR_CORE_CHILISIN STUFFS CHILISIN INDUCTORS FOR HIGH POWER SOC DOMAINS
INDUCTOR_CORE_EATON STUFFS EATON INUDCTORS FOR HIGH POWER SOC DOMAINS
INDUCTOR_CORE_SUNLORD STUFFS SUNLORD INUDCTORS FOR HIGH POWER SOC DOMAINS
VR_GFXCPU_BASE DUMMY PLACE HOLDER FOR GFX/CPU POWER STAGES. NEVER USE THIS IN THE RECIPE FILE
VR_GFXCPU_MP86955 STUFFS GFX/CPU POWER STAGES WITH THE MP86955 (8" WAFER QUAL)
VR_GFXCPU_MP86965 STUFFS GFX/CPU POWER STAGES WITH THE MP86955 (12" WAFER QUAL)
XTAL_25MHZ_BASE DUMMY PLACE HOLDER FOR 25MHZ XTAL. NEVER USE THIS IN THE RECIPE FILE
XTAL_25MHZ_KDS STUFFS 25MHZ XTAL WITH THE KDS PART
XTAL_25MHZ_NDK STUFFS 25MHZ XTAL WITH THE NDK PART
XTAL_25MHZ_TXC STUFFS 25MHZ XTAL WITH THE TXC PART
A
HDMI_LOAD_SWITCH_BASE DUMMY PLACE HOLDER FOR HDMI LOAD SWITCH. NEVER USE THIS IN THE RECIPE FILE A
HDMI_LOAD_SWITCH_DIODES STUFFS HDMI LOAD SWITCH WITH DIODES INC QUAL PART
HDMI_LOAD_SWITCH_ST STUFFS HDMI LOAD SWITCH WITH STMICRO QUAL PART
HDMI_LOAD_SWITCH_TI STUFFS HDMI LOAD SWITCH WITH TEXAS INSTRUMENTS QUAL PART
VR_MEMSOC_BASE DUMMY PLACE HOLDER FOR MEMIO/MEMPHY/SOC POWER STAGES. NEVER USE THIS IN THE RECIPE FILE
VR_MEMSOC_MP86910C STUFFS MEMIO/MEMPHY/SOC POWER STAGES WITH THE MP86910C (8" WAFER QUAL)
VR_MEMSOC_MP86912C STUFFS MEMIO/MEMPHY/SOC POWER STAGES WITH THE MP86912C (12" WAFER QUAL)
MICROSOFT PROJECT NAME PAGE CSA VER

PAGE
CONFIDENTIAL Toledo SoC 59/59 59/59 1.03
8 7 6 5 4 3 2 1

Toledo - Soc - Fabe - Retail (Series X pt2)

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Toledo - Soc - Fabe - Retail (Series X pt2)

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8 7 6 5 4 3 2 1

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: PCIEX, CLOCKS

MXXXXXXX-001 MATL REF_DES DESCR. BOM PROPERTY

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: AUDIO, VIDEO

NC DP1_AUX_P BK11 DP1_AUX_P DP0_AUX_P BN49 SOC_DDC_CLK 30

NC 3V3_DP1_HPD BM6 3P3V_DP1_HPD 3P3V_DP0_HPD BT5 DP0_HPD 30

HDMI TO DP SIGNAL MAPPING

A TMDS DATA1 - DP LANE 1 - DP0_TX1_N A

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: POWER: MEMIO,MEMPHY,SOC,MISC

PROVIDED A RIPPLE VOLTAGE REQUIREMENT OF <30MV PK-PK

M1090982-001 BGA2963 PROJECT NAME PAGE CSA FAB VER

SOC: POWER: GFXCORE

M1090982-001 BGA2963 M1090982-001 BGA2963

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: POWER: CPUCORE

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: POWER: VSS

M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: POWER: VSS

M1090982-001 BGA2963 M1090982-001 BGA2963 M1090982-001 BGA2963

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: POWER: VSS

M1090982-001 BGA2963 M1090982-001 BGA2963

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: MEMORY: PARTITION A & B

19 A_CK_P BD47 A_CK_P 20 B_CK_P AP49 B_CK_P

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: MEMORY: PARTITION C & D

21 C_CK_P AC48 C_CK_P 22 D_CK_P N48 D_CK_P

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: MEMORY: PARTITION E & F

23 E_CK_P K39 E_CK_P 24 F_CK_P J24 F_CK_P

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: MEMORY: PARTITION G & H

25 G0_DQ15 D13 G0_DQ15 G1_DQ15 D5 G1_DQ15 25 26 H0_DQ15 R4 H0_DQ15 H1_DQ15 V1 H1_DQ15 26

25 G_CK_P K11 G_CK_P 26 H_CK_P W11 H_CK_P

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: MEMORY: PARTITION I & J

MICROSOFT PROJECT NAME PAGE CSA FAB VER

SOC: DEBUG, SB SIGNALS, VOLTAGE SENSE

ANATSTOUT_P BE14 ANATSTOUT_P

32 DBREQ_L BL3 DBREQ_N THERMDA BK46 THERMDA

MICROSOFT PROJECT NAME PAGE CSA FAB VER

V_GFXCORE V_GFXCORE V_GFXCORE

C V_GFXCORE V_GFXCORE V_GFXCORE C

V_GFXCORE V_GFXCORE V_GFXCORE

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL A: 8GB

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL B: 16GB

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL C: 8GB

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL D: 16GB

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL E: 16GB

MICROSOFT PROJECT NAME PAGE CSA FAB VER

MEMORY: GDDR6 CHANNEL F: 16GB