APB Divider

• The APB Divider determines the relationship between

the processor clock (CCLK) and the clock used by
peripheral devices (PCLK).
• The APB Divider serves two purposes:
• The first is to provides peripherals with desired PCLK
via APB bus so that they can operate at the speed
chosen for the ARM processor
• The second purpose of the APB Divider is to allow
power savings when an application does not require
any peripherals to run at the full processor rate.
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• Default condition at reset is for the APB bus
to run at one quarter speed.
• Register description:
• APBDIV Controls the rate of the APB clock in
relation to
• The processor clock.
• R/W
• Reset Value, ADD.-0xE01F C100
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• APB Divider register (APBDIV - address 0xE01F C100) bit
description
• Bit Symbol Value Description Reset
• value
• 1:0
• 00 APB bus clock is one fourth of the processor clock.
• 01 APB bus clock is the same as the processor clock.
• 10 APB bus clock is one half of the processor clock.
• 11 It has not affect on the APB clock
• 7:2 - - Reserved, user software should not write ones to reserved
 Power Control
• The LPC2141/2/4/6/8 supports two reduced
power modes: Idle mode and Power-down
mode.
• In Idle mode, execution of instructions is
suspended until either a Reset or interrupt
occurs.
• Peripheral functions continue operation during
Idle mode and may generate interrupts to cause
the processor to resume execution
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• Idle mode eliminates power used by the processor itself, memory
systems and related controllers, and internal buses
• In Power-down mode, the oscillator is shut down and the chip
receives no internal clocks.
• The processor state and registers, peripheral registers, and internal
SRAM values are preserved throughout Power-down mode and
the logic levels of chip pins remain static.
• The Power-down mode can be terminated and normal operation
resumed by either a Reset or certain specific interrupts that are
able to function without clocks.
• Since all dynamic operation of the chip is suspended, Power-down
mode reduces chip power consumption to nearly zero.
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• Register Description:

Register Use Reset Address

Value

PCON Power Control Register. This register 0x00 0xE01F

contains C0C0
control bits that enable the two
reduced power
operating modes of the
microcontroller
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Register Use Reset Address

Value

PCONP Power Control for Peripherals Register. 0x00 0x001817BE