MSDAP

Introduction
■ Digital audio signal processing has become increasingly popular in
multimedia systems, largely thanks to the advent of general digital signal
processor (DSP) chips and high-precision oversampling A/D and D/A
converts [1, 2]. For portable and home entertainment audio systems,
however, the general-DSP-chip-based solution might be too costly and
consume too much power, at least in near years. Then a low-cost and
lowpower solution for this purpose should be sought. By carefully
examining digital audio processing applications, we believe there is a
possibility to develop a tiny digital audio processor chip that is capable of
performing several basic audio processing functions with much improved
performance/(cost.power) ratios over a general DSP chip.
Algorithm
■ The FIR digital filtering involves the following linear convolution. ], the MSDAP
will focus on the FIR digital filtering – a fundamental and computation-intensive
task
 
y(n) = åh(k )*x(n - k )
where x(n) and y(n) are input and output audio sequences, and h(k) are filter
coefficients with the filter order N. (where N here is 512).
Using this algorithm eliminates the use of a barrel shifter. A barrel shifter is a digital
circuit that can shift a data word by a specified number of bits. Implementing
convolution in the straightforward way would need shifting by different number of
bits each time and hence would require a barrel shifter. Barrel shifters are very
hardware intensive and slow. The innovative approach taken by this algorithm is the
use of a single bit shift every time. This greatly reduces the area and complexity of
the designed chip.
Block Diagram

Sclk,Dclk
Start,Reset_n
Input File Frame
InputL,InputR

Controller MSDAP

Output File InReady,OutReady

OutputL,OutputR
Signal Formatting
■ The input signals sent to the chip are each of 16 bits and the output signals from the
chip are 40 bits each.  
■ Rj Value : Rj values are received bit by bit starting from 0th bit (MSB) to 15th bit
(LSB).
15 14   13 12 11 10 9 8 7 6 5 4 3 2 1 0

  Unused/ 0 Padded bits MSB Rj data LSB

■ Coefficient Value : Coefficient values are received bit by bit starting from MSB to
LSB. The 7th bit the sign bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Unused/ 0 Padded bits Sign bit MSB Coefficient data LSB

■ Input Samples : Input samples are received bit by bit starting from MSB to LSB.
The MSB itself is the sign bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MSB data LSB

■ Output Samples : Input samples are received bit by bit starting from MSB to LSB.
The MSB is the sign bit.

39 38 37 36 35 34 …. …. …. …. …. 4 3 2 1 0

MSB(sig                             LSB
n bit)
Input pins
■ Asynchronous Pins
– 1) Start – When Start is set low, the chip begins to initialize.(Low)
– 2) Reset_n –When Reset_n is set low, the chip begins to reset. (Low)
■ Clock Pins
– 1) Sclk – provides the timing reference for the internal and control signals, as well as the
output samples.(26.88MHz)
– 2) Dclk - provides the timing reference for the input samples.(768KHz)
■ Data Input Pins
– 1) Frame –Frame aligns the serial coefficients, input and output samples.(High)
– 2) InputL –InputL carries the left channel coefficients and audio samples in serial form.
– 3) InputR –InputR carries the right channel coefficients and audio samples in serial form.
Output pins
■ Control Pins
– 1) InReady – InReady is set high when the chip is ready to receive Rjs, Coefficients or
Input samples; otherwise it is set low.
– 2) OutReady –OutReady is set high when the chip is transmitting output samples;
otherwise it is set low.

■ Output Pins
– 1) OutputL –OutputL carries the left channel serial output samples.
– 2) OutputR -OutputR carries the right channel serial output samples.
Finite State Machine (FSM) diagram
■ Internal State Diagram of the MSDAP chip
FSM Methodology
■ STATE 0 (Initialization)
When Start is low, the chip begins initialization by clearing all the memories and registers. After this, the
chip enters State 1. 
■ STATE 1 (Waiting to receive Rj)
Here InReady is set high and if the Frame is detected to be high, then the chip enters State 2.
■ STATE 2 (Reading Rj)
Here Rj values are read and InReady is kept high. After all Rj values have been read, the rj_read flag
becomes high and the chip enters State 3.
■ STATE 3 (Waiting to receive coefficients)
Here InReady is set high and if the Frame is detected to be high, then the chip enters State 4.
■ STATE 4 (Reading Coefficients)
Here coefficient values are read and InReady is kept high. After all coefficient values have been read, the
coeff_read flag becomes high and the chip enters State 5.
■ STATE 5 (Waiting to receive data)
Here InReady is set high and if the Frame is detected to be high, then the chip enters State 6
and if Reset_n is detected to be low, the chip enters State 7.
■ STATE 6 (Working)
Here, the chip reads al the input samples, then goes through with the computation and gives
the computed data, while InReady remains high. If Reset_n is detected to be low, the chip
enters State7 and if the chip detects 800 continuous zero input samples, then it enters State 8.
■ STATE 7(Clearing)
Except for Rj and coefficients, all other input or output samples stored in the memory are
cleared to zero. If Reset_n is detected to be zero again during this process, the chip will
restart the process. After resetting, the chip goes back to State 5. 
■ STATE 8(Sleeping)
Here, the chip goes to sleep mode while the InReady is still high, and if a non-zero input
sample is detected on either channel, the chip goes to State 6. Also, if a low is detected on
Reset_n, then the chip enters State 7.
Simulation Results
State 0 -> 1 -> 2
State 2 -> 3 -> 4
State 4 -> 5 -> 6
State 6 -> 8 -> 6
State 6 -> 7 -> 5 -> 6
State 8 -> 6 -> 7 -> 5 -> 6
Complete Waveform
Input data transition format: Parallel

Output data transition format: Serial

Asynchronized Reset
Thank You