EECS 527 Paper Presentation

© KLMH
High-Performance Global Routing
with Fast Overflow Reduction
- by Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang

Presented by Yaoyu Tao

Department Electrical Engineering and Computer Science
University of Michigan, Ann Arbor
10/2011

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 1

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 EECS 527 Paper Presentation

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 Outlines
 Introduction
 Problem Formulation
 Routing Methodology
• Pre-routing
• Initial Iterative Monotonic Routing
• Iterative Forbidden-Region Rip-up/Rerouting (IFR)
• Layer Assignment

 Experimental Results
 Q&A

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 2

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 Introduction

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• State-of-the-art routing techniques
 maze routing
A*-search routing
pattern routing
monotonic routing
multi-commodity flow
integer linear programming (ILP)
 Not clear on their capability to handle
the upcoming design challenges

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 3

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 Introduction

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 State-of-the-art Routers
 Based on INR (iterative negotiation-based
rip-up/rerouting)
 INR becomes the main stream due to its great ability
to spread out congestion as well as to reduce the
overflow
 Lagrange Relaxation (IR) mathematical basis
to improve the INR

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 4

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 Introduction

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 Developments on this paper
 New global router - NTUgr, that contains 3 major
steps: pre-routing, initial routing and enhanced INR
 New techniques in pre-routing
• Congestion-hotspot historical cost pre-increment
• Small bounding-box area routing
 Enhanced INR
• Multiple forbidden regions expansion
• Critical subnets rerouting selection
• Look-ahead historical cost increment

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 5

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 Problem Formulation

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 Routing & Goal
 Routing region - partitioned into global cells and a 2D or
3D routing graph composed of nodes (global tile nodes)
and edges (global edges)
 Each global edge is associated with a capacity
 Objectives of global routing – Minimize the total overflow
 Prioritized order of ISPD’08
• Total overflow
• Maximum overflow
• Weighted total wire length

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 6

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 Some basics

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 Global tile node & global edge
 Overflow: the amount of routing demand
that exceeds the given capacity

Global edge
Tile boundary

Global tile
Tile
node
7

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing

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 Some basics

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 State-of-the-art INR
 Proposed in PathFinder [McMurchie and Ebeling, FPGA’95]
 Spreads the congested wires iteratively
 At the (i)-th iteration, the cost of a global edge e:

(be  he( i ) )  pe

 h ( i 1)
1 if e has overflow
be: base cost of using e, he   (i 1)
(i ) e

pe: # of nets passing e,  he otherwise

he(i): historical cost on e,
INR may get stuck as the number of iterations increases

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing

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 Routing Methodology – Flow Chart

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 Flow of the global router
 Three new techniques
 2nd place of ISPD 2008 Global Routing Contest
3D
3DBenchmark
Benchmark

3D Prerouting
Prerouting
2D
3D 2Dcapacity
capacitymapping
mapping

Enhanced Initial
InitialRouting
Routing
Enhanced2D
2Drouting
routing
Iterative
IterativeForbidden-region
Forbidden-region
2D 3D
2D 3Dlayer
layerassignment
assignment Rip-up/rerouting
Rip-up/rerouting(IFR)
(IFR)
3D
3Drouting
routingresult
result

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 9

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 Routing Methodology - Prerouting

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3D
3DBenchmark
Benchmark

Prerouting
Prerouting
3D 2D
3D 2Dcapacity
capacitymapping
mapping

Initial
InitialRouting
Routing
Enhanced
Enhanced2D
2Drouting
routing

Iterative
IterativeForbidden-region
Forbidden-region
2D 3D
2D 3Dlayer
layerassignment
assignment Rip-up/rerouting
Rip-up/rerouting(IFR)
(IFR)

3D
3Drouting
routingresult
result

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 10

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 Routing Methodology - Prerouting

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 Pre-routing
 Congestion-hotspot Historical Cost Pre-increment
• Mainly for difficult routing instances, e.g., ISPD’07 newblue3 circuit
• Handle with high pin density
• Pre-increment the historical cost he, in cost function (be + he) ・
pe
• For ith global edges lying around the high-pin-density tiles
before going into the INR procedures
• Achieve the least 31024 overflows for newblue3 ever
in the literature

 Small Bounding-box Area Routing

 First route the subnets with smaller bounding-box areas
since they have less flexibility

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 11

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 Routing Methodology – Initial Iterative Monotonic
Routing

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3D
3DBenchmark
Benchmark

Prerouting
Prerouting
3D 2D
3D 2Dcapacity
capacitymapping
mapping

Initial
InitialRouting
Routing
Enhanced
Enhanced2D
2Drouting
routing

Iterative
IterativeForbidden-region
Forbidden-region
2D 3D
2D 3Dlayer
layerassignment
assignment Rip-up/rerouting
Rip-up/rerouting(IFR)
(IFR)

3D
3Drouting
routingresult
result

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 12

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 Routing Methodology – Initial Iterative Monotonic
Routing

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 Initial Iterative Monotonic Routing
 First stage that completes all subnets in the whole chip
 Monotonic paths: this stage stops when the overflow reduction
at the (i+1)-th iteration is less than 5% from the i-th iteration

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 13

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 Routing Methodology - IFR

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3D
3DBenchmark
Benchmark

Prerouting
Prerouting
3D 2D
3D 2Dcapacity
capacitymapping
mapping

Initial
InitialRouting
Routing
Enhanced
Enhanced2D
2Drouting
routing

Iterative
IterativeForbidden-region
Forbidden-region
2D 3D
2D 3Dlayer
layerassignment
assignment Rip-up/rerouting
Rip-up/rerouting(IFR)
(IFR)

3D
3Drouting
routingresult
result

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 14

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 Routing Methodology - IFR

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 15

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 Routing Methodology - IFR

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 Modified pe in IFR
 Pe is usually set as de/ce
 In proposed IFR

 Multiple Forbidden-Regions Expansion

 Identify the congested regions, called multiple forbidden regions
expansion
 Forbidden Region: Introducing overflows in this region is almost
forbidden, or it would incur huge cost penalty
 Three phases for multiple forbidden regions construction in IFR
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 16

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 Routing Methodology - IFR

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 17

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 Routing Methodology - IFR

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 Multiple Forbidden-region Construction at the first phase

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 18

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 Routing Methodology - IFR

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 Second Phase
 Invoked when the number of overflows in the first phase stops
decreasing and gets stuck at local optimal solution
 New technique: Region Propagation Leveling (RPL)
 “Inherit” all forbidden regions at the previous iterations and then
expands these forbidden regions simultaneously
 Avoids the local optima solutions in the first phase

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 19

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 Routing Methodology - IFR

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 Effects of RPL

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 20

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 Routing Methodology - IFR

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 Third Phase
 Starts when the current number of overflows is less than 0.5%
of the total overflows after the initial iterative monotonic routing
 Final expansion – expand the forbidden region
to the entire routing graph to quickly reduce the remaining overflows
 Why? Because INR becomes less effective in reducing the
overflows when the total overflows become smaller

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 21

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 Routing Methodology - IFR

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 Comparisons of Congested Regions

　 BoxRouter NTHU-Route 1.0 NTUgr (Ours)

Congested
Terminology Box Forbidden region
region
Shape Rectangular Rectangular Rectilinear
# of regions Single box Single region Multiple regions
Performing Performing
Selecting
Objective progressive different cost
rerouting nets
ILP functions
Simultaneou
No No Yes
s expansion

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 22

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 Routing Methodology – Critical Subnets Rerouting
Selection

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 New speed-up scheme into IFR – Critical Subnets rerouting
selection
 Reduce the number of rerouting subnets in each iteration
 Iterative rip-up/rerouting takes the most run-time,
thus the key for speed-up is to reduce the number of rerouting
subnets in each iteration
 Only critical subnets are ripped-up and rerouted in IFR
 Criterion for a critical subnet n, S is a constant and e is a global
edge passed by n

 In this paper, S is set to be -1 and obtain about 1.21x speedup

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 23

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 Routing Methodology – Look-ahead Historical Cost
Increment

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 Recall: main advantage of INR is the great ability to spread out
congestion (overflows)
 he Update scheme for most state-of-the-art routers, where K is a
constant, and ce and de represent the capacity and demand of e

 Conventional algorithm gets stuck in local optima solutions

 Why? Because it performs less effective as the number of iterations
increases and cannot minimize the overflows but just exchange
the overflow regions instead

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 24

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 Routing Methodology – Look-ahead Historical Cost
Increment & Layer Assignment

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 New updating scheme

 N > o represents a positive integer

 Not only increase the historical cost on the global edges with
overflows, but also on those near-overflow global edges
 In this paper, N = K = 1, improves the quality of the router
 Layer Assignment: 2-D to 3-D in non-decreasing order
of their wire length
 In this paper, layer assignment prefers the wire and via sharing

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 25

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 Experimental Results

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 NTUgr in C++ on 2.8GHz AMD Opteron Linux workstation
with 12 GB memory
 Comparisons with state-of-the-art global routers in literature
 ISPD’07 and ISPD’08
 Proposed NTUgr obtains the best routing solutions for the most
difficult instance, newblue3 (with only 31024 overflows) and
newblue4 (with only 142 overflows)
 High-quality results for the ISPD’07 and ISPD’08 benchmarks
for both overflow and runtime

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 26

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 Experimental Results

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 Achieved 1.94X speed up and better overflow reduction
with similar total wire length

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 27

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 Experimental Results

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 3-D ISPD’07 Results

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 28

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 Experimental Results

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 3-D ISPD’08 Results

The best solution

in the literature!

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 29

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 EECS 527 Paper Presentation

© KLMH
Thanks!

Q&A

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing 30

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