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Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16
HMOS technology Faster speed, Higher Mb
packing density Virtual memory space 240 bytes = 1 Tb
16 bit processors 40/ 48/ 64 pins Floating point hardware
Easier to program Supports increased number of addressing
Dynamically relatable programs modes
Processor has multiply/ divide arithmetic
hardware Intel 80386
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 2
multiplexed Intel 8085 (8 bit processor)
Microprocessor Functional blocks
Dedicated Adder to
generate 20 bit address
Segment
Registers
16-bit
9
11
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
16-bit
12
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
16-bit
13
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
16-bit
14
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
16-bit
15
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to 6
bytes of instruction code are
pre fetched from the
memory ahead of time.
16
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 17
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
AL in this case contains the low order byte of the word, and
AH contains the high-order byte.
18
8086 Microprocessor
Architecture Execution Unit (EU)
19
8086 Microprocessor
Architecture Execution Unit (EU)
Example:
20
8086 Microprocessor
Architecture Execution Unit (EU)
21
8086 Microprocessor
Architecture Execution Unit (EU)
22
8086 Microprocessor
Architecture Execution Unit (EU)
23
8086 Microprocessor
Architecture Execution Unit (EU)
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 1 1 1 1 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2
into 4 groups
O D IF TF S Z AF P C
F F F F F F
AD0-AD15 (Bidirectional)
Address/Data bus
MN/ MX
MINIMUM / MAXIMUM
TEST
READY
RESET (Input)
CLK
33
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
Pins 24 -31
35
8086 Microprocessor
Pins and Signals Maximum mode signals
36
8086 Microprocessor
Pins and Signals Maximum mode signals
37
8086 Microprocessor
Pins and Signals Maximum mode signals
38