Arizona State University

EEE 598: Neuromorphic Computing Hardware Design

Final Project Presentation

H/W implementation of SNN for Handwritten Digit

Classification
Group members
Rai, Nayyar, Venkataramanaiah

01/24/2022
 Arizona State University

Introduction of Group Members

 Vivek Rai
– RTL, Testbench, APR
 Charanjit Nayyar
– Software model, Primetime
 Shreyas K Venkatarmanaiah
– RTL, Software model, APR

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Motivation of Project
 Fewer hardware implementations of SNN

 Power efficient neuromorphic hardware

– No multipliers

 SNNs are a more accurate model of biological neural networks

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Relevant Works and Proposed Project

 Unsupervised Learning of Digit Recognition Using Spike –Timing
Dependent Plasticity by Diehl & Cook[1]
– Lateral Inhibition, Adaptive threshold, STDP

 This project is a hardware implementation of SNN architecture proposed

by Diehl & Cook[1] for classification.

 Time multiplexed hardware implementation to reduce the area

[1] Diehl, Peter U., and Matthew Cook. "Unsupervised learning of digit recognition using spike-timing-
dependent plasticity." Frontiers in computational neuroscience 9 (2015): 99.

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Neural Network Algorithm

 The intensity values of the

28 x 28 pixel MNIST image
are converted to Poisson-
spike trains as input to
excitatory neurons.
 One to one connections
between Excitatory and
Inhibitory neurons.
 Lateral Inhibition
Fig.1: Network Architecture [1]

[1] https://github.com/peter-u-diehl/stdp-mnist
Diehl, Peter U., and Matthew Cook. "Unsupervised learning of digit recognition using spike-timing-dependent
plasticity." Frontiers in computational neuroscience 9 (2015): 99.
.
Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design
 Arizona State University

Hardware Implementation Scope

 400 excitatory neurons each having 12-bit synapse weights connecting
each pixel to neuron.

 Synapse weights:

Software Hardware Software Hardware

313600 400 160000 400

Double 12-bit fixed point Double 17-bit fixed point

Input to excitatory synapses Inhibitory to excitatory synapses

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Scope

 Hardware Architecture

Clk

rst
Membrane Weights
potential Top
threshold Memory Neurons
Ex. weights module
In. weights

Spike

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Neuron Model:
Fire
Spike_in
Neuron_sel

Ex_wt

Σ +
0
- Spike
In_wt en Vth

Integrate
Weight selection
Counter

Refractory Counter

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Membrane_V

Spike_train

Ex Ex
In In

Ex Ex
In In

Ex Ex

In In

Memory

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Membrane_V

Spike_train

Ex Ex
In In

Ex Ex
In In

Ex Ex

In In

Memory

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Membrane_V

Spike_train

Ex Ex SPIKE!
In In

Ex Ex
In In

Ex Ex

In In

SPIKE!
Memory

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Membrane_V

Spike_train

Ex Ex
In In

Ex Ex
In In

Ex Ex

In In

Memory

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Simulation results (Post Encounter Netlist)

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Comparison of software and hardware results

Hardware spike count plot for didgit-1

800

700

600

500
Spike Count

400

300

200

100

0
0 23 46 69 92 115138161184207230253276299322345368391

Neurons

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Handwritten digit 1

Obtained image from spike rate

Percentage of weighted spike counts
0.11

99.89

7 1

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Handwritten digit 28
Obtained image from spike rate
Percentage of weighted spike counts

9 6 4

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Handwritten digit 4
Obtained image from spike rate Percentage of weighted spike counts

9 4

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Handwritten digit 2
Obtained image from spike rate Percentage of weighted spike counts
2.21

34.02

52.24

11.39

1 2 3 5 6

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Impact of precision loss on accuracy

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Power and Area Reduction

Variation of gate counts for different bit lengths
Variation of Power for different bit lengths
0.3 600000

0.25 500000
Power in watts

0.2 400000

Gate count
0.15
300000
0.1
200000
0.05

0 100000
8 10 12 16 20 32
0
number of bits 8 10 12 16 20 32

Number of bits
Power Dynamic Power Leakage

2.17x reduction 2.5x reduction

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Encounter Layout

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Hardware Implementation Results

 Post-synthesis/-APR results
 Power (Reported by Prime time)
– 0.0351 W (0.035Pdyn +0.01Pleak)
 Area (Reported by Encounter)
– Gate count : 717781
– Cells: 219238
– Area : 0.50331 mm2
 Latency
– Total cycles : 7.84G cycles (for 10000 Images)
– Clock period : 1ns
– Total delay : 7.84s

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

Summary
 Key highlights
– Implementation of the entire network architecture in hardware
– Coherence between hardware and software classification

 Challenges:
– Analyzing the entirety of the MNIST dataset (60000)
– Processing 1184 (784 +400) inputs to the neuron
– Test-bench generation

 Future work
– Exploiting the sparsity of input image to reduce area and power
– Good Calibration of hardware

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design

 Arizona State University

References

1. Diehl, Peter U., and Matthew Cook. "Unsupervised learning of digit

recognition using spike-timing-dependent plasticity." Frontiers in
computational neuroscience 9 (2015): 99.
2. Seo, Jae-sun, et al. "A 45nm CMOS neuromorphic chip with a scalable
architecture for learning in networks of spiking neurons." Custom
Integrated Circuits Conference (CICC), 2011 IEEE. IEEE, 2011.
3. Maass, Wolfgang. "Networks of spiking neurons: the third generation of
neural network models." Neural networks 10.9 (1997): 1659-1671.
4. Goodman, Dan FM, and Romain Brette. “The brian simulator.” Frontiers
in neuroscience 3 (2009): 26.
5. Stimberg, Marcel, et al. "Equation-oriented specification of neural
models for simulations." Frontiers in Neuroinformatics 8 (2014): 6.

Venkataramanaiah, Rai, Nayyar EEE 598 Neuromorphic Computing Hardware Design