COMPUTER ORGANIZATION

COURSE: CYBER SECURITY

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Basic Operations on Memory Cell

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Memory classification
Memory is one of the most essential elements of a computing system because without it computer can’t perform simple tasks. Computer
memory is of two basic type – Primary memory(RAM and ROM) and Secondary memory(hard drive, CD,etc.). Random Access Memory
(RAM) is primary- volatile memory and Read Only Memory (ROM) is primary-non-volatile memory.

1. Random Access Memory (RAM) –

 It is also called as read write memory or the main memory or the primary memory.
 The programs and data that the CPU requires during execution of a program are stored in this memory.
 It is a volatile memory as the data loses when the power is turned off.
 RAM is further classified into two types- SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory).
 2. Read Only Memory (ROM) –
 Stores crucial information essential to operate the system, like the program essential to boot the computer.
 It is not volatile.
 Always retains its data.
 Used in embedded systems or where the programming needs no change.
 Used in calculators and peripheral devices.
 ROM is further classified into 4 types- ROM, PROM, EPROM, and EEPROM.

Types of Read Only Memory (ROM) –

1. PROM (Programmable read-only memory) – It can be programmed by user. Once programmed, the data and instructions in it
cannot be changed.
2. EPROM (Erasable Programmable read only memory) – It can be reprogrammed. To erase data from it, expose it to ultra violet
light. To reprogram it, erase all the previous data.
3. EEPROM (Electrically erasable programmable read only memory) – The data can be erased by applying electric field, no need
of ultra violet light. We can erase only portions of
the chip.
 Memory Cell

The memory cell is the fundamental building block of computer memory.

The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage
level) and reset to store a logic 0 (low voltage level).
Its value is maintained/stored until it is changed by the set/reset process.
The value in the memory cell can be accessed by reading it.
 Memory Cell

• Over the history of computing, different memory cell architectures have been used,
• Eg. core memory and bubble memory.
• Today, the most common memory cell architecture is MOS memory,
• MOS consists of metal–oxide–semiconductor (MOS) memory cells.
• Modern random-access memory (RAM) uses MOS field-effect transistors (MOSFETs) as flip-flops, along with
MOS capacitors for certain types of RAM.
• The SRAM (static RAM) memory cell is a type of flip-flop circuit, typically implemented using MOSFETs.
These require very low power to keep the stored value when not being accessed.

This is the
construction of
SRAM with 6
MOSFETs
 Memory Cell

• A second type, DRAM (dynamic RAM), is based around MOS capacitors. Charging and discharging a
capacitor can store a '1' or a '0' in the cell. However, the charge in this capacitor will slowly leak away, and
must be refreshed periodically. Because of this refresh process,
• DRAM uses more power, but can achieve greater storage densities.
• Non-volatile memory technologies including EPROM, EEPROM and flash memory use floating-gate memory
cells, which are based around floating-gate MOSFET transistors.

This is the construction

of DRAM with 1
MOSFETs 1 capacitor
 Combinational and Sequential Logic Circuits

Logic circuits without memory cells or feedback paths are called combinational,
their outputs values depend only on the current value of their input values.
They do not have memory. In computers, it allows to store both programs and data and memory cells are also used for
temporary storage of the output of combinational circuits to be used later by digital systems.
Logic circuits that use memory cells are called sequential circuits.
Its output depends not only on the present value of its inputs, but also on the circuits previous state, as determined by the
values stored on its memory cells.
These circuits require a timing generator or clock for their operation.
Computer memory used in most contemporary computer systems is built mainly out of DRAM cells; since the layout is
much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity.
Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value
must be constantly rewritten.
This is one of the reasons that make DRAM cells slower than the larger SRAM (Static RAM) cells, which has its value
always available.
That is the reason why SRAM memory is used for on-chip cache included in modern microprocessor chips.
 History of Computer Memory

• 1946 Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device (Williams tube) with 128 40-
bit words.
• It was operational in 1947 and is considered the first practical implementation of random-access memory (RAM).

• In that year, the first patent applications for magnetic-core memory were filed. Later practical magnetic-core memory
was developed by An Wang , and improved by Jay Forrester and Jan A. Rajchman in the early 1950s,
• Later commercialized with the Whirlwind computer in 1953.

• In 1960 Bell Labs developed Magnetic Bubble Memory

• Did not use long due to invention of semiconductor memory

CRT Storage device Magnetic Core Memory Magnetic Bubble Memory

 History….

Semiconductor memory began in the early 1960s with bipolar memory cells, made of bipolar transistors. While it
improved performance, it could not compete with the lower price of magnetic-core memory.
MOS memory cells
Intel 1103, a metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chip.
The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by
Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959,[11] enabled the practical use of metal–oxide–semiconductor
(MOS) transistors as memory cell storage elements, a function previously served by magnetic cores. The first modern
memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (PMOS) static
random-access memory (SRAM).

Magnetic Core Memory Magnetic Bubble Memory

 SRAM and DRAM
further..
• SRAM typically has six-transistor cells, whereas DRAM (dynamic random-access memory) typically has single-
transistor cells
• In 1965, Toshiba's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-
bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors.
• MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J.
Watson Research Center was working on MOS memory.
• While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that
storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS
transistor could control writing the charge to the capacitor.
• This led to his development of a single-transistor DRAM memory cell In 1967, Dennard filed a patent for a
single-transistor DRAM memory cell, based on MOS technology.

The two most common types of DRAM memory cells since the 1980s have been trench- capacitor cells and stacked-
capacitor cells] Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls
are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D
memory), where memory cells are stacked vertically in a three-dimensional cell structure. Both debuted in 1984,
when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory.
 SRAM and DRAM further..

Storage
The storage element of the DRAM memory cell is the capacitor. The charge stored in the capacitor degrades over time,
so its value must be refreshed (read and rewritten) periodically. The n MOS transistor acts as a gate to allow reading or
writing when open or storing when closed.
Reading
For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the n MOS transistor (3) which makes it
conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a
parasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line
will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the
voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers
at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten
after each read.
Writing
The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit
line. The word line activates the n MOS transistor (3) connecting it to the storage capacitor (4). The only issue is to
keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS
transistor (3).
Flip-flop
The flip-flop has many different implementations, its storage element is usually a Latch consisting of a NAND gate
loop or a NOR gate loop with additional gates used to implement clocking. Its value is always available for reading as
an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically
implemented using MOSFET transistors.
•SRAM & DRAM Advantages :

•Advantages of SRAM:
 The SRAM provides a large storage capacities on on-chip memories
 A typically the SRAMs have very low latency and high performance
(Latency is the time delay between sending a request to read/write a
memory byte/word and receiving the response after the request)
 It is very easy to design and interface compared with other memories

Advantages of DRAM:
 The storage capacity is very high

 It is a low cost and medium performance device.

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Memory Hierarchy

Q)Write how
following parameters
changes as we move
down this hierarchy?
a. Capacity
b. Cost per bit
c. Access Time
d. Frequency of
access by CPU
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 Essential Characteristics
needed in memory

• Memory plays a key role in determining the

performance of a computer.
• Hence memory should have following characteristics
– Large Size
– High Speed
– Lower Cost
• Its impossible to maximise all 3 parameters at the
same time.
• Hardware designers need to strike a balance
between these 3 parameters.

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Computer Bus

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 Memory Capacity
• Single memory cell has 1-bit capacity. 8 Bits make
one Byte. Half a Byte is known as a Nibble
• Usable max size of memory is determined by the size
of the address bus of the computer.
• Question - What is the number of memory locations
that can be used by a computer that generates 16-bit
addresses?
• Word length determines the capacity per memory
location. If the word length is 2 bytes in the above
example, what is the size of memory in kb?

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 Memory Capacity
•Word size
– The natural unit of organisation of memory.
• Number of Bytes
– For internal memory, this is typically expressed in terms of
bytes (1 byte 8 bits) or words.
– Common word lengths are 8, 16, and 32 bits.
– External memory capacity is also typically expressed in
terms of bytes.

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 Unit of Transfer
– For internal memory, the unit of transfer is equal
to the number of electrical lines into and out of
the memory module.
– This may be equal to the word length, but is often
larger, such as 64, 128, or 256 bits.

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• There is a three related concepts for internal memory:
– 1. Word
• It is the “natural” unit of organization of memory.
• The size of the word is typically equal to the number of bits used to
represent an integer and to the instruction length.
– 2.Addressable units
• In some systems, the addressable unit is the word.
• The relationship between the length in bits A of an address and the
number N of addressable units is:
2A = N
– 3. Unit of transfer
• For main memory, this is the number of bits read out of or written into
memory at a time.
• For external memory, data are often transferred in much larger units than
a word, and these are referred to as blocks.

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 Processor and Memory Interconnection

• Processor uses the address lines to specify the memory location involved in
a data transfer operation,
• Uses the data lines to transfer the data.
• At the same time, the control lines carry the command indicating a Read or
Write operation and whether a byte or a word is to be transferred.
Ref. Course Text

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 Speed of Memory

A useful measure of the speed of memory units is the time

that elapses between the initiation of an operation to transfer
a word of data and the completion of that operation. This
is referred to as the memory access time or latency.

Another important measure is the memory cycle

time, which is the minimum time delay required between the
initiation of two successive memory operations, for example,
the time between two successive Read operations. The
cycle time is usually slightly longer than the access time,
depending on the implementation details of the memory unit.

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Improvement of Memory speed

RAM Explained

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 Memory Organisation -Location
• Memory is internal and external to the computer 
• Internal memory 
– Internal memory is often referred as main memory 
– The processor requires its own memory inside the CPU. 
– They are called registers 
– Cache is another form of internal memory 
• External memory 
– External memory consists of peripheral storage devices. 
– They include disks, tapes that store and accessible by
the processor via IO controls 

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Organisation of Memory

Read this diagram with the next slide.

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 Organisation of Memory
• Memory cells are organized as an array (Rows and Columns)
inside a chip
• Each raw denotes a “Word” of Memory and each word is
connected to a common line called word line.
• Word line is connected to the decoder in the chip.
• Cells in each column are connected to a Read/Write circuit by
two bit lines,
• Read/Write circuits are connected to the data input/output
lines of the chip.
• During a Read operation, these circuits sense, or read, the
information stored in the cells selected by a word line and
place this information on the output data lines.
• During a Write operation, the Read/Write circuits receive
input data and store them in the cells of the selected word. 27
 Organisation of Memory
• The data input and the data output of each Read/Write circuit
are connected to a single bidirectional data line that connects
to the data lines (data bus) of a computer.
• Two control lines, R/W’ and CS, are provided. The R/W’
(Read/Write) input specifies the required operation, and the
CS (Chip Select) input selects a given chip in a multichip
memory system.
• It also needs two lines for power supply connections.

• What is the size of this memory and number of pins which we

discussed so far?

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 Organisation of Memory

• Consider a total size of 1024 bits size

memory array.
• Using a 8-bit word length data, draw the
memory organisation block diagram.
• How many pins are required for the chip
in total?
• Is there a way we can reduce the number
of pins by changing the design? Tip Consider
1024x1 arrangement.

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 Test Your Knowledge

Diagram given here is partly

completed to show how RAM
is connected to address and
data bus. Identify the
following parts and pins in the
diagram

a. Address Decoder
b. Address Lines
c. Data Lines
d. Chip Select
e. R/W’

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 Test Your Knowledge

Diagram given here is partly

completed to show how RAM
is connected to address and
data bus.
Identify the part in CPU where
each of the components get
connected.
a. Address Bus
b. Data Bus
c. R/W’

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 Test Question
• A memory chip has x number of address pins and n number of
data pins. What is the total memory capacity of this chip?

• Select the incorrect statement about computer memory

– A.Random Access Memory in any location can be reached in a fixed
amount of time after specifying its location.
– B. Primary memory is non-volatile
– C. Computers need non-volatile memory during the bootup process
– D. Virtual memory is special temporary arrangement to convert
Secondary Memory to Primary Memory.

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 Test Question
• Latency time of a particular memory is given as 125ns and the
cycle time is 150ns . What is the minimum time required to
perform 5 consecutive memory read operations in this
memory chip?
• How will this time change if its 5 consecutive Write
operations?

• Select the incorrect statements about computer memory

– A.SRAM is made using FlipFlops.
– B. DRAM is latency time is higher than SRAM
– C. DDR memory uses higher clock speeds than non-DDR
– D. DRAM cell occupies lager space on the chip compared to SRAM cell

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Memory data R/W Timing
Diagrams

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 Memory data R/W steps

1- Provide the addresses to pins.

– 2. Get CS .
– 3. Make W = 0 (R = 1)
– 4. Provide the data to pins .
– 5. Data will be written into SRAM on
the location identified by address

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 Question

Mark the Memory Access Time in this timing diagram

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Organisation of Memory 2

• The required 10-bit address

is divided into two groups of
5 bits each to form the row
and column addresses for the
cell array.
• A row address selects a row
of 32 cells, all of which are
accessed in parallel. But,
only one of these cells is
connected to the external
data line, based on the
column address.
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Timing Diagram of Row/Column
Addressing

 In DRAM, the 8 address

lines are latched accordingly
by the strobe of the RAS and
CAS signals.
 For example: To load a 16
bit address into the DRAM 8
bits of the address are first
latched by pulling RAS low,
then other 8 bits are presented
to A0-A7 and CAS is pulled
low

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 Address Decoding
•Address decoding refers to the way a computer system decodes
the addresses on the address bus to select memory locations in
one or more memory or peripheral devices.
•In 68000 processor, a 23-bit address bus permits 223 16-bit
words to be uniquely addressed.
•In full address decoding, each addressable memory location
corresponds to a unique address value on the address bus.
•In partial address decoding, part of address is decoded.
•In partial address decoding full memory capacity may not be
used.

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40
 DRAM Packaging Challenge
• It is difficult to pack large numbers of cells into single DRAM chips, with
normal numbers of address pins.
• Eg. A 64K-bit chip (64K x 1) must have 16 address lines and
• one data line, requiring 16 pins to send in the address and further pins for
other controls.
• When the number of pins is larger its very challenging to compress them
into a single IC with practical sizes and proportions
• Therefore, Multiplexing/demultiplexing reduces the number of pins.
• This goes one step further from previous block diagram
• Addresses are split & each half is sent through the same pins.
• Internally, the DRAM structure is divided into a square of rows and
columns.
– The first half of the address is called the row.
– The second half is called the column.

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 Overcoming DRAM Packaging Challenge
• In a 64K x 1 organization, the first half
address sent through pins A0–A7.
– Internal latches grab the first half Using
RAS (row address strobe)
• The second address half is sent
through the same pins
– Activating CAS (column address strobe),
latches the second half.
• 8 address pins, plus RAS & CAS make a
total of 10 pins
– Instead of 16, without multiplexing.
• There must be a 2-by-1 multiplexer outside
the DRAM chip to access a bit of data from,
both row & column address must be provided.

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Question- What is the main downside of this solution?
Detail Diagram of Address Multiplexing

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 Question

Using the given DRAM chip on left hand

side draw a block diagram on how to connect
them to create a 64KB memory bank

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Summary

https://www.youtube.com/watch?v=fpnE6UAfbtU

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THANK YOU

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