DESIGN OF COMPUTER

Block diagram of Digital Computer

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List of Registers for Computer

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Data Formats

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Instruction Format

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Memory Reference Instructions

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Demonstration of Branch to Subroutine
Instruction

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Register Reference Instructions

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 Shift Operations
Shift Right Operation
E

A16, A15,……….A1
Shift Left Operation
E

A16, A15,……….A1
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Input-Output Instructions

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 Input Subroutine
100: SKI
BUN 100
INP
BUN 100

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Computer Timings Signal

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Block Diagram of Control Logic

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 Execution of Instructions
• Logic design of computer
• Specify Micro operations for each machine
cycle with help of
– Timing signals to-t3
– Decoded operations q0-q7
– Status bits
• F=0 is fetch cycle
• F=1 is Execute cycle
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Fetch Cycle

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 Fetch Cycle
• The opcode in I is decoded during t3
• Next step depends on value of qi, i = 0…7 that
produces 1 in the output of the decoder
• If decoded output is a memory-reference
instruction, an operand may be needed.
• If not, the instruction may be executed during t3.
• BUN instruction (opcode 5), register reference
instructions and input-output instructions do not
need a second access to memory
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 Fetch Cycle
• When opcode is 0,1,2,3,4 is encountered, the
computer has to go to execute cycle to access
the memory again
F’(q0+q1+q2+q3+q4)t3 : F  1
• The BUN instruction does not need operand
from memory
• q5t3 : PC  B(AD)

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 Register Transfer Operations during Fetch
Cycle

Register reference instructions are recognized as q6 and

input output instructions from q7

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 Execute Cycle
Common Operations for Execute Cycle
F is equal to 1 during this cycle
Instruction to be executed are specified by qi = 0 to 7.
AND 0 (q value)
ADD 1
STO 2
ISZ 3
BSB 4

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Execution of Memory-reference Instructions

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Execution of Register-Reference Instructions

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