QUESTION 1

Complete the output Q and Q’ assuming you are using a positive-edge triggered
JK Flip Flop and the initial value is 0.
 QUESTION 2
Draw the output D flip flop for given input with positive edge and assume
the initial value is 0.
 QUESTION 3
Complete the output assuming you are using a positive-edge triggered JK Flip Flop
and the initial value is 0.
 QUESTION 4
Draw the output D flip flop for given input with positive edge and assume
the initial value is 0.
 QUESTION 5
Draw the output D flip flop for given input with positive edge and assume
the initial value is 0.
 QUESTION 6
Draw the output D flip flop for given input with positive edge and assume
the initial value is 0.
 QUESTION 7
Complete the output assuming you are using a negative-edge triggered JK Flip
Flop and the initial value is 0.
 QUESTION 8
Draw the output T flip flop for given input with positive edge and assume the initial
value is 0.
 QUESTION 9
Using SR Flip Flop (Active LOW), draw the output Q and Q’ of
the timing diagram and assume the initial value is 0.
SESSION JUN 2019
SESSION JUN 2019