Clock Tree Synthesis

Clock tree synthesis is a process of balancing clock skew and minimizing

inserting delay in order to meet timing, power requirements and other
constraints.
Deliver clocks to all sequential elements almost in same time, with
proper buffering, meeting given constraints(skew, insertion delay) with
out DRCs(max tran, max cap)
Why CTS?
• Within most VLSI circuits, data transfer between sequential elements
is synchronized by the process clock.
• Before CTS, all clock pins are driven by a single clock source having
high fanout and high load.
• CTS is the process of inserting buffers/inverters along the clock path of
the ASIC design to balance the clock delay to all clock inputs.
• In order to balance the skew and minimize insertion delay, CTSs is
performed.
Before CTS:

After CTS:
Clock skew:
Minimum difference in the arrival time of a clock signal at pins of two
different sequential elements.
Global Skew: Difference between shortest clock path delay and longest clock
path delay considering all sequential elements(in a clock domain).
Local skew: Difference between the arrival times of the clock signal at the
clock pin of two related flops of the same clock domain.
Positive skew: Capture clock comes late than launch clock. It improves setup
time but can lead to hold violation.
Negative skew: Capture clock comes early than launch clock. It improves hold
time but can lead to setup violation.
Beneficial/Useful skew: If clock is skewed intentionally to improve timing
violation.
Clock Latency/Insertion Delay
Source Latency: It is the time taken by the clock signal to
propagate from its ideal waveform origin point to the clock
definition point in the design.
Network Latency: It is the time taken by the clock signal to
propagate from clock definition point in the design to the
clock pin of the sequential device.