Types of clock Tree

1.H-tree: H tree because of balanced construction, it is easy to

reduce clock skew in the H tree clock structure. A disadvantages
to this that the foxed clock plan makes it difficult to fix register
placement. It is rigid in fine tuning the clock tree.
2.Balance tree: Makes it easy to adjust capacitance of the net to
achieve the skew requirements. But the dummy cells used to
balance the load increase area and power.
3.Spine tree: Arrangement makes it easy to reduce the skew. But it
is heavily influenced by process parameters, and may have
problems with phase delay.
4.Distributed driven buffer tree: Distributed buffers makes it easy
to reduce skew and power. Clock routing may not be an issue.
However, since buffering is customized, it maybe a less area
efficient method.
 Different types of delays
• Source delay/Latency
• Network delay/Latency
• Insertion Delay
• Transition delay/slew: Rise tome, fall time
• Path delay
• Net delay, wire delay, interconnect delay
• Propagation delay
• Phase delay
• Cell delay/Gate delay
• Intrinsic Delay
• Extrinsic delay
• Input delay
• Output delay
• Exit Delay
• Latency(Pre/Post CTS)
• Uncertainty(Pre/Post CTS)
• Unateness: postive unateness, negative unateness
• Jitter: PLL jitter, clock jitter
Gate Delay:
• Transistor within a gate take a finite time to switch. This means that a change on the
input of a gate finite time to cause a change on the output.
• Gate delay =function of(i/p transition time, Cnet+Cpin)
• Cell delay is also same as Gate delay.
Transition delay:
• It is also known as slew. It is defined as the time taken to change the state of the
signal. Time taken for the transition from the logic 0 to logic 1 and vice versa or time
taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa.
• Transition is the time it takes for the pin to change state.
Path delay: Path delay is also known as pin to pin delay. It is the delay from the input
pin of the cell to the output point of the cell.
Net delay: The difference between the time a signal is first applied to the net and the
time it reaches other devices connected to that net. It is due to finite resistance and
capacitance of the net. It is also know as wire delay. Wire delay= fn(Rnet, Cnet+Cpin)
Propagation delay: The time required for a signal to propagate from input to output.
For any gate it is measured between 50% of input transition of the corresponding
50% of output transition. Tpd=(Tphl+Tplh)/2
Intrinsic delay:
Intrinsic delay is the delay internal to the gate. Input pin of the cell to
output pin of the cell.
Extrinsic delay:
Same as the wire, net delay, interconnect delay.
Input delay:
Input delay is the time at which the data arrives at the input pin of the
block from external circuit with respect to the reference clock.
Output delay:
Output delay is time required by the external circuit before which the data
has to arrive at output pin of the block with respect to reference block.
Exit delay:
It is defined as the delay in the longest path(critical path)between clock
pad input and an output. It determines the maximum operating
frequency of the design.
Delay Insertion
• If the delay is more, instead of adding many buffers we can just add a delay cell of particular
delay value. Advantage is the size and also power reduction. But it has high variation, so
usage of delay cells in clock tree is not recommended.
Clock Tree Design Rule Constraints
• Max. Transition.
– The Transition of the clock should not be too tight or too relaxed.
– If it is too tight then we need more number of buffers.
– If it is too relaxed then dynamic power is more.
• Max. Capacitance.
• Max. Fanout.

Clock Tree Exceptions

• Non- Stop Pin
• Exclude Pin
• Float Pin
• Stop Pin
• Don’t Touch Subtree
• Don’t Buffer Nets
• Don’t Size Cells