PIC18 Interrupt System

Lecture 21
Interrupt Concepts
• A system normally
connects to I/O devices
• keyboard
• monitor
• mouse, etc.
• Processor needs to serve
I/O devices at
unpredictable times
(CPU does not know
when you are about to
hit a key)
Solutions
• Alternative 1: Polling
Every so often, processor checks each device to see if it has a request
• Takes CPU time even if no request is pending
• How does software know when to let the system poll?
• Alternative 2: Interrupts
Give each device a wire (interrupt line) that it can use to signal the processor
• When interrupt signalled, processor executes a routine called an interrupt service
routine (ISR) to deal with the interrupt
• No overhead when no requests pending
Interrupts Vs. Polling
• Imagine processor is like a director working in his office, and I/O
devices are guests
Polling is like the director who goes to open the door every period of time to
see if a guest is there.
 Interrupt is like when a guest comes, he knocks on the door. Director then
stops what he is doing and prepares to welcome the guest.
Interrupt Processing
• CPU is executing the main task
• An I/O device requests for service using an interrupt
• Based on the interrupt configuration and priority, CPU
decides if it allows that interrupt
• If yes, save all the status onto stack, run the interrupt
service routine to serve the I/O device
• When finish CPU reloads all
status before processing interrupt,
and continues the main task
• A higher priority interrupt
can interrupt the lower priority one. See table 11-1 (I.V.T)
Execution & Sources
Steps in executing
• Finishes (current instruction) & Saves address
• Jumps to I.V. T & then ISR until RETFIE
• Poping & back to Main
Sources of Interrupts
• Timer 0, 1, 2 & so on.
• External Interrupt RB0, RB1 & RB2
• USART  2 (receiver & Transmitter)
• PORTB-Change
• ADC and CCP
Interrupt Enabling
• BSF INTCON,GIE ; global interrupt enabling
• Setting Individual bits TMR0IE, INT0IE etc
• Setting PEIE (peripheral Interrupt Enable) for TMR1, 2, TX
• Fig 11-2
Timer Interrupts
• Timer flag raises when timer rolls over
• Keep monitoring TMRxIF, makes CPU tied-up
• BTFSS INTCON,TMR0IF
• Enabling timer interrupts can cause CPU to jump to
I.V.T
• TMRxIE: see table 11-5 & Fig 11-4
• Steps:
 In main program; initialize TMRx (e.g. timer or counter, values for
TMRxH & L, pre-scaling & post-scaling etc.)
 In main program; set TMRxIE followed by GIE bit
 In ISR at 08-17H or 18 to onwards; clearing IF & other important
tasks to be performed in case of interrupt happens.
 End with RETFIE; causes GIE to set again
• Note: see (prog-11-1 & 2)how to manage limited space of I.V.T